Searched refs:RCC_PLL1CFGR1_PLL1DIVM (Results 1 – 10 of 10) sorted by relevance
1668 …pRCC_OscInitStruct->PLL1.PLLM = ((cfgr_value & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_P… in HAL_RCC_GetOscConfig()2069 …MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_P… in RCC_PLL_Config()2219 …if ((*p_rcc_pll_cfgr1_reg & (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_PLL1DI… in RCC_PLL_IsNewConfig()
3187 …MODIFY_REG(*p_rcc_pll_cfgr1_reg, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1CFGR1_P… in HAL_RCCEx_PLLSSCGConfig()
311 pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; in SystemCoreClockUpdate()
368 pllm = (pllcfgr & RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos; in SystemCoreClockUpdate()
25354 #define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 refe… macro
26503 #define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 refe… macro
26261 #define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 refe… macro
25596 #define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 refe… macro
5196 MODIFY_REG(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM, M << RCC_PLL1CFGR1_PLL1DIVM_Pos); in LL_RCC_PLL1_SetM()5206 return (uint32_t)(READ_BIT(RCC->PLL1CFGR1, RCC_PLL1CFGR1_PLL1DIVM) >> RCC_PLL1CFGR1_PLL1DIVM_Pos); in LL_RCC_PLL1_GetM()
3638 …RCC->PLL1CFGR1, (RCC_PLL1CFGR1_PLL1SEL | RCC_PLL1CFGR1_PLL1BYP | RCC_PLL1CFGR1_PLL1DIVM | RCC_PLL1…