Searched refs:RCC_DCKCFGR_PLLDIVR_Pos (Results 1 – 4 of 4) sorted by relevance
10530 #define RCC_DCKCFGR_PLLDIVR_Pos (8U) macro10531 #define RCC_DCKCFGR_PLLDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001F00 */10533 #define RCC_DCKCFGR_PLLDIVR_0 (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000100 */10534 #define RCC_DCKCFGR_PLLDIVR_1 (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000200 */10535 #define RCC_DCKCFGR_PLLDIVR_2 (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000400 */10536 #define RCC_DCKCFGR_PLLDIVR_3 (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000800 */10537 #define RCC_DCKCFGR_PLLDIVR_4 (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001000 */
10485 #define RCC_DCKCFGR_PLLDIVR_Pos (8U) macro10486 #define RCC_DCKCFGR_PLLDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001F00 */10488 #define RCC_DCKCFGR_PLLDIVR_0 (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000100 */10489 #define RCC_DCKCFGR_PLLDIVR_1 (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000200 */10490 #define RCC_DCKCFGR_PLLDIVR_2 (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000400 */10491 #define RCC_DCKCFGR_PLLDIVR_3 (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00000800 */10492 #define RCC_DCKCFGR_PLLDIVR_4 (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos) /*!< 0x00001000 */
1690 …riphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); in HAL_RCCEx_GetPeriphCLKConfig()
2117 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
