Searched refs:RCC_D1CFGR_HPRE_DIV1 (Results 1 – 18 of 18) sorted by relevance
283 #if defined(RCC_D1CFGR_HPRE_DIV1)284 #define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1
378 #if defined(RCC_D1CFGR_HPRE_DIV1)379 #define RCC_HCLK_DIV1 RCC_D1CFGR_HPRE_DIV1
15164 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
15152 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
14713 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
14038 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
14701 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
14931 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
14937 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
15244 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
14668 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
15513 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
18670 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
18401 #define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ macro
