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Searched refs:RCC_D1CFGR_D1PPRE (Results 1 – 19 of 19) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c961 #if defined (RCC_D1CFGR_D1PPRE) in HAL_RCC_ClockConfig()
962 if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) in HAL_RCC_ClockConfig()
965 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); in HAL_RCC_ClockConfig()
1148 #if defined(RCC_D1CFGR_D1PPRE) in HAL_RCC_ClockConfig()
1149 if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) in HAL_RCC_ClockConfig()
1152 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); in HAL_RCC_ClockConfig()
1735 RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); in HAL_RCC_GetClockConfig()
Dstm32h7xx_hal_rcc_ex.c2906 #if defined(RCC_D1CFGR_D1PPRE) in HAL_RCCEx_GetD1PCLK1Freq()
2908 …return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR… in HAL_RCCEx_GetD1PCLK1Freq()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h1556 #if defined(RCC_D1CFGR_D1PPRE)
1557 …ER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1C…
2575 #if defined(RCC_D1CFGR_D1PPRE) in LL_RCC_SetAPB3Prescaler()
2576 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler); in LL_RCC_SetAPB3Prescaler()
2698 #if defined(RCC_D1CFGR_D1PPRE) in LL_RCC_GetAPB3Prescaler()
2699 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE)); in LL_RCC_GetAPB3Prescaler()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h730xxq.h15193 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h733xx.h15181 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h725xx.h14742 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h730xx.h15181 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h735xx.h15193 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h742xx.h14067 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h723xx.h14730 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h750xx.h14960 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h753xx.h14966 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h745xx.h15273 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h745xg.h15273 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h743xx.h14697 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h755xx.h15542 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h757xx.h18699 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h747xg.h18430 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro
Dstm32h747xx.h18430 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits… macro