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Searched refs:RCC_CFGR_SWS_PLL1 (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c427 …if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllck… in HAL_RCC_OscConfig()
480 …if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllck… in HAL_RCC_OscConfig()
561 …if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllck… in HAL_RCC_OscConfig()
760 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) in HAL_RCC_OscConfig()
1419 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in HAL_RCC_GetSysClockFreq()
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dsystem_stm32h7xx.c363 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dsystem_stm32h7xx_dualcore_bootcm4_cm7gated.c342 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in SystemCoreClockUpdate()
Dsystem_stm32h7xx_dualcore_bootcm7_cm4gated.c348 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in SystemCoreClockUpdate()
Dsystem_stm32h7xx_dualcore_boot_cm4_cm7.c350 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in SystemCoreClockUpdate()
Dsystem_stm32h7xx_singlecore.c343 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in SystemCoreClockUpdate()
Dsystem_stm32h7xx.c368 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ in SystemCoreClockUpdate()
Dstm32h7a3xx.h12784 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h7b0xx.h13228 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h7b0xxq.h13240 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h7a3xxq.h12796 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h7b3xx.h13235 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h7b3xxq.h13247 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h730xxq.h15095 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h733xx.h15083 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h725xx.h14644 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h730xx.h15083 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h735xx.h15095 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h742xx.h13965 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h723xx.h14632 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h750xx.h14858 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h753xx.h14864 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
Dstm32h745xx.h15171 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used … macro
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h229 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */
Dstm32h7xx_hal_rcc.h341 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */

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