Searched refs:RCC_CFGR_MCO_PLL3CLK_DIV2 (Results 1 – 4 of 4) sorted by relevance
261 #if defined(RCC_CFGR_MCO_PLL3CLK_DIV2)262 #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2…
574 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
1453 #define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divi… macro1469 #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2
1533 #define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divi… macro1549 #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2