Searched refs:RCC_CFGR4_HDIV5 (Results 1 – 8 of 8) sorted by relevance
1009 MODIFY_REG(RCC->CFGR4, (RCC_CFGR4_HDIV5 | RCC_CFGR4_HPRE5), in HAL_RCC_ClockConfig()1371 tmp = (RCC->CFGR4 & RCC_CFGR4_HDIV5) >> RCC_CFGR4_HDIV5_Pos; in HAL_RCC_GetHCLK5Freq()1550 RCC_ClkInitStruct->AHB5_HSEHSI_CLKDivider = (tmpreg1 & RCC_CFGR4_HDIV5); in HAL_RCC_GetClockConfig()
335 #define LL_RCC_AHB5_DIVIDER_2 RCC_CFGR4_HDIV5 …1565 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HDIV5, Divider); in LL_RCC_SetAHB5Divider()1665 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HDIV5)); in LL_RCC_GetAHB5Divider()
352 #define RCC_SYSCLK_HSEHSI_DIV2 RCC_CFGR4_HDIV5 /*!< SYSCLK when HSE or HSI is source d…
6576 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
10478 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
10872 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
10890 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
