Searched refs:RCC_CFGR2_PREDIV1 (Results 1 – 11 of 11) sorted by relevance
407 #if defined(RCC_CFGR2_PREDIV1)453 #if defined(RCC_CFGR2_PREDIV1)1479 #if defined(RCC_CFGR2_PREDIV1) in LL_RCC_PLL_ConfigDomain_SYS()1481 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), in LL_RCC_PLL_ConfigDomain_SYS()1482 (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); in LL_RCC_PLL_ConfigDomain_SYS()1484 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_ConfigDomain_SYS()1584 #if defined(RCC_CFGR2_PREDIV1) in LL_RCC_PLL_GetPrediv()1585 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); in LL_RCC_PLL_GetPrediv()
1589 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1,…1609 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
316 #if defined(RCC_CFGR2_PREDIV1) in HAL_RCC_DeInit()1087 #if defined(RCC_CFGR2_PREDIV1) in HAL_RCC_GetSysClockFreq()1115 #if defined(RCC_CFGR2_PREDIV1) in HAL_RCC_GetSysClockFreq()1116 … prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; in HAL_RCC_GetSysClockFreq()
114 #if defined(RCC_CFGR2_PREDIV1)546 #if defined (RCC_CFGR2_PREDIV1) in UTILS_GetPLLOutputFrequency()
143 #if defined(RCC_CFGR2_PREDIV1) in LL_RCC_DeInit()
424 … prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; in HAL_RCCEx_GetPeriphCLKFreq()
264 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; in SystemCoreClockUpdate()301 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; in SystemCoreClockUpdate()
1399 #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bi… macro
1728 #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bi… macro
1862 #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bi… macro
1954 #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bi… macro
