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Searched refs:RCC_CFGR2_HPRE_0 (Results 1 – 25 of 34) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h250 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) …
252 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_…
254 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_…
256 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE…
Dstm32h5xx_hal_rcc.h341 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) …
343 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) …
345 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) …
347 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | R…
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h317 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) …
319 …YSCLK_DIV_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) …
321 …YSCLK_DIV_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) …
324 RCC_CFGR2_HPRE_0)/*!< SYSCLK divided by 512 */
Dstm32u5xx_hal_rcc.h463 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) …
465 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) …
467 #define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) …
469 #define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | R…
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h264 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) …
266 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)…
Dstm32wbaxx_hal_rcc.h317 #define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) …
319 #define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) …
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h296 #define LL_RCC_AHB_DIV_2 RCC_CFGR2_HPRE_0
298 #define LL_RCC_AHB_DIV_8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)
300 #define LL_RCC_AHB_DIV_32 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0)
302 #define LL_RCC_AHB_DIV_128 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0)
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h5965 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32wba52xx.h9739 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32wba54xx.h10011 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32wba5mxx.h10029 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32wba55xx.h10029 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h8439 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32h523xx.h12576 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32h562xx.h13256 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32h533xx.h13095 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32h573xx.h15859 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32h563xx.h15340 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h14421 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32u535xx.h13908 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32u575xx.h15316 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32u585xx.h15878 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32u595xx.h16344 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32u5a5xx.h16906 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro
Dstm32u5f7xx.h17870 #define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001… macro

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