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Searched refs:RCC_CDCFGR2_CDPPRE1_Pos (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc.c1524 …() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU… in HAL_RCC_GetPCLK1Freq()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_rcc.h1525 …L_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU…
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h12936 #define RCC_CDCFGR2_CDPPRE1_Pos (4U) macro
12937 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 …
12939 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 …
12940 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 …
12941 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 …
Dstm32h7b0xx.h13380 #define RCC_CDCFGR2_CDPPRE1_Pos (4U) macro
13381 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 …
13383 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 …
13384 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 …
13385 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 …
Dstm32h7b0xxq.h13392 #define RCC_CDCFGR2_CDPPRE1_Pos (4U) macro
13393 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 …
13395 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 …
13396 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 …
13397 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 …
Dstm32h7a3xxq.h12948 #define RCC_CDCFGR2_CDPPRE1_Pos (4U) macro
12949 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 …
12951 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 …
12952 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 …
12953 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 …
Dstm32h7b3xx.h13387 #define RCC_CDCFGR2_CDPPRE1_Pos (4U) macro
13388 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 …
13390 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 …
13391 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 …
13392 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 …
Dstm32h7b3xxq.h13399 #define RCC_CDCFGR2_CDPPRE1_Pos (4U) macro
13400 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 …
13402 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 …
13403 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 …
13404 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 …