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Searched refs:RCC_CCIPR4_I3C1SEL_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h718 …CE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x0000000…
720 …CE_PLL3R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR…
722 …CE_PLL2R LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR…
724 …CE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR…
725 …CE_NONE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, RCC_CCIPR…
1070 …URCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0x0000000…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h751 …_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U)
752 …3C1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
754 …3C1_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
756 …3C1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
758 …3C1_CLKSOURCE_MSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
760 …3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\
1305 …_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U)
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h9289 #define RCC_CCIPR4_I3C1SEL_Pos (24U) macro
9290 #define RCC_CCIPR4_I3C1SEL_Msk (0x3UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x03000000 */
9292 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x01000000 */
9293 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x02000000 */
Dstm32h523xx.h13760 #define RCC_CCIPR4_I3C1SEL_Pos (24U) macro
13761 #define RCC_CCIPR4_I3C1SEL_Msk (0x3UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x03000000 */
13763 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x01000000 */
13764 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x02000000 */
Dstm32h562xx.h14740 #define RCC_CCIPR4_I3C1SEL_Pos (24U) macro
14741 #define RCC_CCIPR4_I3C1SEL_Msk (0x3UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x03000000 */
14743 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x01000000 */
14744 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x02000000 */
Dstm32h533xx.h14309 #define RCC_CCIPR4_I3C1SEL_Pos (24U) macro
14310 #define RCC_CCIPR4_I3C1SEL_Msk (0x3UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x03000000 */
14312 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x01000000 */
14313 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x02000000 */
Dstm32h573xx.h17385 #define RCC_CCIPR4_I3C1SEL_Pos (24U) macro
17386 #define RCC_CCIPR4_I3C1SEL_Msk (0x3UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x03000000 */
17388 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x01000000 */
17389 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x02000000 */
Dstm32h563xx.h16836 #define RCC_CCIPR4_I3C1SEL_Pos (24U) macro
16837 #define RCC_CCIPR4_I3C1SEL_Msk (0x3UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x03000000 */
16839 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x01000000 */
16840 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x02000000 */
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h25982 #define RCC_CCIPR4_I3C1SEL_Pos (16U) macro
25983 #define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) …
25985 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
25986 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
25987 #define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
Dstm32n657xx.h27131 #define RCC_CCIPR4_I3C1SEL_Pos (16U) macro
27132 #define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) …
27134 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
27135 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
27136 #define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
Dstm32n655xx.h26889 #define RCC_CCIPR4_I3C1SEL_Pos (16U) macro
26890 #define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) …
26892 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
26893 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
26894 #define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
Dstm32n647xx.h26224 #define RCC_CCIPR4_I3C1SEL_Pos (16U) macro
26225 #define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) …
26227 #define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
26228 #define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…
26229 #define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!<…