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Searched refs:RCC_CCIPR3_SPI1SEL_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h744 …CE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x0000000…
745 …CE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
747 …CE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
749 …CE_PIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
750 …CE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
1028 …SOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0x0000000…
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_rcc.h767 …CLKSOURCE_PLL1Q LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0U)
768 …CE_PLL2P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
769 …CE_PLL3P LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
770 …CE_I2S_CKIN LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
772 …CE_CLKP LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, RCC_CCIPR…
1023 …CLKSOURCE LL_CLKSOURCE(CCIPR3_OFFSET, RCC_CCIPR3_SPI1SEL, RCC_CCIPR3_SPI1SEL_Pos, 0U)
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h9235 #define RCC_CCIPR3_SPI1SEL_Pos (0U) macro
9236 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000007…
9238 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000001…
9239 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000002…
9240 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000004…
Dstm32h523xx.h13682 #define RCC_CCIPR3_SPI1SEL_Pos (0U) macro
13683 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000007…
13685 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000001…
13686 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000002…
13687 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000004…
Dstm32h562xx.h14642 #define RCC_CCIPR3_SPI1SEL_Pos (0U) macro
14643 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000007…
14645 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000001…
14646 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000002…
14647 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000004…
Dstm32h533xx.h14231 #define RCC_CCIPR3_SPI1SEL_Pos (0U) macro
14232 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000007…
14234 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000001…
14235 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000002…
14236 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000004…
Dstm32h573xx.h17284 #define RCC_CCIPR3_SPI1SEL_Pos (0U) macro
17285 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000007…
17287 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000001…
17288 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000002…
17289 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000004…
Dstm32h563xx.h16735 #define RCC_CCIPR3_SPI1SEL_Pos (0U) macro
16736 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000007…
16738 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000001…
16739 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000002…
16740 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000004…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h15152 #define RCC_CCIPR3_SPI1SEL_Pos (8U) macro
15153 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */
15155 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */
15156 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */
15157 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */
Dstm32h7s7xx.h16186 #define RCC_CCIPR3_SPI1SEL_Pos (8U) macro
16187 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */
16189 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */
16190 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */
16191 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */
Dstm32h7s3xx.h15784 #define RCC_CCIPR3_SPI1SEL_Pos (8U) macro
15785 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */
15787 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */
15788 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */
15789 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */
Dstm32h7r7xx.h15552 #define RCC_CCIPR3_SPI1SEL_Pos (8U) macro
15553 #define RCC_CCIPR3_SPI1SEL_Msk (0x7UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000700 */
15555 #define RCC_CCIPR3_SPI1SEL_0 (0x1UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000100 */
15556 #define RCC_CCIPR3_SPI1SEL_1 (0x2UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000200 */
15557 #define RCC_CCIPR3_SPI1SEL_2 (0x4UL << RCC_CCIPR3_SPI1SEL_Pos) /*!< 0x00000400 */