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Searched refs:RCC_CCIPR2_LPTIM1SEL_Pos (Results 1 – 12 of 12) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h801 …E_PCLK3 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x000000…
802 …E_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP…
804 …E_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP…
806 …E_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP…
807 …E_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP…
808 …E_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCIP…
1081 …RCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0x000000…
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_rcc.h662 …OURCE_PCLK1 LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0U)
663 …_PLL2P LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCI…
664 …_PLL3R LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCI…
665 …_LSE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCI…
667 …_LSI LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCI…
668 …_CLKP LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, RCC_CCI…
964 …KSOURCE LL_CLKSOURCE(CCIPR2_OFFSET, RCC_CCIPR2_LPTIM1SEL, RCC_CCIPR2_LPTIM1SEL_Pos, 0U)
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h9220 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro
9221 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000700…
9223 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000100…
9224 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000200…
9225 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000400…
Dstm32h523xx.h13667 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro
13668 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000700…
13670 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000100…
13671 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000200…
13672 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000400…
Dstm32h562xx.h14599 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro
14600 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000700…
14602 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000100…
14603 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000200…
14604 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000400…
Dstm32h533xx.h14216 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro
14217 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000700…
14219 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000100…
14220 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000200…
14221 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000400…
Dstm32h573xx.h17241 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro
17242 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000700…
17244 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000100…
17245 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000200…
17246 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000400…
Dstm32h563xx.h16692 #define RCC_CCIPR2_LPTIM1SEL_Pos (8U) macro
16693 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000700…
16695 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000100…
16696 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000200…
16697 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00000400…
/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7r3xx.h15112 #define RCC_CCIPR2_LPTIM1SEL_Pos (16U) macro
15113 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */
15115 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */
15116 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */
15117 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */
Dstm32h7s7xx.h16146 #define RCC_CCIPR2_LPTIM1SEL_Pos (16U) macro
16147 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */
16149 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */
16150 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */
16151 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */
Dstm32h7s3xx.h15744 #define RCC_CCIPR2_LPTIM1SEL_Pos (16U) macro
15745 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */
15747 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */
15748 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */
15749 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */
Dstm32h7r7xx.h15512 #define RCC_CCIPR2_LPTIM1SEL_Pos (16U) macro
15513 #define RCC_CCIPR2_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00070000 */
15515 #define RCC_CCIPR2_LPTIM1SEL_0 (0x1UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00010000 */
15516 #define RCC_CCIPR2_LPTIM1SEL_1 (0x2UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00020000 */
15517 #define RCC_CCIPR2_LPTIM1SEL_2 (0x4UL << RCC_CCIPR2_LPTIM1SEL_Pos) /*!< 0x00040000 */