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Searched refs:RCC_BASE (Results 1 – 25 of 292) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h1862 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); in LL_RCC_SetI2CClockSource()
1881 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); in LL_RCC_SetSPIClockSource()
1902 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); in LL_RCC_SetLPTIMClockSource()
2011 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U)); in LL_RCC_GetI2CClockSource()
2032 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U)); in LL_RCC_GetSPIClockSource()
2055 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U)); in LL_RCC_GetLPTIMClockSource()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc.h1216 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1282 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
1285 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
1288 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h2886 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTxSource >> 24U)); in LL_RCC_SetUSARTClockSource()
2954 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); in LL_RCC_SetI2CClockSource()
2983 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); in LL_RCC_SetSPIClockSource()
3011 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); in LL_RCC_SetLPTIMClockSource()
3301 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTx >> 24U)); in LL_RCC_GetUSARTClockSource()
3371 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U)); in LL_RCC_GetI2CClockSource()
3401 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U)); in LL_RCC_GetSPIClockSource()
3431 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U)); in LL_RCC_GetLPTIMClockSource()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_hal_rcc.h65 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
78 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
81 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
84 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_hal_rcc.h61 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
127 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
130 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
133 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_hal_rcc.h62 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
127 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
130 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
133 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc.h1290 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1322 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1325 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc.h1188 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
1191 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h67 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
81 #define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10U + 0x00U))
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h1904 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1945 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
1948 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_rcc.h1592 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); in LL_RCC_SetI2CClockSource()
1820 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); in LL_RCC_GetI2CClockSource()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_rcc.h1916 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); in LL_RCC_SetI2CClockSource()
2079 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); in LL_RCC_GetI2CClockSource()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_rcc.h2423 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); in LL_RCC_SetI2CClockSource()
2692 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); in LL_RCC_GetI2CClockSource()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_rcc.h3013 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U)); in LL_RCC_SetI2CClockSource()
3358 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U)); in LL_RCC_GetI2CClockSource()
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f101x6.h504 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
553 #define RCC ((RCC_TypeDef *)RCC_BASE)
Dstm32f101xb.h514 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
568 #define RCC ((RCC_TypeDef *)RCC_BASE)
Dstm32f100xb.h565 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
628 #define RCC ((RCC_TypeDef *)RCC_BASE)
/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h463 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
511 #define RCC ((RCC_TypeDef *) RCC_BASE)
Dstm32f030x8.h474 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
527 #define RCC ((RCC_TypeDef *) RCC_BASE)
Dstm32f070x6.h506 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
555 #define RCC ((RCC_TypeDef *) RCC_BASE)
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h544 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
601 #define RCC ((RCC_TypeDef *) RCC_BASE)
Dstm32l010x8.h505 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
559 #define RCC ((RCC_TypeDef *) RCC_BASE)
Dstm32l010xb.h507 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
563 #define RCC ((RCC_TypeDef *) RCC_BASE)
Dstm32l011xx.h521 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
573 #define RCC ((RCC_TypeDef *) RCC_BASE)
Dstm32l021xx.h540 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) macro
593 #define RCC ((RCC_TypeDef *) RCC_BASE)

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