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Searched refs:RCC_APB2ENR_SPI5EN (Results 1 – 25 of 68) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1547 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1549 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1593 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1634 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1647 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
3412 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3414 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
3424 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
3437 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
3440 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
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Dstm32f4xx_ll_bus.h312 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h2268 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2270 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
2335 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
2369 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)
2397 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)
3448 SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3450 tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\
3503 #define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)
4478 SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
4480 tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\
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Dstm32h7xx_ll_bus.h334 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1323 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1325 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1421 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
1676 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
1717 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Dstm32f7xx_ll_bus.h216 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_bus.h213 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
Dstm32h7rsxx_hal_rcc.h1707 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
1745 #define __HAL_RCC_SPI5_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN)
2163 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN) != 0U)
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_bus.h307 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f410cx.h4677 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f410rx.h4681 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f411xe.h4388 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f412cx.h8864 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f423xx.h10178 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f412zx.h9842 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f412rx.h9818 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f412vx.h9826 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f413xx.h10136 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f427xx.h10860 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9775 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f722xx.h9756 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f730xx.h9995 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f733xx.h9995 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f732xx.h9976 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro
Dstm32f750xx.h11239 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk macro

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