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Searched refs:RCC_APB1ENR_CAN2EN (Results 1 – 25 of 40) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1386 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1388 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1461 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1490 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1509 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
2415 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2417 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
2476 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
2503 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
2520 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
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Dstm32f4xx_ll_bus.h248 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/include/
Dstm32f1xx_hal_rcc_ex.h1020 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1022 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1026 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1136 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1137 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Dstm32f1xx_ll_bus.h110 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h796 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
798 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
837 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
871 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET)
895 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET)
Dstm32f2xx_ll_bus.h150 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h1145 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1147 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1197 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1640 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1645 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Dstm32f7xx_ll_bus.h176 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h9559 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f205xx.h9310 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f207xx.h9630 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f217xx.h9879 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h9716 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f412cx.h8817 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f415xx.h9995 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f423xx.h10113 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f407xx.h10037 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f412zx.h9795 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f412rx.h9771 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f412vx.h9779 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f413xx.h10071 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f427xx.h10801 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
Dstm32f446xx.h10659 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk macro
/hal_stm32-latest/stm32cube/stm32f1xx/soc/
Dstm32f105xc.h1788 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enab… macro
Dstm32f107xc.h1877 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enab… macro

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