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Searched refs:RCC_AHB3ENR_FMCEN (Results 1 – 25 of 77) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c368 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
571 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
707 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
715 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); in SystemInit_ExtMemCtl()
Dstm32f427xx.h10736 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f446xx.h10585 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h780 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
782 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
798 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
1373 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1381 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
Dstm32g4xx_ll_bus.h123 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h907 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
909 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
921 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
1479 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1481 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
Dstm32l5xx_ll_bus.h116 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h1269 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1271 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
1274 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
1297 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1298 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
4128 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4130 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
4141 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
4154 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
4157 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Dstm32f4xx_ll_bus.h171 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h1000 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
1002 … tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
1038 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
1845 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1861 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
Dstm32l4xx_ll_bus.h151 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc.h793 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
795 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
876 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
912 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)
941 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)
2675 SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
2677 tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\
2703 #define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))
3702 SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
3704 tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\
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Dstm32h7xx_ll_bus.h79 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h895 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
897 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
909 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
1572 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
1575 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Dstm32f7xx_ll_bus.h138 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g473xx.h8809 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32g483xx.h9036 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9642 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f722xx.h9623 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f730xx.h9862 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f733xx.h9862 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f732xx.h9843 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f750xx.h11100 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
Dstm32f745xx.h10471 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l471xx.h11003 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk macro

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