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Searched refs:RCC_AHB2ENR_AESEN (Results 1 – 25 of 42) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_rcc.h687 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
689 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
751 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN)
1099 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
Dstm32wbaxx_ll_bus.h94 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_hal_rcc.h711 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
713 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
760 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
1316 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
1355 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
Dstm32g4xx_ll_bus.h111 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_hal_rcc.h809 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
811 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
878 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
1426 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
1456 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
Dstm32l5xx_ll_bus.h98 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_hal_rcc.h865 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
867 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
964 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
1746 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
1811 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
Dstm32l4xx_ll_bus.h123 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h879 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
881 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
885 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
1551 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
1552 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
Dstm32f7xx_ll_bus.h123 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_rcc.h1011 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
1013 … tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
1109 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
2194 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
2251 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
Dstm32h5xx_ll_bus.h163 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_bus.h146 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
Dstm32f4xx_hal_rcc_ex.h4868 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
4870 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
4874 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
4903 #define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
4904 #define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h6252 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
Dstm32wba52xx.h10052 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h6121 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
Dstm32l442xx.h9642 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g441xx.h7965 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
Dstm32g4a1xx.h8341 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
Dstm32g483xx.h9028 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f423xx.h10020 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f730xx.h9851 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
Dstm32f733xx.h9851 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro
Dstm32f732xx.h9832 #define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk macro

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