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Searched refs:RCC_AHB1ENR_GPIOFEN_Pos (Results 1 – 25 of 32) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dstm32f215xx.h9444 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9445 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f205xx.h9201 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9202 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f207xx.h9506 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9507 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f217xx.h9749 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9750 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f405xx.h9597 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9598 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f415xx.h9870 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9871 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f423xx.h9994 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9995 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f407xx.h9903 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9904 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f412zx.h9688 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9689 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f413xx.h9955 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9956 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f427xx.h10658 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
10659 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f446xx.h10537 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
10538 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f417xx.h10173 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
10174 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f429xx.h11005 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
11006 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f439xx.h11287 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
11288 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f437xx.h10945 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
10946 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9597 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9598 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f722xx.h9578 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9579 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f730xx.h9814 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9815 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f733xx.h9814 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9815 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f732xx.h9795 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
9796 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f750xx.h11025 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
11026 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f745xx.h10402 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
10403 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f756xx.h11025 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
11026 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
Dstm32f746xx.h10744 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) macro
10745 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */

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