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Searched refs:RCC_AHB1ENR_GPIODEN (Results 1 – 25 of 45) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_hal_rcc_ex.h993 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
995 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
1089 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
1134 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
1155 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESE…
2060 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2062 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
2107 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
2182 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESE…
2190 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESE…
[all …]
Dstm32f4xx_ll_bus.h74 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
/hal_stm32-latest/stm32cube/stm32f2xx/drivers/include/
Dstm32f2xx_hal_rcc.h433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
518 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
543 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != R…
559 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == …
Dstm32f2xx_ll_bus.h73 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
/hal_stm32-latest/stm32cube/stm32f2xx/soc/
Dsystem_stm32f2xx.c269 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); in SystemInit_ExtMemCtl()
Dstm32f215xx.h9440 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f205xx.h9197 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f207xx.h9502 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f217xx.h9745 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_hal_rcc_ex.h653 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
655 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
735 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
1470 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESE…
1492 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESE…
Dstm32f7xx_ll_bus.h73 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dsystem_stm32f4xx.c651 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); in SystemInit_ExtMemCtl()
Dstm32f401xc.h4276 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f401xe.h4276 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f411xe.h4288 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f405xx.h9593 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f415xx.h9866 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f423xx.h9990 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f407xx.h9899 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f412zx.h9684 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f412rx.h9669 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f412vx.h9674 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f413xx.h9951 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h9593 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro
Dstm32f722xx.h9574 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk macro

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