Searched refs:PWR_CR5_SMPSEN_Pos (Results 1 – 14 of 14) sorted by relevance
1351 …MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_… in LL_PWR_SMPS_SetMode()1372 …uint32_t OperatingMode = (READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) >> (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPS… in LL_PWR_SMPS_GetMode()
843 …return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos… in HAL_PWREx_SMPS_GetEffectiveMode()
923 …MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, (OperatingMode & PWR_SR2_SMPSF) << (PWR_CR5_SMPSEN_Pos - PWR_… in HAL_PWREx_SMPS_SetMode()
1217 …return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos… in LL_PWR_SMPS_GetEffectiveMode()
5513 #define PWR_CR5_SMPSEN_Pos (15U) macro5514 #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
6301 #define PWR_CR5_SMPSEN_Pos (15U) macro6302 #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
5706 #define PWR_CR5_SMPSEN_Pos (15U) macro5707 #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
6463 #define PWR_CR5_SMPSEN_Pos (15U) macro6464 #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
6551 #define PWR_CR5_SMPSEN_Pos (15U) macro6552 #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
