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Searched refs:PWR_CR2_PVDRT_Pos (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h3736 #define PWR_CR2_PVDRT_Pos (4U) macro
3737 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
3739 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
3740 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
3741 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g041xx.h3972 #define PWR_CR2_PVDRT_Pos (4U) macro
3973 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
3975 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
3976 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
3977 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g051xx.h4072 #define PWR_CR2_PVDRT_Pos (4U) macro
4073 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
4075 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
4076 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
4077 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g061xx.h4308 #define PWR_CR2_PVDRT_Pos (4U) macro
4309 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
4311 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
4312 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
4313 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g071xx.h4287 #define PWR_CR2_PVDRT_Pos (4U) macro
4288 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
4290 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
4291 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
4292 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g081xx.h4523 #define PWR_CR2_PVDRT_Pos (4U) macro
4524 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
4526 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
4527 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
4528 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g0c1xx.h5552 #define PWR_CR2_PVDRT_Pos (4U) macro
5553 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
5555 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
5556 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
5557 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
Dstm32g0b1xx.h5316 #define PWR_CR2_PVDRT_Pos (4U) macro
5317 #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
5319 #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
5320 #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
5321 #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */