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Searched refs:PWR_CR2_PVDE (Results 1 – 25 of 85) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_pwr.h117 #if defined(PWR_CR2_PVDE)
592 #if defined (PWR_CR2_PVDE)
671 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
681 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
691 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_pwr.h499 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
509 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
519 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_pwr.h685 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
695 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
705 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_pwr.h659 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
669 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
679 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_pwr.h697 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
707 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
718 temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_IsEnabledPVD()
720 return ((temp == (PWR_CR2_PVDE))?1U:0U); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/include/
Dstm32wlxx_ll_pwr.h591 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
601 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
611 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_pwr.c359 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
368 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_pwr.c356 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
365 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_pwr.c364 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
373 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
Dstm32u0xx_hal_pwr_ex.c797 if (READ_BIT(PWR->CR2, PWR_CR2_PVDE) != 0U) in HAL_PWREx_PVD_PVM_IRQHandler()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/src/
Dstm32wb0x_hal_pwr.c170 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
180 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_pwr.h737 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
747 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
757 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_hal_pwr.c413 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
423 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_pwr.c358 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
367 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
/hal_stm32-latest/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_pwr.c392 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
402 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_DisablePVD()
/hal_stm32-latest/stm32cube/stm32wb0x/drivers/include/
Dstm32wb0x_ll_pwr.h702 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
712 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
722 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_pwr_ex.c235 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWREx_EnablePVD()
245 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWREx_DisablePVD()
/hal_stm32-latest/stm32cube/stm32g0xx/soc/
Dstm32g031xx.h3729 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Vo… macro
Dstm32g041xx.h3965 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Vo… macro
Dstm32g051xx.h4065 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Vo… macro
Dstm32g061xx.h4301 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Vo… macro
Dstm32g071xx.h4280 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Vo… macro
/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h5338 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage d… macro
Dstm32wle5xx.h5338 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power voltage d… macro
/hal_stm32-latest/stm32cube/stm32wb0x/soc/
Dstm32wb05.h3163 #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk macro

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