Home
last modified time | relevance | path

Searched refs:PWR_CR1_UDEN_Pos (Results 1 – 14 of 14) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h8759 #define PWR_CR1_UDEN_Pos (18U) macro
8760 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
8762 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
8763 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f722xx.h8743 #define PWR_CR1_UDEN_Pos (18U) macro
8744 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
8746 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
8747 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f730xx.h8973 #define PWR_CR1_UDEN_Pos (18U) macro
8974 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
8976 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
8977 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f733xx.h8973 #define PWR_CR1_UDEN_Pos (18U) macro
8974 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
8976 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
8977 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f732xx.h8957 #define PWR_CR1_UDEN_Pos (18U) macro
8958 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
8960 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
8961 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f750xx.h10150 #define PWR_CR1_UDEN_Pos (18U) macro
10151 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10153 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10154 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f745xx.h9536 #define PWR_CR1_UDEN_Pos (18U) macro
9537 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
9539 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
9540 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f756xx.h10150 #define PWR_CR1_UDEN_Pos (18U) macro
10151 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10153 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10154 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f746xx.h9875 #define PWR_CR1_UDEN_Pos (18U) macro
9876 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
9878 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
9879 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f765xx.h10047 #define PWR_CR1_UDEN_Pos (18U) macro
10048 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10050 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10051 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f777xx.h10698 #define PWR_CR1_UDEN_Pos (18U) macro
10699 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10701 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10702 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f767xx.h10423 #define PWR_CR1_UDEN_Pos (18U) macro
10424 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10426 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10427 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f779xx.h10781 #define PWR_CR1_UDEN_Pos (18U) macro
10782 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10784 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10785 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */
Dstm32f769xx.h10506 #define PWR_CR1_UDEN_Pos (18U) macro
10507 #define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */
10509 #define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */
10510 #define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */