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Searched refs:PWR_CR1_RESERVED0_Pos (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h22448 #define PWR_CR1_RESERVED0_Pos (3U) macro
22449 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151fxx_cm4.h22611 #define PWR_CR1_RESERVED0_Pos (3U) macro
22612 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151axx_ca7.h22448 #define PWR_CR1_RESERVED0_Pos (3U) macro
22449 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151axx_cm4.h22414 #define PWR_CR1_RESERVED0_Pos (3U) macro
22415 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151dxx_cm4.h22414 #define PWR_CR1_RESERVED0_Pos (3U) macro
22415 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151cxx_ca7.h22645 #define PWR_CR1_RESERVED0_Pos (3U) macro
22646 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151cxx_cm4.h22611 #define PWR_CR1_RESERVED0_Pos (3U) macro
22612 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp151fxx_ca7.h22645 #define PWR_CR1_RESERVED0_Pos (3U) macro
22646 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153axx_ca7.h23999 #define PWR_CR1_RESERVED0_Pos (3U) macro
24000 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153axx_cm4.h23965 #define PWR_CR1_RESERVED0_Pos (3U) macro
23966 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153cxx_ca7.h24196 #define PWR_CR1_RESERVED0_Pos (3U) macro
24197 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153cxx_cm4.h24162 #define PWR_CR1_RESERVED0_Pos (3U) macro
24163 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153dxx_ca7.h23999 #define PWR_CR1_RESERVED0_Pos (3U) macro
24000 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153dxx_cm4.h23965 #define PWR_CR1_RESERVED0_Pos (3U) macro
23966 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153fxx_ca7.h24196 #define PWR_CR1_RESERVED0_Pos (3U) macro
24197 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp153fxx_cm4.h24162 #define PWR_CR1_RESERVED0_Pos (3U) macro
24163 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157axx_ca7.h25222 #define PWR_CR1_RESERVED0_Pos (3U) macro
25223 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157axx_cm4.h25188 #define PWR_CR1_RESERVED0_Pos (3U) macro
25189 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157cxx_ca7.h25419 #define PWR_CR1_RESERVED0_Pos (3U) macro
25420 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157cxx_cm4.h25385 #define PWR_CR1_RESERVED0_Pos (3U) macro
25386 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157dxx_ca7.h25222 #define PWR_CR1_RESERVED0_Pos (3U) macro
25223 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157dxx_cm4.h25188 #define PWR_CR1_RESERVED0_Pos (3U) macro
25189 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157fxx_ca7.h25419 #define PWR_CR1_RESERVED0_Pos (3U) macro
25420 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */
Dstm32mp157fxx_cm4.h25385 #define PWR_CR1_RESERVED0_Pos (3U) macro
25386 #define PWR_CR1_RESERVED0_Msk (0x1UL << PWR_CR1_RESERVED0_Pos) /*!< 0x00000008 */