Searched refs:PWR_CR1_POPL_Pos (Results 1 – 6 of 6) sorted by relevance
579 MODIFY_REG(PWR->CR1, PWR_CR1_POPL_Msk, (Pulselowtime << PWR_CR1_POPL_Pos)); in HAL_PWREx_SetPulseLow()590 return ((PWR->CR1 & PWR_CR1_POPL_Msk) >> PWR_CR1_POPL_Pos); in HAL_PWREx_GetPulseLow()
319 MODIFY_REG(PWR->CR1, PWR_CR1_POPL, (PulseTime << PWR_CR1_POPL_Pos)); in LL_PWR_SetPwrONPulseLowTime()329 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_POPL) >> PWR_CR1_POPL_Pos); in LL_PWR_GetPwrONPulseLowTime()
24644 #define PWR_CR1_POPL_Pos (16U) macro24645 #define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */24647 #define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */24648 #define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */24649 #define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */24650 #define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */24651 #define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */
25793 #define PWR_CR1_POPL_Pos (16U) macro25794 #define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */25796 #define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */25797 #define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */25798 #define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */25799 #define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */25800 #define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */
25551 #define PWR_CR1_POPL_Pos (16U) macro25552 #define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */25554 #define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */25555 #define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */25556 #define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */25557 #define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */25558 #define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */
24886 #define PWR_CR1_POPL_Pos (16U) macro24887 #define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */24889 #define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */24890 #define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */24891 #define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */24892 #define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */24893 #define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */
