Searched refs:PLLP2 (Results 1 – 5 of 5) sorted by relevance
259 assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP2)); in LL_PLL_ConfigSystemClock_HSI()276 pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2); in LL_PLL_ConfigSystemClock_HSI()278 …am(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruct->PLLP2)); in LL_PLL_ConfigSystemClock_HSI()345 assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP2)); in LL_PLL_ConfigSystemClock_MSI()360 pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2); in LL_PLL_ConfigSystemClock_MSI()363 …am(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruct->PLLP2)); in LL_PLL_ConfigSystemClock_MSI()438 assert_param(IS_LL_UTILS_PLLP_VALUE(pUTILS_PLLInitStruct->PLLP2)); in LL_PLL_ConfigSystemClock_HSE()453 pUTILS_PLLInitStruct->PLLP1, pUTILS_PLLInitStruct->PLLP2); in LL_PLL_ConfigSystemClock_HSE()456 …am(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq * pUTILS_PLLInitStruct->PLLP1 * pUTILS_PLLInitStruct->PLLP2)); in LL_PLL_ConfigSystemClock_HSE()531 LL_RCC_PLL1_SetP2(pUTILS_PLLInitStruct->PLLP2); in UTILS_ConfigurePLL1InIntegerMode()
1674 …pRCC_OscInitStruct->PLL1.PLLP2 = ((cfgr_value & RCC_PLL1CFGR3_PLL1PDIV2) >> RCC_PLL1CFGR3_PLL1PDIV… in HAL_RCC_GetOscConfig()1701 …pRCC_OscInitStruct->PLL2.PLLP2 = ((cfgr_value & RCC_PLL2CFGR3_PLL2PDIV2) >> RCC_PLL2CFGR3_PLL2PDIV… in HAL_RCC_GetOscConfig()1728 …pRCC_OscInitStruct->PLL3.PLLP2 = ((cfgr_value & RCC_PLL3CFGR3_PLL3PDIV2) >> RCC_PLL3CFGR3_PLL3PDIV… in HAL_RCC_GetOscConfig()1755 …pRCC_OscInitStruct->PLL4.PLLP2 = ((cfgr_value & RCC_PLL4CFGR3_PLL4PDIV2) >> RCC_PLL4CFGR3_PLL4PDIV… in HAL_RCC_GetOscConfig()2045 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2)); in RCC_PLL_Config()2073 …((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Po… in RCC_PLL_Config()2231 …((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Po… in RCC_PLL_IsNewConfig()
3162 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2)); in HAL_RCCEx_PLLSSCGConfig()3163 assert_param(IS_RCC_PLLP_VALUE(pPLLInit->PLLP2)); in HAL_RCCEx_PLLSSCGConfig()3191 …((pPLLInit->PLLP1 << RCC_PLL1CFGR3_PLL1PDIV1_Pos) | (pPLLInit->PLLP2 << RCC_PLL1CFGR3_PLL1PDIV2_Po… in HAL_RCCEx_PLLSSCGConfig()
117 uint32_t PLLP2; /*!< Division factor level 2 for PLL VCO output clock. member
72 uint32_t PLLP2; /*!< Division factor P2 for system clock. member
