Searched refs:PLLDivR (Results 1 – 2 of 2) sorted by relevance
1358 assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); in HAL_RCCEx_PeriphCLKConfig()1361 __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); in HAL_RCCEx_PeriphCLKConfig()1383 assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); in HAL_RCCEx_PeriphCLKConfig()1386 __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); in HAL_RCCEx_PeriphCLKConfig()1690 …PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Po… in HAL_RCCEx_GetPeriphCLKConfig()
234 uint32_t PLLDivR; /*!< Specifies the PLL division factor for SAI1 clock. member
