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Searched refs:PLLDiv (Results 1 – 13 of 13) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_utils.c306 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in LL_PLL_ConfigSystemClock_HSI()
326 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSI()
369 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in LL_PLL_ConfigSystemClock_HSI48()
385 …ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI48, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSI48()
435 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in LL_PLL_ConfigSystemClock_HSE()
466 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSE()
512 …RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in UTILS_GetPLLOutputFrequency()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_utils.c319 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in LL_PLL_ConfigSystemClock_HSI()
339 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSI()
392 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in LL_PLL_ConfigSystemClock_HSE()
423 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSE()
469 …RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in UTILS_GetPLLOutputFrequency()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_utils.c345 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSI()
423 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSE()
462 assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in UTILS_GetPLLOutputFrequency()
474 pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U); in UTILS_GetPLLOutputFrequency()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_ll_utils.c356 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSI()
430 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSE()
468 assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in UTILS_GetPLLOutputFrequency()
480 pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U); in UTILS_GetPLLOutputFrequency()
/hal_stm32-latest/stm32cube/stm32l1xx/drivers/include/
Dstm32l1xx_ll_rcc.h1217 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) in LL_RCC_PLL_ConfigDomain_SYS() argument
1219 …DIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()
Dstm32l1xx_ll_utils.h97 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. member
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_utils.h98 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. member
Dstm32l0xx_ll_rcc.h1832 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) in LL_RCC_PLL_ConfigDomain_SYS() argument
1834 …DIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()
/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_utils.h99 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. member
Dstm32f0xx_ll_rcc.h1578 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) in LL_RCC_PLL_ConfigDomain_SYS() argument
1581 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()
/hal_stm32-latest/stm32cube/stm32f3xx/drivers/include/
Dstm32f3xx_ll_utils.h104 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. member
Dstm32f3xx_ll_rcc.h2242 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) in LL_RCC_PLL_ConfigDomain_SYS() argument
2245 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()
/hal_stm32-latest/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_utils.c375 assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in LL_PLL_ConfigSystemClock_HSI()