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Searched refs:PLL4CFGR1 (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_rcc.c373 WRITE_REG(RCC->PLL4CFGR1, 0x00010031U); in HAL_RCC_DeInit()
1905 …RCC_OscInitStruct->PLL4.PLLM = (uint32_t)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_… in HAL_RCC_GetOscConfig()
1906 …RCC_OscInitStruct->PLL4.PLLN = (uint32_t)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) >> RCC_PLL4CFGR1_D… in HAL_RCC_GetOscConfig()
1910 RCC_OscInitStruct->PLL4.PLLRGE = (uint32_t)(RCC->PLL4CFGR1 & RCC_PLL4CFGR1_IFRGE); in HAL_RCC_GetOscConfig()
2166 pll4m = ((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1U; in HAL_RCC_GetPLL4ClockFreq()
2169 …pll4vco = (float)((float)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x2000))… in HAL_RCC_GetPLL4ClockFreq()
Dstm32mp1xx_ll_rcc.c313 WRITE_REG(RCC->PLL4CFGR1, 0x00010031U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h6017 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL, PLLSource); in LL_RCC_PLL4_SetSource()
6031 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4SEL)); in LL_RCC_PLL4_GetSource()
6073 SET_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP); in LL_RCC_PLL4_EnableBypass()
6084 CLEAR_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP); in LL_RCC_PLL4_DisableBypass()
6094 return ((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4BYP) == RCC_PLL4CFGR1_PLL4BYP) ? 1UL : 0UL); in LL_RCC_PLL4_IsEnabledBypass()
6224 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN, N << RCC_PLL4CFGR1_PLL4DIVN_Pos); in LL_RCC_PLL4_SetN()
6235 …return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVN) >> RCC_PLL4CFGR1_PLL4DIVN_Pos)… in LL_RCC_PLL4_GetN()
6246 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM, M << RCC_PLL4CFGR1_PLL4DIVM_Pos); in LL_RCC_PLL4_SetM()
6256 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_PLL4DIVM) >> RCC_PLL4CFGR1_PLL4DIVM_Pos); in LL_RCC_PLL4_GetM()
Dstm32n6xx_hal_rcc.h3946 …MODIFY_REG(RCC->PLL4CFGR1, (RCC_PLL4CFGR1_PLL4SEL | RCC_PLL4CFGR1_PLL4BYP | RCC_PLL4CFGR1_PLL4DIVM…
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_rcc.h5084 return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVN) >> RCC_PLL4CFGR1_DIVN_Pos) + 1U); in LL_RCC_PLL4_GetN()
5094 …return (uint32_t)((READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1U… in LL_RCC_PLL4_GetM()
5106 return (uint32_t)(READ_BIT(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE)); in LL_RCC_PLL4_GetIFRGE()
5157 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVN, (DIVN - 1U) << RCC_PLL4CFGR1_DIVN_Pos); in LL_RCC_PLL4_SetN()
5168 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_DIVM4, (DIVM4 - 1U) << RCC_PLL4CFGR1_DIVM4_Pos); in LL_RCC_PLL4_SetM()
5182 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, IFRange); in LL_RCC_PLL4_SetIFRGE()
Dstm32mp1xx_hal_rcc.h3693 do{ MODIFY_REG( RCC->PLL4CFGR1, (RCC_PLL4CFGR1_DIVN | RCC_PLL4CFGR1_DIVM4) , \
3724 MODIFY_REG(RCC->PLL4CFGR1, RCC_PLL4CFGR1_IFRGE, (__RCC_PLL4IFRange__))
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c291 WRITE_REG(RCC->PLL4CFGR1, 0x08000000U); in HAL_RCC_DeInit()
1746 cfgr_value = RCC->PLL4CFGR1; in HAL_RCC_GetOscConfig()
1759 cfgr_value = RCC->PLL4CFGR1; in HAL_RCC_GetOscConfig()
Dstm32n6xx_ll_rcc.c244 WRITE_REG(RCC->PLL4CFGR1, 0x08000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c350 pllcfgr = READ_REG(RCC->PLL4CFGR1); in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c407 pllcfgr = READ_REG(RCC->PLL4CFGR1); in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h1681 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151fxx_cm4.h1647 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151axx_ca7.h1681 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151axx_cm4.h1647 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151dxx_cm4.h1647 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151cxx_ca7.h1681 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151cxx_cm4.h1647 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp151fxx_ca7.h1681 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153axx_ca7.h1782 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153axx_cm4.h1748 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153cxx_ca7.h1782 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153cxx_cm4.h1748 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153dxx_ca7.h1782 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153dxx_cm4.h1748 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member
Dstm32mp153fxx_ca7.h1782 …__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 Configuration Register 1 … member

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