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Searched refs:PLL3M (Results 1 – 8 of 8) sorted by relevance

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c1345 …pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M… in HAL_RCCEx_GetPeriphCLKConfig()
3216 assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M)); in HAL_RCCEx_EnablePLL3()
3246 …__HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL… in HAL_RCCEx_EnablePLL3()
4244 assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M)); in RCCEx_PLL3_Config()
4267 pll3->PLL3M, in RCCEx_PLL3_Config()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_rcc_ex.c2558 …pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M… in HAL_RCCEx_GetPeriphCLKConfig()
5418 assert_param(IS_RCC_PLL3_DIVM_VALUE(pPLL3Init->PLL3M)); in HAL_RCCEx_EnablePLL3()
5453 …__HAL_RCC_PLL3_CONFIG(pPLL3Init->PLL3Source, pPLL3Init->PLL3M, pPLL3Init->PLL3N, pPLL3Init->PLL3P, in HAL_RCCEx_EnablePLL3()
6213 assert_param(IS_RCC_PLL3_DIVM_VALUE(pll3->PLL3M)); in RCCEx_PLL3_Config()
6240 pll3->PLL3M, in RCCEx_PLL3_Config()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c1742 …PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIV… in HAL_RCCEx_GetPeriphCLKConfig()
3802 assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); in RCCEx_PLL3_Config()
3835 __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, in RCCEx_PLL3_Config()
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_rcc.h5061 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t PLL3M) in LL_RCC_PLL3_SetM() argument
5063 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, PLL3M << RCC_PLL3CFGR_PLL3M_Pos); in LL_RCC_PLL3_SetM()
Dstm32h5xx_hal_rcc_ex.h90 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. member
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_rcc.h4984 __STATIC_INLINE void LL_RCC_PLL3_SetDivider(uint32_t PLL3M) in LL_RCC_PLL3_SetDivider() argument
4986 MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, (PLL3M - 1UL) << RCC_PLL3CFGR_PLL3M_Pos); in LL_RCC_PLL3_SetDivider()
Dstm32u5xx_hal_rcc_ex.h85 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. member
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_rcc_ex.h80 uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. member