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Searched refs:PLL2CFGR3 (Results 1 – 11 of 11) sorted by relevance

/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5405 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST); in LL_RCC_PLL2_AssertModulationSpreadSpectrumReset()
5416 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSRST); in LL_RCC_PLL2_ReleaseModulationSpreadSpectrumReset()
5427 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN); in LL_RCC_PLL2_EnableDAC()
5438 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN); in LL_RCC_PLL2_DisableDAC()
5448 …return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2DACEN) == RCC_PLL2CFGR3_PLL2DACEN) ? 1UL : 0UL… in LL_RCC_PLL2_IsEnabledDAC()
5459 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS); in LL_RCC_PLL2_EnableModulationSpreadSpectrum()
5470 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS); in LL_RCC_PLL2_DisableModulationSpreadSpectrum()
5480 return ((READ_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSSDIS) == 0UL) ? 1UL : 0UL); in LL_RCC_PLL2_IsEnabledModulationSpreadSpectrum()
5491 SET_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN); in LL_RCC_PLL2_EnableFractionalModulationSpreadSpectrum()
5502 CLEAR_BIT(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODDSEN); in LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum()
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Dstm32n6xx_hal_rcc_ex.h1132 …MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPR, (uint32_t)(__PLLMODSPR__) << RCC_PLL2CFGR3_PL…
1143 …MODIFY_REG(RCC->PLL2CFGR3, RCC_PLL2CFGR3_PLL2MODSPRDW, (uint32_t)(__PLLMODSPRDW__) << RCC_PLL2CFGR…
Dstm32n6xx_hal_rcc.h3743 MODIFY_REG(RCC->PLL2CFGR3, (RCC_PLL2CFGR3_PLL2PDIV1 | RCC_PLL2CFGR3_PLL2PDIV2), \
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c328 pllcfgr = READ_REG(RCC->PLL2CFGR3); in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c385 pllcfgr = READ_REG(RCC->PLL2CFGR3); in SystemCoreClockUpdate()
Dstm32n645xx.h1937 …__IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 … member
Dstm32n657xx.h2063 …__IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 … member
Dstm32n655xx.h2035 …__IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 … member
Dstm32n647xx.h1965 …__IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 … member
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c285 WRITE_REG(RCC->PLL2CFGR3, 0x49000005U); in HAL_RCC_DeInit()
1699 cfgr_value = RCC->PLL2CFGR3; in HAL_RCC_GetOscConfig()
Dstm32n6xx_ll_rcc.c238 WRITE_REG(RCC->PLL2CFGR3, 0x49000005U); in LL_RCC_DeInit()