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Searched refs:PLL2CFGR1 (Results 1 – 25 of 38) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_rcc.c349 WRITE_REG(RCC->PLL2CFGR1, 0x00010063U); in HAL_RCC_DeInit()
1821 …RCC_OscInitStruct->PLL2.PLLM = (uint32_t)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_… in HAL_RCC_GetOscConfig()
1822 …RCC_OscInitStruct->PLL2.PLLN = (uint32_t)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) >> RCC_PLL2CFGR1_D… in HAL_RCC_GetOscConfig()
2050 pll2m = ((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1U; in HAL_RCC_GetPLL2ClockFreq()
2053 …pll2vco = (float)((float)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) + 1U) + (fracn1 / (float)0x2000));… in HAL_RCC_GetPLL2ClockFreq()
Dstm32mp1xx_ll_rcc.c289 WRITE_REG(RCC->PLL2CFGR1, 0x00010063U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_rcc.h5317 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL, PLLSource); in LL_RCC_PLL2_SetSource()
5331 return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2SEL)); in LL_RCC_PLL2_GetSource()
5373 SET_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP); in LL_RCC_PLL2_EnableBypass()
5384 CLEAR_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP); in LL_RCC_PLL2_DisableBypass()
5394 return ((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2BYP) == RCC_PLL2CFGR1_PLL2BYP) ? 1UL : 0UL); in LL_RCC_PLL2_IsEnabledBypass()
5524 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN, N << RCC_PLL2CFGR1_PLL2DIVN_Pos); in LL_RCC_PLL2_SetN()
5535 …return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVN) >> RCC_PLL2CFGR1_PLL2DIVN_Pos)… in LL_RCC_PLL2_GetN()
5546 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM, M << RCC_PLL2CFGR1_PLL2DIVM_Pos); in LL_RCC_PLL2_SetM()
5556 return (uint32_t)(READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_PLL2DIVM) >> RCC_PLL2CFGR1_PLL2DIVM_Pos); in LL_RCC_PLL2_GetM()
Dstm32n6xx_hal_rcc.h3740 …MODIFY_REG(RCC->PLL2CFGR1, (RCC_PLL2CFGR1_PLL2SEL | RCC_PLL2CFGR1_PLL2BYP | RCC_PLL2CFGR1_PLL2DIVM…
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_rcc.c283 WRITE_REG(RCC->PLL2CFGR1, 0x08000000U); in HAL_RCC_DeInit()
1692 cfgr_value = RCC->PLL2CFGR1; in HAL_RCC_GetOscConfig()
1705 cfgr_value = RCC->PLL2CFGR1; in HAL_RCC_GetOscConfig()
Dstm32n6xx_ll_rcc.c236 WRITE_REG(RCC->PLL2CFGR1, 0x08000000U); in LL_RCC_DeInit()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_ll_rcc.h4316 return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVN) >> RCC_PLL2CFGR1_DIVN_Pos) + 1U); in LL_RCC_PLL2_GetN()
4326 …return (uint32_t)((READ_BIT(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1U… in LL_RCC_PLL2_GetM()
4377 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVN, (DIVN - 1U) << RCC_PLL2CFGR1_DIVN_Pos); in LL_RCC_PLL2_SetN()
4388 MODIFY_REG(RCC->PLL2CFGR1, RCC_PLL2CFGR1_DIVM2, (DIVM2 - 1U) << RCC_PLL2CFGR1_DIVM2_Pos); in LL_RCC_PLL2_SetM()
Dstm32mp1xx_hal_rcc.h3344 do{ MODIFY_REG( RCC->PLL2CFGR1, (RCC_PLL2CFGR1_DIVN | RCC_PLL2CFGR1_DIVM2) , \
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dsystem_stm32n6xx_s.c320 pllcfgr = READ_REG(RCC->PLL2CFGR1); in SystemCoreClockUpdate()
Dsystem_stm32n6xx_fsbl.c377 pllcfgr = READ_REG(RCC->PLL2CFGR1); in SystemCoreClockUpdate()
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h1580 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151fxx_cm4.h1546 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151axx_ca7.h1580 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151axx_cm4.h1546 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151dxx_cm4.h1546 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151cxx_ca7.h1580 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151cxx_cm4.h1546 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp151fxx_ca7.h1580 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153axx_ca7.h1681 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153axx_cm4.h1647 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153cxx_ca7.h1681 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153cxx_cm4.h1647 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153dxx_ca7.h1681 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153dxx_cm4.h1647 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member
Dstm32mp153fxx_ca7.h1681 …__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 Configuration Register 1 … member

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