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Searched refs:PARAM (Results 1 – 25 of 49) sorted by relevance

12

/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_mdf.h934 #define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ argument
935 ((PARAM) == MDF1_Filter1))
937 #define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ argument
938 ((PARAM) == MDF1_Filter1) || \
939 ((PARAM) == MDF1_Filter2) || \
940 ((PARAM) == MDF1_Filter3) || \
941 ((PARAM) == MDF1_Filter4) || \
942 ((PARAM) == MDF1_Filter5))
945 #define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0) argument
948 #define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ argument
[all …]
Dstm32u5xx_hal_gfxtim.h572 #define IS_GFXTIM_INTERRUPT(PARAM) (((PARAM) == GFXTIM_IT_ENABLE ) || \ argument
573 ((PARAM) == GFXTIM_IT_DISABLE ))
575 #define IS_GFXTIM_SYNC_SRC(PARAM) (((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_0) || \ argument
576 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_1) || \
577 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_2) || \
578 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_3))
580 #define IS_GFXTIM_TE_SRC(PARAM) (((PARAM) == GFXTIM_TE_SRC_GPIO ) || \ argument
581 ((PARAM) == GFXTIM_TE_SRC_ITE ) || \
582 ((PARAM) == GFXTIM_TE_SRC_HSYNC ) || \
583 ((PARAM) == GFXTIM_TE_SRC_VSYNC ))
[all …]
Dstm32u5xx_ll_fmac.h378 SET_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_EnableStart()
389 CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_DisableStart()
400 return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL); in LL_FMAC_IsEnabledStart()
417 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function); in LL_FMAC_SetFunction()
433 return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC)); in LL_FMAC_GetFunction()
446 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos); in LL_FMAC_SetParamR()
457 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos); in LL_FMAC_GetParamR()
470 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos); in LL_FMAC_SetParamQ()
481 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos); in LL_FMAC_GetParamQ()
494 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); in LL_FMAC_SetParamP()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_mdf.h927 #define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ argument
928 ((PARAM) == MDF1_Filter1) || \
929 ((PARAM) == MDF1_Filter2) || \
930 ((PARAM) == MDF1_Filter3) || \
931 ((PARAM) == MDF1_Filter4) || \
932 ((PARAM) == MDF1_Filter5))
934 #define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0) argument
936 #define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ argument
937 ((PARAM) == MDF_BITSTREAM0_FALLING) || \
938 ((PARAM) == MDF_BITSTREAM1_RISING) || \
[all …]
Dstm32n6xx_hal_gfxtim.h572 #define IS_GFXTIM_INTERRUPT(PARAM) (((PARAM) == GFXTIM_IT_ENABLE ) || \ argument
573 ((PARAM) == GFXTIM_IT_DISABLE ))
575 #define IS_GFXTIM_SYNC_SRC(PARAM) (((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_0) || \ argument
576 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_1) || \
577 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_2) || \
578 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_3))
580 #define IS_GFXTIM_TE_SRC(PARAM) (((PARAM) == GFXTIM_TE_SRC_GPIO ) || \ argument
581 ((PARAM) == GFXTIM_TE_SRC_ITE ) || \
582 ((PARAM) == GFXTIM_TE_SRC_HSYNC ) || \
583 ((PARAM) == GFXTIM_TE_SRC_VSYNC ))
[all …]
Dstm32n6xx_hal_dts.h221 #define IS_DTS_SENSOR_MODE(PARAM) (((PARAM) == DTS_SENSOR_MODE_DISABLE) || \ argument
222 ((PARAM) == DTS_SENSOR_MODE_SINGLE) || \
223 ((PARAM) == DTS_SENSOR_MODE_CONTINUOUS) || \
224 ((PARAM) == DTS_SENSOR_MODE_TRIGGER))
226 #define IS_DTS_SENSOR_RESOLUTION(PARAM) (((PARAM) == DTS_SENSOR_RESOLUTION_12BITS) || \ argument
227 ((PARAM) == DTS_SENSOR_RESOLUTION_10BITS) || \
228 ((PARAM) == DTS_SENSOR_RESOLUTION_8BITS))
230 #define IS_DTS_SENSOR_TRIGGER(PARAM) (((PARAM) == DTS_SENSOR_TRIGGER_LPTIM4_OUT) || \ argument
231 ((PARAM) == DTS_SENSOR_TRIGGER_LPTIM2_CH1) || \
232 ((PARAM) == DTS_SENSOR_TRIGGER_LPTIM3_CH1) || \
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_gfxtim.h572 #define IS_GFXTIM_INTERRUPT(PARAM) (((PARAM) == GFXTIM_IT_ENABLE ) || \ argument
573 ((PARAM) == GFXTIM_IT_DISABLE ))
575 #define IS_GFXTIM_SYNC_SRC(PARAM) (((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_0) || \ argument
576 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_1) || \
577 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_2) || \
578 ((PARAM) == GFXTIM_SYNC_SRC_HSYNC_VSYNC_3))
580 #define IS_GFXTIM_TE_SRC(PARAM) (((PARAM) == GFXTIM_TE_SRC_GPIO ) || \ argument
581 ((PARAM) == GFXTIM_TE_SRC_ITE ) || \
582 ((PARAM) == GFXTIM_TE_SRC_HSYNC ) || \
583 ((PARAM) == GFXTIM_TE_SRC_VSYNC ))
[all …]
Dstm32h7rsxx_hal_mdf.h652 #define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ argument
653 ((PARAM) == MDF_BITSTREAM0_FALLING))
655 #define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U)) argument
657 #define IS_MDF_OUTPUT_CLOCK_PINS(PARAM) (((PARAM) == MDF_OUTPUT_CLOCK_0) || \ argument
658 ((PARAM) == MDF_OUTPUT_CLOCK_1) || \
659 ((PARAM) == MDF_OUTPUT_CLOCK_ALL))
661 #define IS_MDF_OUTPUT_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 16U)) argument
663 #define IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \ argument
664 ((PARAM) == MDF_CLOCK_TRIG_EXTI15))
666 #define IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_RISING_EDGE) || \ argument
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_fmac.h378 SET_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_EnableStart()
389 CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_DisableStart()
400 return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL); in LL_FMAC_IsEnabledStart()
417 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function); in LL_FMAC_SetFunction()
433 return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC)); in LL_FMAC_GetFunction()
446 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos); in LL_FMAC_SetParamR()
457 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos); in LL_FMAC_GetParamR()
470 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos); in LL_FMAC_SetParamQ()
481 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos); in LL_FMAC_GetParamQ()
494 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); in LL_FMAC_SetParamP()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_fmac.h378 SET_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_EnableStart()
389 CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_DisableStart()
400 return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL); in LL_FMAC_IsEnabledStart()
417 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function); in LL_FMAC_SetFunction()
433 return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC)); in LL_FMAC_GetFunction()
446 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos); in LL_FMAC_SetParamR()
457 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos); in LL_FMAC_GetParamR()
470 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos); in LL_FMAC_SetParamQ()
481 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos); in LL_FMAC_GetParamQ()
494 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); in LL_FMAC_SetParamP()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_fmac.h378 SET_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_EnableStart()
389 CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START); in LL_FMAC_DisableStart()
400 return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL); in LL_FMAC_IsEnabledStart()
417 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function); in LL_FMAC_SetFunction()
433 return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC)); in LL_FMAC_GetFunction()
446 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos); in LL_FMAC_SetParamR()
457 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos); in LL_FMAC_GetParamR()
470 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos); in LL_FMAC_SetParamQ()
481 return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos); in LL_FMAC_GetParamQ()
494 MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); in LL_FMAC_SetParamP()
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_fmac.c305 ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
941 WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam)); in HAL_FMAC_FilterStart()
1211 CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START); in HAL_FMAC_FilterStop()
1791 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterConfig()
1909 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
1945 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
2037 while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_WaitOnStartUntilTimeout()
2385 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterConfig()
2392 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_DMAFilterConfig()
2436 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterPreload()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_fmac.c305 ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
941 WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam)); in HAL_FMAC_FilterStart()
1211 CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START); in HAL_FMAC_FilterStop()
1791 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterConfig()
1909 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
1945 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
2037 while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_WaitOnStartUntilTimeout()
2385 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterConfig()
2392 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_DMAFilterConfig()
2436 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterPreload()
[all …]
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_fmac.c305 ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
941 WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam)); in HAL_FMAC_FilterStart()
1211 CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START); in HAL_FMAC_FilterStop()
1792 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterConfig()
1939 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
1999 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
2115 while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_WaitOnStartUntilTimeout()
2551 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterConfig()
2558 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_DMAFilterConfig()
2603 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterPreload()
[all …]
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_fmac.c305 ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
941 WRITE_REG(hfmac->Instance->PARAM, (uint32_t)(hfmac->FilterParam)); in HAL_FMAC_FilterStart()
1211 CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START); in HAL_FMAC_FilterStop()
1792 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterConfig()
1939 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
1999 WRITE_REG(hfmac->Instance->PARAM, \ in FMAC_FilterPreload()
2115 while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_WaitOnStartUntilTimeout()
2551 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterConfig()
2558 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) in FMAC_DMAFilterConfig()
2603 if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) in FMAC_DMAFilterPreload()
[all …]
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h443 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g411xc.h458 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g441xx.h453 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32gbk1cb.h451 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g431xx.h452 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g4a1xx.h466 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g491xx.h465 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g473xx.h481 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g471xx.h474 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member
Dstm32g483xx.h482 …__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C … member

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