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Searched refs:OCTOSPI_WPCCR_ISIZE_Pos (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l5xx/soc/
Dstm32l552xx.h9692 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
9693 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
9695 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
9696 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32l562xx.h10024 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
10025 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
10027 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
10028 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h7a3xx.h18983 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
18984 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
18986 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
18987 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7b0xx.h19463 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
19464 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
19466 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
19467 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7b0xxq.h19475 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
19476 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
19478 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
19479 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7a3xxq.h18995 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
18996 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
18998 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
18999 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7b3xx.h19470 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
19471 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
19473 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
19474 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h7b3xxq.h19482 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
19483 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
19485 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
19486 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h730xxq.h21163 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
21164 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
21166 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
21167 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h733xx.h21151 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
21152 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
21154 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
21155 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h725xx.h20676 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
20677 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
20679 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
20680 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h730xx.h21151 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
21152 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
21154 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
21155 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h735xx.h21163 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
21164 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
21166 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
21167 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
Dstm32h723xx.h20664 #define OCTOSPI_WPCCR_ISIZE_Pos (4U) macro
20665 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
20667 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
20668 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h523xx.h11473 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32h562xx.h12199 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32h533xx.h11882 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32h573xx.h14692 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32h563xx.h14283 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h12572 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32u535xx.h12172 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32u575xx.h13207 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32u585xx.h13656 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32u595xx.h13556 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro
Dstm32u5a5xx.h14005 #define OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos macro

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