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Searched refs:NODE_CTR1_DEFAULT_OFFSET (Results 1 – 22 of 22) sorted by relevance

/hal_stm32-latest/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_dma_ex.c3713 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | in DMA_List_BuildNode()
3723 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3729 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; in DMA_List_BuildNode()
3737 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= in DMA_List_BuildNode()
3949 …pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3950 …pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3951 …pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3952 …pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3953 pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3955 pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
[all …]
Dstm32h5xx_hal_sram.c692 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Read_DMA()
794 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Write_DMA()
Dstm32h5xx_hal_sdram.c742 …data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CT… in HAL_SDRAM_Read_DMA()
846 …data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CT… in HAL_SDRAM_Write_DMA()
Dstm32h5xx_hal_xspi.c1444 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1529 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Transmit_DMA()
1629 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
1715 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Receive_DMA()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_dma_ex.c3714 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | in DMA_List_BuildNode()
3724 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3730 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; in DMA_List_BuildNode()
3738 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= in DMA_List_BuildNode()
3948 …pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3949 …pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3950 …pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3951 …pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3952 pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3954 pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
[all …]
Dstm32u5xx_hal_sram.c692 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Read_DMA()
794 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Write_DMA()
Dstm32u5xx_hal_ospi.c1427 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_OSPI_Transmit_DMA()
1512 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_OSPI_Transmit_DMA()
1608 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_OSPI_Receive_DMA()
1694 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_OSPI_Receive_DMA()
Dstm32u5xx_hal_xspi.c1591 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1676 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Transmit_DMA()
1776 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
1862 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Receive_DMA()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_dma_ex.c3523 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | in DMA_List_BuildNode()
3533 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3539 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; in DMA_List_BuildNode()
3547 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= in DMA_List_BuildNode()
3635 …pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3636 …pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3637 …pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3638 …pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3639 pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3641 pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
[all …]
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_dma_ex.c3733 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | in DMA_List_BuildNode()
3743 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; in DMA_List_BuildNode()
3749 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; in DMA_List_BuildNode()
3757 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= in DMA_List_BuildNode()
3969 …pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3970 …pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3971 …pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3972 …pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3973 pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3975 pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
[all …]
Dstm32n6xx_hal_sram.c691 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Read_DMA()
793 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Write_DMA()
Dstm32n6xx_hal_sdram.c741 …data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CT… in HAL_SDRAM_Read_DMA()
845 …data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CT… in HAL_SDRAM_Write_DMA()
Dstm32n6xx_hal_xspi.c1471 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1556 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Transmit_DMA()
1656 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
1742 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Receive_DMA()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_dma_ex.c3697 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | in DMA_List_BuildNode()
3708 pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= in DMA_List_BuildNode()
3909 …pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3910 …pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3911 …pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3912 …pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] &… in DMA_List_GetNodeConfig()
3913 pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3915 pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3917 pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
3919 pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & in DMA_List_GetNodeConfig()
[all …]
Dstm32h7rsxx_hal_sram.c691 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Read_DMA()
793 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Write_DMA()
Dstm32h7rsxx_hal_sdram.c741 …data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CT… in HAL_SDRAM_Read_DMA()
845 …data_width = hsdram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CT… in HAL_SDRAM_Write_DMA()
Dstm32h7rsxx_hal_xspi.c1464 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Transmit_DMA()
1549 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Transmit_DMA()
1649 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_XSPI_Receive_DMA()
1735 MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ in HAL_XSPI_Receive_DMA()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_hal_dma_ex.h487 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ macro
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_hal_dma_ex.h625 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ macro
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_hal_dma_ex.h609 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ macro
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_hal_dma_ex.h624 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ macro
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_hal_dma_ex.h766 #define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ macro