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Searched refs:MCHDLYCR (Results 1 – 4 of 4) sorted by relevance

/hal_stm32-latest/stm32cube/stm32f4xx/drivers/include/
Dstm32f4xx_ll_system.h754 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource); in LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection()
766 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL)); in LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection()
778 SET_BIT(SYSCFG->MCHDLYCR, MCHDLY); in LL_SYSCFG_DFSDM_EnableDelayClock()
791 CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY); in LL_SYSCFG_DFSDM_DisableDelayClock()
806 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); in LL_SYSCFG_DFSDM_SetDataIn0Source()
823 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); in LL_SYSCFG_DFSDM_GetDataIn0Source()
837 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF)); in LL_SYSCFG_DFSDM_SetDataIn2Source()
854 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); in LL_SYSCFG_DFSDM_GetDataIn2Source()
867 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source); in LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution()
879 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL)); in LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution()
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/hal_stm32-latest/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_hal_dfsdm.c3721 tmp = SYSCFG->MCHDLYCR; in HAL_DFSDM_BitstreamClock_Start()
3724 SYSCFG->MCHDLYCR = (tmp|SYSCFG_MCHDLYCR_BSCKSEL); in HAL_DFSDM_BitstreamClock_Start()
3737 tmp = SYSCFG->MCHDLYCR; in HAL_DFSDM_BitstreamClock_Stop()
3740 SYSCFG->MCHDLYCR = tmp; in HAL_DFSDM_BitstreamClock_Stop()
3757 tmp = SYSCFG->MCHDLYCR; in HAL_DFSDM_DisableDelayClock()
3767 SYSCFG->MCHDLYCR = tmp; in HAL_DFSDM_DisableDelayClock()
3784 tmp = SYSCFG->MCHDLYCR; in HAL_DFSDM_EnableDelayClock()
3787 SYSCFG->MCHDLYCR = (tmp|MCHDLY); in HAL_DFSDM_EnableDelayClock()
3804 tmp = SYSCFG->MCHDLYCR; in HAL_DFSDM_ClockIn_SourceSelection()
3820 SYSCFG->MCHDLYCR = (source|tmp); in HAL_DFSDM_ClockIn_SourceSelection()
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/hal_stm32-latest/stm32cube/stm32f4xx/soc/
Dstm32f423xx.h471 …__IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset… member
Dstm32f413xx.h470 …__IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset… member