Home
last modified time | relevance | path

Searched refs:LPTIM_CFGR2_IN1SEL_3_Msk (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h33213 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33214 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151fxx_cm4.h33376 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33377 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151axx_ca7.h33213 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33214 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151axx_cm4.h33179 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33180 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151dxx_cm4.h33179 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33180 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151cxx_ca7.h33410 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33411 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151cxx_cm4.h33376 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33377 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp151fxx_ca7.h33410 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
33411 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153axx_ca7.h34764 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34765 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153axx_cm4.h34730 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34731 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153cxx_ca7.h34961 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34962 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153cxx_cm4.h34927 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34928 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153dxx_ca7.h34764 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34765 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153dxx_cm4.h34730 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34731 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153fxx_ca7.h34961 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34962 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp153fxx_cm4.h34927 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
34928 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157axx_ca7.h35987 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
35988 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157axx_cm4.h35953 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
35954 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157cxx_ca7.h36184 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
36185 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157cxx_cm4.h36150 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
36151 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157dxx_ca7.h35987 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
35988 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157dxx_cm4.h35953 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
35954 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157fxx_ca7.h36184 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
36185 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */
Dstm32mp157fxx_cm4.h36150 #define LPTIM_CFGR2_IN1SEL_3_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_3_Pos) /*!< 0x00000008 */ macro
36151 #define LPTIM_CFGR2_IN1SEL_3 LPTIM_CFGR2_IN1SEL_3_Msk /*!< Bit 3 */