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Searched refs:LPTIM_CFGR2_IN1SEL_1_Msk (Results 1 – 24 of 24) sorted by relevance

/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h33207 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33208 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151fxx_cm4.h33370 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33371 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151axx_ca7.h33207 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33208 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151axx_cm4.h33173 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33174 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151dxx_cm4.h33173 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33174 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151cxx_ca7.h33404 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33405 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151cxx_cm4.h33370 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33371 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp151fxx_ca7.h33404 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
33405 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153axx_ca7.h34758 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34759 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153axx_cm4.h34724 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34725 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153cxx_ca7.h34955 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34956 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153cxx_cm4.h34921 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34922 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153dxx_ca7.h34758 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34759 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153dxx_cm4.h34724 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34725 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153fxx_ca7.h34955 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34956 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp153fxx_cm4.h34921 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
34922 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157axx_ca7.h35981 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
35982 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157axx_cm4.h35947 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
35948 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157cxx_ca7.h36178 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
36179 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157cxx_cm4.h36144 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
36145 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157dxx_ca7.h35981 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
35982 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157dxx_cm4.h35947 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
35948 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157fxx_ca7.h36178 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
36179 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */
Dstm32mp157fxx_cm4.h36144 #define LPTIM_CFGR2_IN1SEL_1_Msk (0x1UL << LPTIM_CFGR2_IN1SEL_1_Pos) /*!< 0x00000002 */ macro
36145 #define LPTIM_CFGR2_IN1SEL_1 LPTIM_CFGR2_IN1SEL_1_Msk /*!< Bit 1 */