1 /** 2 ********************************************************************************************************************** 3 * @file stm32u5xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32U5xx_HAL_DMA_H 21 #define STM32U5xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ----------------------------------------------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 39 /* Exported types ----------------------------------------------------------------------------------------------------*/ 40 41 /** @defgroup DMA_Exported_Types DMA Exported Types 42 * @brief DMA Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief DMA Transfer Configuration Structure definition. 48 */ 49 typedef struct 50 { 51 uint32_t Request; /*!< Specifies the DMA channel request. 52 This parameter can be a value of @ref DMA_Request_Selection */ 53 54 uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. 55 Block Hardware request feature can be used only with dedicated peripherals. 56 This parameter can be a value of @ref DMA_Block_Request */ 57 58 uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. 59 This parameter can be a value of @ref DMA_Transfer_Direction */ 60 61 uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. 62 This parameter can be a value of @ref DMA_Source_Increment_Mode */ 63 64 uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. 65 This parameter can be a value of @ref DMA_Destination_Increment_Mode */ 66 67 uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. 68 This parameter can be a value of @ref DMA_Source_Data_Width */ 69 70 uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. 71 This parameter can be a value of @ref DMA_Destination_Data_Width */ 72 73 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 74 This parameter can be a value of @ref DMA_Priority_Level */ 75 76 uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA 77 channel. 78 This parameter can be a value between 1 and 64 */ 79 80 uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the 81 DMA channel. 82 This parameter can be a value between 1 and 64 */ 83 84 uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. 85 This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ 86 87 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 88 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 89 90 uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. 91 This parameter can be a value of @ref DMA_Transfer_Mode */ 92 93 } DMA_InitTypeDef; 94 95 /** 96 * @brief DMA Linked-List Configuration Structure Definition. 97 */ 98 typedef struct 99 { 100 uint32_t Priority; /*!< Specifies the priority level for the DMA channel. 101 This parameter can be a value of @ref DMA_Priority_Level */ 102 103 uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. 104 This parameter can be a value of @ref DMAEx_Link_Step_Mode */ 105 106 uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. 107 This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ 108 109 uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. 110 This parameter can be a value of @ref DMA_Transfer_Event_Mode */ 111 112 uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. 113 This parameter can be a value of @ref DMAEx_LinkedList_Mode */ 114 115 } DMA_InitLinkedListTypeDef; 116 117 /** 118 * @brief HAL DMA State Enumeration Definition. 119 */ 120 typedef enum 121 { 122 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 123 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 124 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 125 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ 126 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ 127 HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ 128 129 } HAL_DMA_StateTypeDef; 130 131 /** 132 * @brief HAL DMA Level Complete Enumeration Definition. 133 */ 134 typedef enum 135 { 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ 137 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ 138 139 } HAL_DMA_LevelCompleteTypeDef; 140 141 /** 142 * @brief HAL DMA Callbacks IDs Enumeration Definition. 143 */ 144 typedef enum 145 { 146 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ 147 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ 148 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ 149 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ 150 HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ 151 HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ 152 153 } HAL_DMA_CallbackIDTypeDef; 154 155 /** 156 * @brief DMA handle Structure definition 157 */ 158 typedef struct __DMA_HandleTypeDef 159 { 160 DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ 161 162 DMA_InitTypeDef Init; /*!< DMA channel init parameters */ 163 164 DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ 165 166 HAL_LockTypeDef Lock; /*!< DMA locking object */ 167 168 uint32_t Mode; /*!< DMA transfer mode */ 169 170 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 171 172 __IO uint32_t ErrorCode; /*!< DMA error code */ 173 174 void *Parent; /*!< Parent object state */ 175 176 void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 177 178 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ 179 180 void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 181 182 void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ 183 184 void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ 185 186 struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ 187 188 } DMA_HandleTypeDef; 189 /** 190 * @} 191 */ 192 193 194 /* Exported constants ------------------------------------------------------------------------------------------------*/ 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants 196 * @brief DMA Exported constants 197 * @{ 198 */ 199 200 /** @defgroup DMA_Error_Codes DMA Error Codes 201 * @brief DMA Error Codes 202 * @{ 203 */ 204 #define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ 205 #define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ 206 #define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ 207 #define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ 208 #define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ 209 #define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ 210 #define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ 211 #define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ 212 #define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ 213 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ 214 /** 215 * @} 216 */ 217 218 /** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition 219 * @brief DMA Interrupt Enable Definition 220 * @{ 221 */ 222 #define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ 223 #define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ 224 #define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ 225 #define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ 226 #define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ 227 #define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ 228 #define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMA_Flag_Definition DMA Flag Definition 234 * @brief DMA Flag Definition 235 * @{ 236 */ 237 #define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ 238 #define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ 239 #define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ 240 #define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ 241 #define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ 242 #define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ 243 #define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ 244 #define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ 245 /** 246 * @} 247 */ 248 249 /** @defgroup DMA_Request_Selection DMA Request Selection 250 * @brief DMA Request Selection 251 * @{ 252 */ 253 /* GPDMA1 requests */ 254 #define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ 255 #define GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW request is ADC4 */ 256 #define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ 257 #define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ 258 #define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ 259 #define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ 260 #define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ 261 #define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ 262 #define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ 263 #define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ 264 #define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ 265 #define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ 266 #define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ 267 #define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ 268 #define GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW request is I2C1_EVC */ 269 #define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ 270 #define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ 271 #define GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW request is I2C2_EVC */ 272 #define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ 273 #define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ 274 #define GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW request is I2C3_EVC */ 275 #define GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW request is I2C4_RX */ 276 #define GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW request is I2C4_TX */ 277 #define GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW request is I2C4_EVC */ 278 #define GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW request is USART1_RX */ 279 #define GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW request is USART1_TX */ 280 #if defined(USART2) 281 #define GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW request is USART2_RX */ 282 #define GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW request is USART2_TX */ 283 #endif /* USART2 */ 284 #define GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW request is USART3_RX */ 285 #define GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW request is USART3_TX */ 286 #define GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW request is UART4_RX */ 287 #define GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW request is UART4_TX */ 288 #define GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW request is UART5_RX */ 289 #define GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW request is UART5_TX */ 290 #define GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW request is LPUART1_RX */ 291 #define GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW request is LPUART1_TX */ 292 #define GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW request is SAI1_A */ 293 #define GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW request is SAI1_B */ 294 #if defined(SAI2) 295 #define GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW request is SAI2_A */ 296 #define GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW request is SAI2_B */ 297 #endif /* SAI2 */ 298 #define GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW request is OCTOSPI1 */ 299 #if defined(OCTOSPI2) 300 #define GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW request is OCTOSPI2 */ 301 #endif /* OCTOSPI2 */ 302 #define GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW request is TIM1_CH1 */ 303 #define GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW request is TIM1_CH2 */ 304 #define GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW request is TIM1_CH3 */ 305 #define GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW request is TIM1_CH4 */ 306 #define GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW request is TIM1_UP */ 307 #define GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW request is TIM1_TRIG */ 308 #define GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW request is TIM1_COM */ 309 #define GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW request is TIM8_CH1 */ 310 #define GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW request is TIM8_CH2 */ 311 #define GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW request is TIM8_CH3 */ 312 #define GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW request is TIM8_CH4 */ 313 #define GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW request is TIM8_UP */ 314 #define GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW request is TIM8_TRIG */ 315 #define GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW request is TIM8_COM */ 316 #define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ 317 #define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ 318 #define GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW request is TIM2_CH3 */ 319 #define GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW request is TIM2_CH4 */ 320 #define GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW request is TIM2_UP */ 321 #define GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW request is TIM3_CH1 */ 322 #define GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW request is TIM3_CH2 */ 323 #define GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW request is TIM3_CH3 */ 324 #define GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW request is TIM3_CH4 */ 325 #define GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW request is TIM3_UP */ 326 #define GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW request is TIM3_TRIG */ 327 #define GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW request is TIM4_CH1 */ 328 #define GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW request is TIM4_CH2 */ 329 #define GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW request is TIM4_CH3 */ 330 #define GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW request is TIM4_CH4 */ 331 #define GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW request is TIM4_UP */ 332 #define GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW request is TIM5_CH1 */ 333 #define GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW request is TIM5_CH2 */ 334 #define GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW request is TIM5_CH3 */ 335 #define GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW request is TIM5_CH4 */ 336 #define GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW request is TIM5_UP */ 337 #define GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW request is TIM5_TRIG */ 338 #define GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW request is TIM15_CH1 */ 339 #define GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW request is TIM15_UP */ 340 #define GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW request is TIM15_TRIG */ 341 #define GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW request is TIM15_COM */ 342 #define GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW request is TIM16_CH1 */ 343 #define GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW request is TIM16_UP */ 344 #define GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW request is TIM17_CH1 */ 345 #define GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW request is TIM17_UP */ 346 #define GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW request is DCMI_PSSI */ 347 #define GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW request is AES_IN */ 348 #define GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW request is AES_OUT */ 349 #define GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW request is HASH_IN */ 350 #if defined(UCPD1) 351 #define GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW request is UCPD1_TX */ 352 #define GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW request is UCPD1_RX */ 353 #endif /* UCPD1 */ 354 #define GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW request is MDF1_FLT0 */ 355 #define GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW request is MDF1_FLT1 */ 356 #define GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW request is MDF1_FLT2 */ 357 #define GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW request is MDF1_FLT3 */ 358 #define GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW request is MDF1_FLT4 */ 359 #define GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW request is MDF1_FLT5 */ 360 #define GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW request is ADF1_FLT0 */ 361 #define GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW request is FMAC_READ */ 362 #define GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW request is FMAC_WRITE */ 363 #define GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW request is CORDIC_READ */ 364 #define GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW request is CORDIC_WRITE */ 365 #define GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW request is SAES_IN */ 366 #define GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW request is SAES_OUT */ 367 #define GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW request is LPTIM1_IC1 */ 368 #define GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW request is LPTIM1_IC2 */ 369 #define GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW request is LPTIM1_UE */ 370 #define GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW request is LPTIM2_IC1 */ 371 #define GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW request is LPTIM2_IC2 */ 372 #define GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW request is LPTIM2_UE */ 373 #define GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW request is LPTIM3_IC1 */ 374 #define GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW request is LPTIM3_IC2 */ 375 #define GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW request is LPTIM3_UE */ 376 #if defined (HSPI1_BASE) 377 #define GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ 378 #endif /* HSPI1_BASE */ 379 #if defined (I2C5) 380 #define GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ 381 #define GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ 382 #define GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ 383 #endif /* I2C5 */ 384 #if defined (I2C6) 385 #define GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ 386 #define GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ 387 #define GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ 388 #endif /* I2C6 */ 389 #if defined (USART6) 390 #define GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ 391 #define GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ 392 #endif /* USART6 */ 393 #if defined (ADC2) 394 #define GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ 395 #endif /* ADC2 */ 396 #if defined (JPEG) 397 #define GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ 398 #define GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ 399 #endif /* JPEG */ 400 401 /* LPDMA1 requests */ 402 #define LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW request is LPUART1_RX */ 403 #define LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW request is LPUART1_TX */ 404 #define LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW request is SPI3_RX */ 405 #define LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW request is SPI3_TX */ 406 #define LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW request is I2C3_RX */ 407 #define LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW request is I2C3_TX */ 408 #define LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW request is I2C3_EVC */ 409 #define LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW request is ADC4 */ 410 #define LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW request is DAC1_CH1 */ 411 #define LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW request is DAC1_CH2 */ 412 #define LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW request is ADF1_FLT0 */ 413 #define LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW request is LPTIM1_IC1 */ 414 #define LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW request is LPTIM1_IC2 */ 415 #define LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW request is LPTIM1_UE */ 416 #define LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW request is LPTIM3_IC1 */ 417 #define LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW request is LPTIM3_IC2 */ 418 #define LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW request is LPTIM3_UE */ 419 420 /* Software request */ 421 #define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup DMA_Block_Request DMA Block Request 427 * @brief DMA Block Request 428 * @{ 429 */ 430 #define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ 431 #define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ 432 /** 433 * @} 434 */ 435 436 /** @defgroup DMA_Transfer_Direction DMA Transfer Direction 437 * @brief DMA transfer direction 438 * @{ 439 */ 440 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 441 #define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ 442 #define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode 448 * @brief DMA Source Increment Mode 449 * @{ 450 */ 451 #define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ 452 #define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ 453 /** 454 * @} 455 */ 456 457 /** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode 458 * @brief DMA Destination Increment Mode 459 * @{ 460 */ 461 #define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ 462 #define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup DMA_Source_Data_Width DMA Source Data Width 468 * @brief DMA Source Data Width 469 * @{ 470 */ 471 #define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ 472 #define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ 473 #define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup DMA_Destination_Data_Width DMA destination Data Width 479 * @brief DMA destination Data Width 480 * @{ 481 */ 482 #define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ 483 #define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ 484 #define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ 485 486 /** 487 * @} 488 */ 489 490 /** @defgroup DMA_Priority_Level DMA Priority Level 491 * @brief DMA Priority Level 492 * @{ 493 */ 494 #define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ 495 #define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ 496 #define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ 497 #define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ 498 /** 499 * @} 500 */ 501 502 /** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port 503 * @brief DMA Transfer Allocated Port 504 * @{ 505 */ 506 #define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ 507 #define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ 508 #define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ 509 #define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ 510 /** 511 * @} 512 */ 513 514 /** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode 515 * @brief DMA Transfer Event Mode 516 * @{ 517 */ 518 #define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the 519 HT event is generated at the half of each block */ 520 #define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block 521 and the HT event is generated at the half of the repeated 522 block */ 523 #define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list 524 item and the HT event is generated at the half of each 525 linked-list item */ 526 #define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last 527 linked-list item and the HT event is generated at the half 528 of the last linked-list item */ 529 /** 530 * @} 531 */ 532 533 /** @defgroup DMA_Transfer_Mode DMA Transfer Mode 534 * @brief DMA Transfer Mode 535 * @{ 536 */ 537 #define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ 538 /** 539 * @} 540 */ 541 542 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 543 * @brief DMA Channel Security and Privilege Attributes 544 * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 545 * @{ 546 */ 547 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ 548 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 549 550 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ 551 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 552 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ 553 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 554 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ 555 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 556 557 #define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ 558 #define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ 559 /** 560 * @} 561 */ 562 563 564 /** 565 * @} 566 */ 567 568 569 /* Exported macro ----------------------------------------------------------------------------------------------------*/ 570 /** @defgroup DMA_Exported_Macros DMA Exported Macros 571 * @brief DMA Exported Macros 572 * @{ 573 */ 574 575 /** @brief Reset DMA handle state. 576 * @param __HANDLE__ : DMA handle. 577 * @retval None. 578 */ 579 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ 580 ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 581 582 /** 583 * @brief Enable the specified DMA Channel. 584 * @param __HANDLE__ : DMA handle. 585 * @retval None 586 */ 587 #define __HAL_DMA_ENABLE(__HANDLE__) \ 588 ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 589 590 /** 591 * @brief Disable the specified DMA Channel. 592 * @param __HANDLE__ : DMA handle. 593 * @retval None 594 */ 595 #define __HAL_DMA_DISABLE(__HANDLE__) \ 596 ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) 597 598 /** 599 * @brief Get the DMA channel pending flags. 600 * @param __HANDLE__ : DMA handle. 601 * @param __FLAG__ : Get the specified flag. 602 * This parameter can be any combination of the following values: 603 * @arg DMA_FLAG_TC : Transfer Complete flag. 604 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 605 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 606 * @arg DMA_FLAG_ULE : Update linked-list Error flag. 607 * @arg DMA_FLAG_USE : User Setting Error flag. 608 * @arg DMA_FLAG_TO : Trigger Overrun flag. 609 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 610 * @arg DMA_FLAG_IDLEF : Idle flag. 611 * @retval The state of FLAG (SET or RESET). 612 */ 613 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ 614 ((__HANDLE__)->Instance->CSR & (__FLAG__)) 615 616 /** 617 * @brief Clear the DMA Channel pending flags. 618 * @param __HANDLE__ : DMA handle. 619 * @param __FLAG__ : Specifies the flag to clear. 620 * This parameter can be any combination of the following values: 621 * @arg DMA_FLAG_TC : Transfer Complete flag. 622 * @arg DMA_FLAG_HT : Half Transfer Complete flag. 623 * @arg DMA_FLAG_DTE : Data Transfer Error flag. 624 * @arg DMA_FLAG_ULE : Update Linked-List Error flag. 625 * @arg DMA_FLAG_USE : User Setting Error flag. 626 * @arg DMA_FLAG_TO : Trigger Overrun flag. 627 * @arg DMA_FLAG_SUSP : Completed Suspension flag. 628 * @retval None 629 */ 630 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 631 ((__HANDLE__)->Instance->CFCR = (__FLAG__)) 632 633 /** 634 * @brief Enable the specified DMA Channel interrupts. 635 * @param __HANDLE__ : DMA handle. 636 * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. 637 * This parameter can be any combination of the following values: 638 * @arg DMA_IT_TC : Transfer Complete interrupt. 639 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 640 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 641 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 642 * @arg DMA_IT_USE : User Setting Error interrupt. 643 * @arg DMA_IT_TO : Trigger Overrun interrupt. 644 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 645 * @retval None 646 */ 647 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 648 ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 649 650 /** 651 * @brief Disable the specified DMA Channel interrupts. 652 * @param __HANDLE__ : DMA handle. 653 * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. 654 * This parameter can be any combination of the following values: 655 * @arg DMA_IT_TC : Transfer Complete interrupt. 656 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 657 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 658 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 659 * @arg DMA_IT_USE : User Setting Error interrupt. 660 * @arg DMA_IT_TO : Trigger Overrun interrupt. 661 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 662 * @retval None 663 */ 664 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 665 ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 666 667 /** 668 * @brief Checks whether the specified DMA Channel interrupt is enabled or not. 669 * @param __HANDLE__ : DMA handle. 670 * @param __INTERRUPT__ : specifies the DMA interrupt source to check. 671 * @arg DMA_IT_TC : Transfer Complete interrupt. 672 * @arg DMA_IT_HT : Half Transfer Complete interrupt. 673 * @arg DMA_IT_DTE : Data Transfer Error interrupt. 674 * @arg DMA_IT_ULE : Update Linked-List Error interrupt. 675 * @arg DMA_IT_USE : User Setting Error interrupt. 676 * @arg DMA_IT_TO : Trigger Overrun interrupt. 677 * @arg DMA_IT_SUSP : Completed Suspension interrupt. 678 * @retval The state of DMA_IT (SET or RESET). 679 */ 680 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 681 (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 682 683 /** 684 * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. 685 * @param __HANDLE__ : DMA handle. 686 * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). 687 */ 688 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ 689 MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) 690 691 /** 692 * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. 693 * @param __HANDLE__ : DMA handle. 694 * @retval The number of remaining data units in the current DMA Stream transfer. 695 */ 696 #define __HAL_DMA_GET_COUNTER(__HANDLE__) \ 697 (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) 698 /** 699 * @} 700 */ 701 702 703 /* Include DMA HAL Extension module */ 704 #include "stm32u5xx_hal_dma_ex.h" 705 706 707 /* Exported functions ------------------------------------------------------------------------------------------------*/ 708 /** @defgroup DMA_Exported_Functions DMA Exported Functions 709 * @brief DMA Exported Functions 710 * @{ 711 */ 712 713 /** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions 714 * @brief Initialization and De-Initialization Functions 715 * @{ 716 */ 717 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); 718 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); 719 /** 720 * @} 721 */ 722 723 /** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions 724 * @brief I/O Operation Functions 725 * @{ 726 */ 727 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, 728 uint32_t SrcAddress, 729 uint32_t DstAddress, 730 uint32_t SrcDataSize); 731 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, 732 uint32_t SrcAddress, 733 uint32_t DstAddress, 734 uint32_t SrcDataSize); 735 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); 736 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); 737 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, 738 HAL_DMA_LevelCompleteTypeDef CompleteLevel, 739 uint32_t Timeout); 740 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); 741 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, 742 HAL_DMA_CallbackIDTypeDef CallbackID, 743 void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); 744 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, 745 HAL_DMA_CallbackIDTypeDef CallbackID); 746 /** 747 * @} 748 */ 749 750 /** @defgroup DMA_Exported_Functions_Group3 State and Error Functions 751 * @brief State and Error Functions 752 * @{ 753 */ 754 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); 755 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); 756 /** 757 * @} 758 */ 759 760 /** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions 761 * @brief DMA Attributes Functions 762 * @{ 763 */ 764 765 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, 766 uint32_t ChannelAttributes); 767 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, 768 uint32_t *const pChannelAttributes); 769 770 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 771 HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); 772 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 773 HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, 774 uint32_t *const pLockState); 775 776 777 /** 778 * @} 779 */ 780 781 /** 782 * @} 783 */ 784 785 786 /* Private constants -------------------------------------------------------------------------------------------------*/ 787 /** @defgroup DMA_Private_Constants DMA Private Constants 788 * @brief DMA Private Constants 789 * @{ 790 */ 791 #define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ 792 #define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ 793 #define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ 794 #define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ 795 #define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ 796 #define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ 797 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ 798 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ 799 #define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ 800 #define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ 801 #define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ 802 #define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ 803 /** 804 * @} 805 */ 806 807 808 /* Private macros ----------------------------------------------------------------------------------------------------*/ 809 /** @defgroup DMA_Private_Macros DMA Private Macros 810 * @brief DMA Private Macros 811 * @{ 812 */ 813 #define GET_DMA_INSTANCE(__HANDLE__) \ 814 ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) 815 816 #define GET_DMA_CHANNEL(__HANDLE__) \ 817 ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) 818 819 #define IS_DMA_MODE(MODE) \ 820 ((MODE) == DMA_NORMAL) 821 822 #define IS_DMA_DIRECTION(DIRECTION) \ 823 (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ 824 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 825 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 826 827 #define IS_DMA_LEVEL_COMPLETE(LEVEL) \ 828 (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ 829 ((LEVEL) == HAL_DMA_HALF_TRANSFER)) 830 831 #define IS_DMA_SOURCE_INC(INC) \ 832 (((INC) == DMA_SINC_FIXED) || \ 833 ((INC) == DMA_SINC_INCREMENTED)) 834 835 #define IS_DMA_DESTINATION_INC(INC) \ 836 (((INC) == DMA_DINC_FIXED) || \ 837 ((INC) == DMA_DINC_INCREMENTED)) 838 839 #define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ 840 (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ 841 ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ 842 ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) 843 844 #define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ 845 (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ 846 ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ 847 ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) 848 849 #define IS_DMA_BURST_LENGTH(LENGTH) \ 850 (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ 851 ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) 852 853 #define IS_DMA_PRIORITY(PRIORITY) \ 854 (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ 855 ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ 856 ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ 857 ((PRIORITY) == DMA_HIGH_PRIORITY)) 858 859 #define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ 860 (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) 861 862 #if defined (GPDMA1_REQUEST_JPEG_TX) 863 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_JPEG_TX)) 864 #elif defined (GPDMA1_REQUEST_ADC2) 865 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADC2)) 866 #else 867 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE)) 868 #endif /* GPDMA1_REQUEST_JPEG_TX */ 869 870 #define IS_DMA_BLOCK_HW_REQUEST(MODE) \ 871 (((MODE) == DMA_BREQ_SINGLE_BURST) || \ 872 ((MODE) == DMA_BREQ_BLOCK)) 873 874 #define IS_DMA_TCEM_EVENT_MODE(MODE) \ 875 (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ 876 ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ 877 ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ 878 ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) 879 880 #define IS_DMA_BLOCK_SIZE(SIZE) \ 881 (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) 882 883 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 884 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 885 (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ 886 (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ 887 (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) 888 #else 889 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ 890 (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 891 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 892 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 893 894 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 895 #define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ 896 (((INSTANCE)->SMISR & (GLOBAL_FLAG))) 897 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 898 #define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ 899 (((INSTANCE)->MISR & (GLOBAL_FLAG))) 900 901 /** 902 * @} 903 */ 904 905 906 /* Private functions -------------------------------------------------------------------------------------------------*/ 907 /** @defgroup DMA_Private_Functions DMA Private Functions 908 * @brief DMA Private Functions 909 * @{ 910 */ 911 912 /** 913 * @} 914 */ 915 916 /** 917 * @} 918 */ 919 920 /** 921 * @} 922 */ 923 924 /** 925 * @} 926 */ 927 928 #ifdef __cplusplus 929 } 930 #endif 931 932 #endif /* STM32U5xx_HAL_DMA_H */ 933
