1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32H7RSxx_LL_TIM_H
21 #define __STM32H7RSxx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7rsxx.h"
29
30 /** @addtogroup STM32H7RSxx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM9) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x04U, /* 7: TIMx_CH4N */
55 0x38U, /* 8: TIMx_CH5 */
56 0x38U /* 9: TIMx_CH6 */
57
58 };
59
60 static const uint8_t SHIFT_TAB_OCxx[] =
61 {
62 0U, /* 0: OC1M, OC1FE, OC1PE */
63 0U, /* 1: - NA */
64 8U, /* 2: OC2M, OC2FE, OC2PE */
65 0U, /* 3: - NA */
66 0U, /* 4: OC3M, OC3FE, OC3PE */
67 0U, /* 5: - NA */
68 8U, /* 6: OC4M, OC4FE, OC4PE */
69 0U, /* 7: - NA */
70 0U, /* 8: OC5M, OC5FE, OC5PE */
71 8U /* 9: OC6M, OC6FE, OC6PE */
72 };
73
74 static const uint8_t SHIFT_TAB_ICxx[] =
75 {
76 0U, /* 0: CC1S, IC1PSC, IC1F */
77 0U, /* 1: - NA */
78 8U, /* 2: CC2S, IC2PSC, IC2F */
79 0U, /* 3: - NA */
80 0U, /* 4: CC3S, IC3PSC, IC3F */
81 0U, /* 5: - NA */
82 8U, /* 6: CC4S, IC4PSC, IC4F */
83 0U, /* 7: - NA */
84 0U, /* 8: - NA */
85 0U /* 9: - NA */
86 };
87
88 static const uint8_t SHIFT_TAB_CCxP[] =
89 {
90 0U, /* 0: CC1P */
91 2U, /* 1: CC1NP */
92 4U, /* 2: CC2P */
93 6U, /* 3: CC2NP */
94 8U, /* 4: CC3P */
95 10U, /* 5: CC3NP */
96 12U, /* 6: CC4P */
97 14U, /* 7: CC4NP */
98 16U, /* 8: CC5P */
99 20U /* 9: CC6P */
100 };
101
102 static const uint8_t SHIFT_TAB_OISx[] =
103 {
104 0U, /* 0: OIS1 */
105 1U, /* 1: OIS1N */
106 2U, /* 2: OIS2 */
107 3U, /* 3: OIS2N */
108 4U, /* 4: OIS3 */
109 5U, /* 5: OIS3N */
110 6U, /* 6: OIS4 */
111 7U, /* 7: OIS4N */
112 8U, /* 8: OIS5 */
113 10U /* 9: OIS6 */
114 };
115 /**
116 * @}
117 */
118
119 /* Private constants ---------------------------------------------------------*/
120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
121 * @{
122 */
123
124 /* Defines used for the bit position in the register and perform offsets */
125 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
126
127 /* Generic bit definitions for TIMx_AF1 register */
128 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
129 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
130
131
132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
133 #define DT_DELAY_1 ((uint8_t)0x7F)
134 #define DT_DELAY_2 ((uint8_t)0x3F)
135 #define DT_DELAY_3 ((uint8_t)0x1F)
136 #define DT_DELAY_4 ((uint8_t)0x1F)
137
138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
139 #define DT_RANGE_1 ((uint8_t)0x00)
140 #define DT_RANGE_2 ((uint8_t)0x80)
141 #define DT_RANGE_3 ((uint8_t)0xC0)
142 #define DT_RANGE_4 ((uint8_t)0xE0)
143
144 /** Legacy definitions for compatibility purpose
145 @cond 0
146 */
147 /**
148 @endcond
149 */
150
151 /**
152 * @}
153 */
154
155 /* Private macros ------------------------------------------------------------*/
156 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
157 * @{
158 */
159 /** @brief Convert channel id into channel index.
160 * @param __CHANNEL__ This parameter can be one of the following values:
161 * @arg @ref LL_TIM_CHANNEL_CH1
162 * @arg @ref LL_TIM_CHANNEL_CH1N
163 * @arg @ref LL_TIM_CHANNEL_CH2
164 * @arg @ref LL_TIM_CHANNEL_CH2N
165 * @arg @ref LL_TIM_CHANNEL_CH3
166 * @arg @ref LL_TIM_CHANNEL_CH3N
167 * @arg @ref LL_TIM_CHANNEL_CH4
168 * @arg @ref LL_TIM_CHANNEL_CH4N
169 * @arg @ref LL_TIM_CHANNEL_CH5
170 * @arg @ref LL_TIM_CHANNEL_CH6
171 * @retval none
172 */
173 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
174 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
175 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
176 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
183
184 /** @brief Calculate the deadtime sampling period(in ps).
185 * @param __TIMCLK__ timer input clock frequency (in Hz).
186 * @param __CKD__ This parameter can be one of the following values:
187 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
188 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
190 * @retval none
191 */
192 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
193 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
194 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
195 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
196 /**
197 * @}
198 */
199
200
201 /* Exported types ------------------------------------------------------------*/
202 #if defined(USE_FULL_LL_DRIVER)
203 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
204 * @{
205 */
206
207 /**
208 * @brief TIM Time Base configuration structure definition.
209 */
210 typedef struct
211 {
212 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
213 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
214
215 This feature can be modified afterwards using unitary function
216 @ref LL_TIM_SetPrescaler().*/
217
218 uint32_t CounterMode; /*!< Specifies the counter mode.
219 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
220
221 This feature can be modified afterwards using unitary function
222 @ref LL_TIM_SetCounterMode().*/
223
224 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
225 Auto-Reload Register at the next update event.
226 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
227 Some timer instances may support 32 bits counters. In that case this parameter must
228 be a number between 0x0000 and 0xFFFFFFFF.
229
230 This feature can be modified afterwards using unitary function
231 @ref LL_TIM_SetAutoReload().*/
232
233 uint32_t ClockDivision; /*!< Specifies the clock division.
234 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
235
236 This feature can be modified afterwards using unitary function
237 @ref LL_TIM_SetClockDivision().*/
238
239 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
240 reaches zero, an update event is generated and counting restarts
241 from the RCR value (N).
242 This means in PWM mode that (N+1) corresponds to:
243 - the number of PWM periods in edge-aligned mode
244 - the number of half PWM period in center-aligned mode
245 GP timers: this parameter must be a number between Min_Data = 0x00 and
246 Max_Data = 0xFF.
247 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
248 Max_Data = 0xFFFF.
249
250 This feature can be modified afterwards using unitary function
251 @ref LL_TIM_SetRepetitionCounter().*/
252 } LL_TIM_InitTypeDef;
253
254 /**
255 * @brief TIM Output Compare configuration structure definition.
256 */
257 typedef struct
258 {
259 uint32_t OCMode; /*!< Specifies the output mode.
260 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
261
262 This feature can be modified afterwards using unitary function
263 @ref LL_TIM_OC_SetMode().*/
264
265 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
266 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
267
268 This feature can be modified afterwards using unitary functions
269 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
270
271 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
272 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
273
274 This feature can be modified afterwards using unitary functions
275 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
276
277 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
278 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
279
280 This feature can be modified afterwards using unitary function
281 LL_TIM_OC_SetCompareCHx (x=1..6).*/
282
283 uint32_t OCPolarity; /*!< Specifies the output polarity.
284 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
285
286 This feature can be modified afterwards using unitary function
287 @ref LL_TIM_OC_SetPolarity().*/
288
289 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
290 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
291
292 This feature can be modified afterwards using unitary function
293 @ref LL_TIM_OC_SetPolarity().*/
294
295
296 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
297 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetIdleState().*/
301
302 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
303 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
304
305 This feature can be modified afterwards using unitary function
306 @ref LL_TIM_OC_SetIdleState().*/
307 } LL_TIM_OC_InitTypeDef;
308
309 /**
310 * @brief TIM Input Capture configuration structure definition.
311 */
312
313 typedef struct
314 {
315
316 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
317 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
318
319 This feature can be modified afterwards using unitary function
320 @ref LL_TIM_IC_SetPolarity().*/
321
322 uint32_t ICActiveInput; /*!< Specifies the input.
323 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
324
325 This feature can be modified afterwards using unitary function
326 @ref LL_TIM_IC_SetActiveInput().*/
327
328 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
329 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
330
331 This feature can be modified afterwards using unitary function
332 @ref LL_TIM_IC_SetPrescaler().*/
333
334 uint32_t ICFilter; /*!< Specifies the input capture filter.
335 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
336
337 This feature can be modified afterwards using unitary function
338 @ref LL_TIM_IC_SetFilter().*/
339 } LL_TIM_IC_InitTypeDef;
340
341
342 /**
343 * @brief TIM Encoder interface configuration structure definition.
344 */
345 typedef struct
346 {
347 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
348 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_SetEncoderMode().*/
352
353 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
354 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
355
356 This feature can be modified afterwards using unitary function
357 @ref LL_TIM_IC_SetPolarity().*/
358
359 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
360 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
361
362 This feature can be modified afterwards using unitary function
363 @ref LL_TIM_IC_SetActiveInput().*/
364
365 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
366 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
367
368 This feature can be modified afterwards using unitary function
369 @ref LL_TIM_IC_SetPrescaler().*/
370
371 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
372 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
373
374 This feature can be modified afterwards using unitary function
375 @ref LL_TIM_IC_SetFilter().*/
376
377 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
378 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
379
380 This feature can be modified afterwards using unitary function
381 @ref LL_TIM_IC_SetPolarity().*/
382
383 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
384 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
385
386 This feature can be modified afterwards using unitary function
387 @ref LL_TIM_IC_SetActiveInput().*/
388
389 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
390 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
391
392 This feature can be modified afterwards using unitary function
393 @ref LL_TIM_IC_SetPrescaler().*/
394
395 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
396 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
397
398 This feature can be modified afterwards using unitary function
399 @ref LL_TIM_IC_SetFilter().*/
400
401 } LL_TIM_ENCODER_InitTypeDef;
402
403 /**
404 * @brief TIM Hall sensor interface configuration structure definition.
405 */
406 typedef struct
407 {
408
409 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
410 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
411
412 This feature can be modified afterwards using unitary function
413 @ref LL_TIM_IC_SetPolarity().*/
414
415 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
416 Prescaler must be set to get a maximum counter period longer than the
417 time interval between 2 consecutive changes on the Hall inputs.
418 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
419
420 This feature can be modified afterwards using unitary function
421 @ref LL_TIM_IC_SetPrescaler().*/
422
423 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
424 This parameter can be a value of
425 @ref TIM_LL_EC_IC_FILTER.
426
427 This feature can be modified afterwards using unitary function
428 @ref LL_TIM_IC_SetFilter().*/
429
430 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
431 A positive pulse (TRGO event) is generated with a programmable delay every time
432 a change occurs on the Hall inputs.
433 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
434
435 This feature can be modified afterwards using unitary function
436 @ref LL_TIM_OC_SetCompareCH2().*/
437 } LL_TIM_HALLSENSOR_InitTypeDef;
438
439 /**
440 * @brief BDTR (Break and Dead Time) structure definition
441 */
442 typedef struct
443 {
444 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
445 This parameter can be a value of @ref TIM_LL_EC_OSSR
446
447 This feature can be modified afterwards using unitary function
448 @ref LL_TIM_SetOffStates()
449
450 @note This bit-field cannot be modified as long as LOCK level 2 has been
451 programmed. */
452
453 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
454 This parameter can be a value of @ref TIM_LL_EC_OSSI
455
456 This feature can be modified afterwards using unitary function
457 @ref LL_TIM_SetOffStates()
458
459 @note This bit-field cannot be modified as long as LOCK level 2 has been
460 programmed. */
461
462 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
463 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
464
465 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
466 register has been written, their content is frozen until the next reset.*/
467
468 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
469 switching-on of the outputs.
470 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
471
472 This feature can be modified afterwards using unitary function
473 @ref LL_TIM_OC_SetDeadTime()
474
475 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
476 programmed. */
477
478 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
479 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
480
481 This feature can be modified afterwards using unitary functions
482 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
483
484 @note This bit-field can not be modified as long as LOCK level 1 has been
485 programmed. */
486
487 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
488 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
489
490 This feature can be modified afterwards using unitary function
491 @ref LL_TIM_ConfigBRK()
492
493 @note This bit-field can not be modified as long as LOCK level 1 has been
494 programmed. */
495
496 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
497 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
498
499 This feature can be modified afterwards using unitary function
500 @ref LL_TIM_ConfigBRK()
501
502 @note This bit-field can not be modified as long as LOCK level 1 has been
503 programmed. */
504
505 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
506 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
507
508 This feature can be modified afterwards using unitary functions
509 @ref LL_TIM_ConfigBRK()
510
511 @note Bidirectional break input is only supported by advanced timers instances.
512
513 @note This bit-field can not be modified as long as LOCK level 1 has been
514 programmed. */
515
516 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
518
519 This feature can be modified afterwards using unitary functions
520 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
521
522 @note This bit-field can not be modified as long as LOCK level 1 has been
523 programmed. */
524
525 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
526 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
527
528 This feature can be modified afterwards using unitary function
529 @ref LL_TIM_ConfigBRK2()
530
531 @note This bit-field can not be modified as long as LOCK level 1 has been
532 programmed. */
533
534 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
535 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
536
537 This feature can be modified afterwards using unitary function
538 @ref LL_TIM_ConfigBRK2()
539
540 @note This bit-field can not be modified as long as LOCK level 1 has been
541 programmed. */
542
543 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
544 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
545
546 This feature can be modified afterwards using unitary functions
547 @ref LL_TIM_ConfigBRK2()
548
549 @note Bidirectional break input is only supported by advanced timers instances.
550
551 @note This bit-field can not be modified as long as LOCK level 1 has been
552 programmed. */
553
554 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
555 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
556
557 This feature can be modified afterwards using unitary functions
558 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
559
560 @note This bit-field can not be modified as long as LOCK level 1 has been
561 programmed. */
562 } LL_TIM_BDTR_InitTypeDef;
563
564 /**
565 * @}
566 */
567 #endif /* USE_FULL_LL_DRIVER */
568
569 /* Exported constants --------------------------------------------------------*/
570 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
571 * @{
572 */
573
574 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
575 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
576 * @{
577 */
578 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
579 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
580 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
581 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
582 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
583 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
584 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
585 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
586 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
587 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
588 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
589 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
590 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
591 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
592 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
593 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
594 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
595 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
596 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
597 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
598 /**
599 * @}
600 */
601
602 #if defined(USE_FULL_LL_DRIVER)
603 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
604 * @{
605 */
606 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
607 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
608 /**
609 * @}
610 */
611
612 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
613 * @{
614 */
615 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
616 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
617 /**
618 * @}
619 */
620
621 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
622 * @{
623 */
624 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
625 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
626 /**
627 * @}
628 */
629 #endif /* USE_FULL_LL_DRIVER */
630
631 /** @defgroup TIM_LL_EC_IT IT Defines
632 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
633 * @{
634 */
635 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
636 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
637 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
638 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
639 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
640 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
641 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
642 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
643 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
644 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
645 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
646 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
647 /**
648 * @}
649 */
650
651 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
652 * @{
653 */
654 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
655 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
656 /**
657 * @}
658 */
659
660 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
661 * @{
662 */
663 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
664 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
665 /**
666 * @}
667 */
668
669 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
670 * @{
671 */
672 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
673 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
674 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
675 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
676 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
677 /**
678 * @}
679 */
680
681 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
682 * @{
683 */
684 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
685 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
686 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
692 * @{
693 */
694 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
695 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
696 /**
697 * @}
698 */
699
700 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
701 * @{
702 */
703 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
704 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
705 /**
706 * @}
707 */
708
709 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
710 * @{
711 */
712 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
713 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
714 /**
715 * @}
716 */
717
718 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
719 * @{
720 */
721 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
722 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
723 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
724 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
725 /**
726 * @}
727 */
728
729 /** @defgroup TIM_LL_EC_CHANNEL Channel
730 * @{
731 */
732 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
733 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
734 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
735 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
736 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
737 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
738 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
739 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
740 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
741 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
742 /**
743 * @}
744 */
745
746 #if defined(USE_FULL_LL_DRIVER)
747 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
748 * @{
749 */
750 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
751 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
752 /**
753 * @}
754 */
755 #endif /* USE_FULL_LL_DRIVER */
756
757 /** Legacy definitions for compatibility purpose
758 @cond 0
759 */
760 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
761 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
762 /**
763 @endcond
764 */
765
766 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
767 * @{
768 */
769 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
770 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
771 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
772 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
773 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
774 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
775 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
776 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
777 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
778 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
779 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
780 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
781 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
782 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
783 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
784 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
785 /**
786 * @}
787 */
788
789 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
790 * @{
791 */
792 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
793 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
794 /**
795 * @}
796 */
797
798 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
799 * @{
800 */
801 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
802 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
803 /**
804 * @}
805 */
806
807 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
808 * @{
809 */
810 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
811 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
812 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
813 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
814 /**
815 * @}
816 */
817
818 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
819 * @{
820 */
821 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
822 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
823 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
824 /**
825 * @}
826 */
827
828 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
829 * @{
830 */
831 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
832 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
833 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
834 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
835 /**
836 * @}
837 */
838
839 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
840 * @{
841 */
842 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
843 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
844 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
845 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
846 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
847 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
848 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
849 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
850 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
851 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
852 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
853 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
854 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
855 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
856 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
857 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
858 /**
859 * @}
860 */
861
862 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
863 * @{
864 */
865 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
866 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
867 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
868 /**
869 * @}
870 */
871
872 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
873 * @{
874 */
875 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
876 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
877 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
878 /**
879 * @}
880 */
881
882 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
883 * @{
884 */
885 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
886 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
887 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
888 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
889 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
890 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
891 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
892 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
893 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
894 /**
895 * @}
896 */
897
898 /** @defgroup TIM_LL_EC_TRGO Trigger Output
899 * @{
900 */
901 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
902 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
903 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
904 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
905 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
906 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
907 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
908 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
909 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
910 /**
911 * @}
912 */
913
914 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
915 * @{
916 */
917 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
918 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
919 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
920 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
921 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
922 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
923 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
924 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
926 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
927 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
928 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
929 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
930 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
931 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
932 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
933 /**
934 * @}
935 */
936
937 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
938 * @{
939 */
940 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
941 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
942 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
943 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
944 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
945 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
946 the counter are controlled. */
947 /**
948 * @}
949 */
950
951 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
952 * @{
953 */
954 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
955 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
956 /**
957 * @}
958 */
959
960 /** @defgroup TIM_LL_EC_TS Trigger Selection
961 * @{
962 */
963 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
964 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
965 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
966 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
967 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
968 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
969 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
970 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
971 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
972 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
973 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
974 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
975 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
976 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
977 #define LL_TIM_TS_ITR14 (TIM_SMCR_TS_1 | TIM_SMCR_TS_4) /*!< Internal Trigger 14 (ITR14) is used as trigger input */
978 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
979 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
980 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
981 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
982 /**
983 * @}
984 */
985
986 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
987 * @{
988 */
989 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
990 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
991 /**
992 * @}
993 */
994
995 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
996 * @{
997 */
998 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
999 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
1000 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1001 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1002 /**
1003 * @}
1004 */
1005
1006 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1007 * @{
1008 */
1009 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1010 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1011 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1012 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1013 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1014 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1015 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1016 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1017 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1018 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1019 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1020 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1021 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1022 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1023 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1024 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1030 * @{
1031 */
1032 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000UL /*!< TIM1_ETR is connected to I/O */
1033 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
1034 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */
1035 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
1036 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD1 */
1037 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC2 AWD2 */
1038 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 TIM_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC2 AWD3 */
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1044 * @{
1045 */
1046 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000UL /*!< TIM2_ETR is connected to I/O */
1047 #define LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC TIM_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to DCMIPP HSYNC */
1048 #define LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC TIM_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to LTDC HSYNC */
1049 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
1050 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */
1051 #define LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to GFXTIM TE */
1052 #define LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DCMIPP VSYNC */
1053 #define LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to LTDC VSYNC */
1054 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM3 ETR */
1055 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */
1056 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to TIM5 ETR */
1057 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to ETH PPS */
1058 /**
1059 * @}
1060 */
1061
1062 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1063 * @{
1064 */
1065 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000UL /*!< TIM3_ETR is connected to I/O */
1066 #define LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC TIM_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to DCMIPP HSYNC */
1067 #define LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC TIM_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to LTDC HSYNC */
1068 #define LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to GFXTIM TE */
1069 #define LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to DCMIPP VSYNC */
1070 #define LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to LTDC VSYNC */
1071 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM2 ETR */
1072 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */
1073 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to TIM5 ETR */
1074 #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ETH PPS */
1075 /**
1076 * @}
1077 */
1078
1079 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1080 * @{
1081 */
1082 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000UL /*!< TIM4_ETR is connected to I/O */
1083 #define LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC TIM_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to DCMIPP HSYNC */
1084 #define LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC TIM_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to LTDC HSYNC */
1085 #define LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to GFXTIM TE */
1086 #define LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to DCMIPP VSYNC */
1087 #define LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to LTDC VSYNC */
1088 #define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM2 ETR */
1089 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to TIM3 ETR */
1090 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM4_ETR is connected to TIM5 ETR */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1096 * @{
1097 */
1098 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000UL /*!< TIM5_ETR is connected to I/O */
1099 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */
1100 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */
1101 #define LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to DCMIPP HSYNC */
1102 #define LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC TIM_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to LTDC HSYNC */
1103 #define LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to GFXTIM TE */
1104 #define LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to DCMIPP VSYNC */
1105 #define LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to LTDC VSYNC */
1106 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM2 ETR */
1107 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM3 ETR */
1108 #define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM5 ETR */
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1114 * @{
1115 */
1116 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1117 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1118 /**
1119 * @}
1120 */
1121
1122 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1123 * @{
1124 */
1125 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1126 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1127 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1128 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1129 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1130 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1131 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1132 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1133 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1134 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1135 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1136 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1137 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1138 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1139 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1140 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1141 /**
1142 * @}
1143 */
1144
1145 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1146 * @{
1147 */
1148 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1149 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1155 * @{
1156 */
1157 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1158 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1159 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1160 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1161 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1162 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1163 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1164 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1165 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1166 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1167 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1168 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1169 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1170 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1171 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1172 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1173 /**
1174 * @}
1175 */
1176
1177 /** @defgroup TIM_LL_EC_OSSI OSSI
1178 * @{
1179 */
1180 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1181 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1182 /**
1183 * @}
1184 */
1185
1186 /** @defgroup TIM_LL_EC_OSSR OSSR
1187 * @{
1188 */
1189 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1190 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1196 * @{
1197 */
1198 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1199 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1205 * @{
1206 */
1207 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1208 /**
1209 * @}
1210 */
1211
1212 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1213 * @{
1214 */
1215 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1216 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1217 /**
1218 * @}
1219 */
1220
1221 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1222 * @{
1223 */
1224 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1225 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1226 /**
1227 * @}
1228 */
1229
1230 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1231 * @{
1232 */
1233 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1234 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1235 /**
1236 * @}
1237 */
1238
1239 /** Legacy definitions for compatibility purpose
1240 @cond 0
1241 */
1242 #define LL_TIM_ReArmBRK(_PARAM_)
1243 #define LL_TIM_ReArmBRK2(_PARAM_)
1244 /**
1245 @endcond
1246 */
1247
1248 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1249 * @{
1250 */
1251 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1252 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1253 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1254 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1255 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1256 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1257 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1258 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1259 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1260 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1261 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1262 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1263 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1264 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1265 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1266 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1267 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1268 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1269 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1270 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1271 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1272 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1273 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1274 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1275 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1276 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1277 /**
1278 * @}
1279 */
1280
1281 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1282 * @{
1283 */
1284 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1285 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1286 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1287 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1288 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1289 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1290 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1291 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1292 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1293 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1294 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1295 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1296 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1297 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1298 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1299 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1300 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1301 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1302 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1303 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1304 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1305 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1306 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1307 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1308 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1309 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1310 /**
1311 * @}
1312 */
1313
1314 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1315 * @{
1316 */
1317 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1318 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1319 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1320 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1321 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1322 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1323 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1329 * @{
1330 */
1331 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1332 #define LL_TIM_TIM2_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */
1333 /**
1334 * @}
1335 */
1336
1337 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1338 * @{
1339 */
1340 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
1341 #define LL_TIM_TIM3_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to ETH PPS */
1342 /**
1343 * @}
1344 */
1345
1346 /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 External Input Ch1 Remap
1347 * @{
1348 */
1349 #define LL_TIM_TIM9_TI1_RMP_GPIO 0x00000000UL /*!< TIM9_TI1 is connected to GPIO */
1350 #define LL_TIM_TIM9_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_2 /*!< TIM9_TI1 is connected to MCO1 */
1351 #define LL_TIM_TIM9_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM9_TI1 is connected to MCO2 */
1352 /**
1353 * @}
1354 */
1355
1356 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 External Input Ch1 Remap
1357 * @{
1358 */
1359 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */
1360 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */
1361 #define LL_TIM_TIM12_TI1_RMP_HSI_1024 TIM_TISEL_TI1SEL_1 /*!< TIM12_TI1 is connected to HSI/1024 */
1362 #define LL_TIM_TIM12_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI/128*/
1363 #define LL_TIM_TIM12_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to MCO1 */
1364 #define LL_TIM_TIM12_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to MCO2 */
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1370 * @{
1371 */
1372 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1373 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 GPIO */
1374 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 GPIO */
1375 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 CH1 GPIO */
1376 #define LL_TIM_TIM15_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to MCO1 */
1377 #define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to MCO2 */
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
1383 * @{
1384 */
1385 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */
1386 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 CH2 GPIO */
1387 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 CH2 GPIO */
1388 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 CH2 GPIO */
1389 /**
1390 * @}
1391 */
1392
1393 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1394 * @{
1395 */
1396 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */
1397 #define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC Wakeup */
1398 /**
1399 * @}
1400 */
1401
1402 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1403 * @{
1404 */
1405 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
1406 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17_TI1 is connected to SPDIFRX FS */
1407 /**
1408 * @}
1409 */
1410
1411 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1412 * @{
1413 */
1414 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1415 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1416 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1417 /**
1418 * @}
1419 */
1420
1421 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1422 * @{
1423 */
1424 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1425 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1426 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1427 /**
1428 * @}
1429 */
1430
1431 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1432 * @{
1433 */
1434 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1435 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1436 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1437 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1438 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1439 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1440 /**
1441 * @}
1442 */
1443
1444 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1445 * @{
1446 */
1447 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1448 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1449 /**
1450 * @}
1451 */
1452 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1453 * @{
1454 */
1455 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1456 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1457 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1458 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1459 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1460 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1461 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1462 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1463 /**
1464 * @}
1465 */
1466
1467 /** Legacy definitions for compatibility purpose
1468 @cond 0
1469 */
1470 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1471 /**
1472 @endcond
1473 */
1474
1475 /**
1476 * @}
1477 */
1478
1479 /* Exported macro ------------------------------------------------------------*/
1480 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1481 * @{
1482 */
1483
1484 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1485 * @{
1486 */
1487 /**
1488 * @brief Write a value in TIM register.
1489 * @param __INSTANCE__ TIM Instance
1490 * @param __REG__ Register to be written
1491 * @param __VALUE__ Value to be written in the register
1492 * @retval None
1493 */
1494 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1495
1496 /**
1497 * @brief Read a value in TIM register.
1498 * @param __INSTANCE__ TIM Instance
1499 * @param __REG__ Register to be read
1500 * @retval Register value
1501 */
1502 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1503 /**
1504 * @}
1505 */
1506
1507 /**
1508 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1509 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1510 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1511 * to TIMx_CNT register bit 31)
1512 * @param __CNT__ Counter value
1513 * @retval UIF status bit
1514 */
1515 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1516 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1517
1518 /**
1519 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1520 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1521 * @param __TIMCLK__ timer input clock frequency (in Hz)
1522 * @param __CKD__ This parameter can be one of the following values:
1523 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1524 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1525 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1526 * @param __DT__ deadtime duration (in ns)
1527 * @retval DTG[0:7]
1528 */
1529 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1530 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1531 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1532 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1533 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1534 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1535 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1536 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1537 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1538 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1539 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1540 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1541 0U)
1542
1543 /**
1544 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1545 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1546 * @param __TIMCLK__ timer input clock frequency (in Hz)
1547 * @param __CNTCLK__ counter clock frequency (in Hz)
1548 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1549 */
1550 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1551 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1552
1553 /**
1554 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1555 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1556 * @param __TIMCLK__ timer input clock frequency (in Hz)
1557 * @param __PSC__ prescaler
1558 * @param __FREQ__ output signal frequency (in Hz)
1559 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1560 */
1561 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1562 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1563
1564 /**
1565 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1566 * output signal frequency.
1567 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1568 * @param __TIMCLK__ timer input clock frequency (in Hz)
1569 * @param __PSC__ prescaler
1570 * @param __FREQ__ output signal frequency (in Hz)
1571 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1572 */
1573 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1574 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1575 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1576
1577 /**
1578 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1579 * active/inactive delay.
1580 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1581 * @param __TIMCLK__ timer input clock frequency (in Hz)
1582 * @param __PSC__ prescaler
1583 * @param __DELAY__ timer output compare active/inactive delay (in us)
1584 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1585 */
1586 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1587 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1588 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1589
1590 /**
1591 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1592 * output compare active/inactive delay.
1593 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1594 * @param __TIMCLK__ timer input clock frequency (in Hz)
1595 * @param __PSC__ prescaler
1596 * @param __DELAY__ timer output compare active/inactive delay (in us)
1597 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1598 */
1599 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1600 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1601 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1602
1603 /**
1604 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1605 * (when the timer operates in one pulse mode).
1606 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1607 * @param __TIMCLK__ timer input clock frequency (in Hz)
1608 * @param __PSC__ prescaler
1609 * @param __DELAY__ timer output compare active/inactive delay (in us)
1610 * @param __PULSE__ pulse duration (in us)
1611 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1612 */
1613 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1614 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1615 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1616
1617 /**
1618 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1619 * pulse duration (when the timer operates in one pulse mode).
1620 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1621 * @param __TIMCLK__ timer input clock frequency (in Hz)
1622 * @param __PSC__ prescaler
1623 * @param __DELAY__ timer output compare active/inactive delay (in us)
1624 * @param __PULSE__ pulse duration (in us)
1625 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1626 */
1627 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1628 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1629 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1630
1631 /**
1632 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1633 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1634 * @param __ICPSC__ This parameter can be one of the following values:
1635 * @arg @ref LL_TIM_ICPSC_DIV1
1636 * @arg @ref LL_TIM_ICPSC_DIV2
1637 * @arg @ref LL_TIM_ICPSC_DIV4
1638 * @arg @ref LL_TIM_ICPSC_DIV8
1639 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1640 */
1641 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1642 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1643
1644
1645 /**
1646 * @}
1647 */
1648
1649 /* Exported functions --------------------------------------------------------*/
1650 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1651 * @{
1652 */
1653
1654 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1655 * @{
1656 */
1657 /**
1658 * @brief Enable timer counter.
1659 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1660 * @param TIMx Timer instance
1661 * @retval None
1662 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1663 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1664 {
1665 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1666 }
1667
1668 /**
1669 * @brief Disable timer counter.
1670 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1671 * @param TIMx Timer instance
1672 * @retval None
1673 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1674 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1675 {
1676 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1677 }
1678
1679 /**
1680 * @brief Indicates whether the timer counter is enabled.
1681 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1682 * @param TIMx Timer instance
1683 * @retval State of bit (1 or 0).
1684 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1685 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1686 {
1687 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1688 }
1689
1690 /**
1691 * @brief Enable update event generation.
1692 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1693 * @param TIMx Timer instance
1694 * @retval None
1695 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1696 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1697 {
1698 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1699 }
1700
1701 /**
1702 * @brief Disable update event generation.
1703 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1704 * @param TIMx Timer instance
1705 * @retval None
1706 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1707 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1708 {
1709 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1710 }
1711
1712 /**
1713 * @brief Indicates whether update event generation is enabled.
1714 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1715 * @param TIMx Timer instance
1716 * @retval Inverted state of bit (0 or 1).
1717 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1718 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1719 {
1720 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1721 }
1722
1723 /**
1724 * @brief Set update event source
1725 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1726 * generate an update interrupt or DMA request if enabled:
1727 * - Counter overflow/underflow
1728 * - Setting the UG bit
1729 * - Update generation through the slave mode controller
1730 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1731 * overflow/underflow generates an update interrupt or DMA request if enabled.
1732 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1733 * @param TIMx Timer instance
1734 * @param UpdateSource This parameter can be one of the following values:
1735 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1736 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1737 * @retval None
1738 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1739 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1740 {
1741 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1742 }
1743
1744 /**
1745 * @brief Get actual event update source
1746 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1747 * @param TIMx Timer instance
1748 * @retval Returned value can be one of the following values:
1749 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1750 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1751 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1752 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1753 {
1754 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1755 }
1756
1757 /**
1758 * @brief Set one pulse mode (one shot v.s. repetitive).
1759 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1760 * @param TIMx Timer instance
1761 * @param OnePulseMode This parameter can be one of the following values:
1762 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1763 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1764 * @retval None
1765 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1766 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1767 {
1768 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1769 }
1770
1771 /**
1772 * @brief Get actual one pulse mode.
1773 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1774 * @param TIMx Timer instance
1775 * @retval Returned value can be one of the following values:
1776 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1777 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1778 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1779 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1780 {
1781 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1782 }
1783
1784 /**
1785 * @brief Set the timer counter counting mode.
1786 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1787 * check whether or not the counter mode selection feature is supported
1788 * by a timer instance.
1789 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1790 * requires a timer reset to avoid unexpected direction
1791 * due to DIR bit readonly in center aligned mode.
1792 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1793 * CR1 CMS LL_TIM_SetCounterMode
1794 * @param TIMx Timer instance
1795 * @param CounterMode This parameter can be one of the following values:
1796 * @arg @ref LL_TIM_COUNTERMODE_UP
1797 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1798 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1799 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1800 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1801 * @retval None
1802 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1803 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1804 {
1805 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1806 }
1807
1808 /**
1809 * @brief Get actual counter mode.
1810 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1811 * check whether or not the counter mode selection feature is supported
1812 * by a timer instance.
1813 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1814 * CR1 CMS LL_TIM_GetCounterMode
1815 * @param TIMx Timer instance
1816 * @retval Returned value can be one of the following values:
1817 * @arg @ref LL_TIM_COUNTERMODE_UP
1818 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1819 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1820 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1821 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1822 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1823 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1824 {
1825 uint32_t counter_mode;
1826
1827 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1828
1829 if (counter_mode == 0U)
1830 {
1831 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1832 }
1833
1834 return counter_mode;
1835 }
1836
1837 /**
1838 * @brief Enable auto-reload (ARR) preload.
1839 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1840 * @param TIMx Timer instance
1841 * @retval None
1842 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1843 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1844 {
1845 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1846 }
1847
1848 /**
1849 * @brief Disable auto-reload (ARR) preload.
1850 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1851 * @param TIMx Timer instance
1852 * @retval None
1853 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1854 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1855 {
1856 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1857 }
1858
1859 /**
1860 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1861 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1862 * @param TIMx Timer instance
1863 * @retval State of bit (1 or 0).
1864 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1865 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1866 {
1867 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1868 }
1869
1870 /**
1871 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1872 * (when supported) and the digital filters.
1873 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1874 * whether or not the clock division feature is supported by the timer
1875 * instance.
1876 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1877 * @param TIMx Timer instance
1878 * @param ClockDivision This parameter can be one of the following values:
1879 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1880 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1881 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1882 * @retval None
1883 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1884 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1885 {
1886 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1887 }
1888
1889 /**
1890 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1891 * generators (when supported) and the digital filters.
1892 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1893 * whether or not the clock division feature is supported by the timer
1894 * instance.
1895 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1896 * @param TIMx Timer instance
1897 * @retval Returned value can be one of the following values:
1898 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1899 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1900 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1901 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1902 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1903 {
1904 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1905 }
1906
1907 /**
1908 * @brief Set the counter value.
1909 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1910 * whether or not a timer instance supports a 32 bits counter.
1911 * @note If dithering is activated, pay attention to the Counter value interpretation
1912 * @rmtoll CNT CNT LL_TIM_SetCounter
1913 * @param TIMx Timer instance
1914 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1915 * @retval None
1916 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1917 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1918 {
1919 WRITE_REG(TIMx->CNT, Counter);
1920 }
1921
1922 /**
1923 * @brief Get the counter value.
1924 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1925 * whether or not a timer instance supports a 32 bits counter.
1926 * @note If dithering is activated, pay attention to the Counter value interpretation
1927 * @rmtoll CNT CNT LL_TIM_GetCounter
1928 * @param TIMx Timer instance
1929 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1930 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)1931 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
1932 {
1933 return (uint32_t)(READ_REG(TIMx->CNT));
1934 }
1935
1936 /**
1937 * @brief Get the current direction of the counter
1938 * @rmtoll CR1 DIR LL_TIM_GetDirection
1939 * @param TIMx Timer instance
1940 * @retval Returned value can be one of the following values:
1941 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1942 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1943 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)1944 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
1945 {
1946 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1947 }
1948
1949 /**
1950 * @brief Set the prescaler value.
1951 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1952 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1953 * prescaler ratio is taken into account at the next update event.
1954 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1955 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1956 * @param TIMx Timer instance
1957 * @param Prescaler between Min_Data=0 and Max_Data=65535
1958 * @retval None
1959 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1960 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1961 {
1962 WRITE_REG(TIMx->PSC, Prescaler);
1963 }
1964
1965 /**
1966 * @brief Get the prescaler value.
1967 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1968 * @param TIMx Timer instance
1969 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1970 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)1971 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
1972 {
1973 return (uint32_t)(READ_REG(TIMx->PSC));
1974 }
1975
1976 /**
1977 * @brief Set the auto-reload value.
1978 * @note The counter is blocked while the auto-reload value is null.
1979 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1980 * whether or not a timer instance supports a 32 bits counter.
1981 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1982 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
1983 * parameter.
1984 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1985 * @param TIMx Timer instance
1986 * @param AutoReload between Min_Data=0 and Max_Data=65535
1987 * @retval None
1988 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1989 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1990 {
1991 WRITE_REG(TIMx->ARR, AutoReload);
1992 }
1993
1994 /**
1995 * @brief Get the auto-reload value.
1996 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1997 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1998 * whether or not a timer instance supports a 32 bits counter.
1999 * @note If dithering is activated, pay attention to the returned value interpretation
2000 * @param TIMx Timer instance
2001 * @retval Auto-reload value
2002 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2003 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2004 {
2005 return (uint32_t)(READ_REG(TIMx->ARR));
2006 }
2007
2008 /**
2009 * @brief Set the repetition counter value.
2010 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2011 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2012 * whether or not a timer instance supports a repetition counter.
2013 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2014 * @param TIMx Timer instance
2015 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2016 * @retval None
2017 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2018 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2019 {
2020 WRITE_REG(TIMx->RCR, RepetitionCounter);
2021 }
2022
2023 /**
2024 * @brief Get the repetition counter value.
2025 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2026 * whether or not a timer instance supports a repetition counter.
2027 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2028 * @param TIMx Timer instance
2029 * @retval Repetition counter value
2030 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2031 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2032 {
2033 return (uint32_t)(READ_REG(TIMx->RCR));
2034 }
2035
2036 /**
2037 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2038 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2039 * in an atomic way.
2040 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2041 * @param TIMx Timer instance
2042 * @retval None
2043 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2044 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2045 {
2046 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2047 }
2048
2049 /**
2050 * @brief Disable update interrupt flag (UIF) remapping.
2051 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2052 * @param TIMx Timer instance
2053 * @retval None
2054 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2055 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2056 {
2057 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2058 }
2059
2060 /**
2061 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2062 * @param Counter Counter value
2063 * @retval State of bit (1 or 0).
2064 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2065 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2066 {
2067 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2068 }
2069
2070 /**
2071 * @brief Enable dithering.
2072 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2073 * a timer instance provides dithering.
2074 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2075 * @param TIMx Timer instance
2076 * @retval None
2077 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2078 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2079 {
2080 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2081 }
2082
2083 /**
2084 * @brief Disable dithering.
2085 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2086 * a timer instance provides dithering.
2087 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2088 * @param TIMx Timer instance
2089 * @retval None
2090 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2091 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2092 {
2093 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2094 }
2095
2096 /**
2097 * @brief Indicates whether dithering is activated.
2098 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2099 * a timer instance provides dithering.
2100 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2101 * @param TIMx Timer instance
2102 * @retval State of bit (1 or 0).
2103 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2104 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2105 {
2106 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2107 }
2108
2109 /**
2110 * @}
2111 */
2112
2113 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2114 * @{
2115 */
2116 /**
2117 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2118 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2119 * they are updated only when a commutation event (COM) occurs.
2120 * @note Only on channels that have a complementary output.
2121 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2122 * whether or not a timer instance is able to generate a commutation event.
2123 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2124 * @param TIMx Timer instance
2125 * @retval None
2126 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2127 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2128 {
2129 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2130 }
2131
2132 /**
2133 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2134 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2135 * whether or not a timer instance is able to generate a commutation event.
2136 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2137 * @param TIMx Timer instance
2138 * @retval None
2139 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2140 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2141 {
2142 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2143 }
2144
2145 /**
2146 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2147 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2148 * @param TIMx Timer instance
2149 * @retval State of bit (1 or 0).
2150 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2151 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2152 {
2153 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2154 }
2155
2156 /**
2157 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2158 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2159 * whether or not a timer instance is able to generate a commutation event.
2160 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2161 * @param TIMx Timer instance
2162 * @param CCUpdateSource This parameter can be one of the following values:
2163 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2164 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2165 * @retval None
2166 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2167 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2168 {
2169 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2170 }
2171
2172 /**
2173 * @brief Set the trigger of the capture/compare DMA request.
2174 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2175 * @param TIMx Timer instance
2176 * @param DMAReqTrigger This parameter can be one of the following values:
2177 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2178 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2179 * @retval None
2180 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2181 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2182 {
2183 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2184 }
2185
2186 /**
2187 * @brief Get actual trigger of the capture/compare DMA request.
2188 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2189 * @param TIMx Timer instance
2190 * @retval Returned value can be one of the following values:
2191 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2192 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2193 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2194 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2195 {
2196 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2197 }
2198
2199 /**
2200 * @brief Set the lock level to freeze the
2201 * configuration of several capture/compare parameters.
2202 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2203 * the lock mechanism is supported by a timer instance.
2204 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2205 * @param TIMx Timer instance
2206 * @param LockLevel This parameter can be one of the following values:
2207 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2208 * @arg @ref LL_TIM_LOCKLEVEL_1
2209 * @arg @ref LL_TIM_LOCKLEVEL_2
2210 * @arg @ref LL_TIM_LOCKLEVEL_3
2211 * @retval None
2212 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2213 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2214 {
2215 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2216 }
2217
2218 /**
2219 * @brief Enable capture/compare channels.
2220 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2221 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2222 * CCER CC2E LL_TIM_CC_EnableChannel\n
2223 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2224 * CCER CC3E LL_TIM_CC_EnableChannel\n
2225 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2226 * CCER CC4E LL_TIM_CC_EnableChannel\n
2227 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2228 * CCER CC5E LL_TIM_CC_EnableChannel\n
2229 * CCER CC6E LL_TIM_CC_EnableChannel
2230 * @param TIMx Timer instance
2231 * @param Channels This parameter can be a combination of the following values:
2232 * @arg @ref LL_TIM_CHANNEL_CH1
2233 * @arg @ref LL_TIM_CHANNEL_CH1N
2234 * @arg @ref LL_TIM_CHANNEL_CH2
2235 * @arg @ref LL_TIM_CHANNEL_CH2N
2236 * @arg @ref LL_TIM_CHANNEL_CH3
2237 * @arg @ref LL_TIM_CHANNEL_CH3N
2238 * @arg @ref LL_TIM_CHANNEL_CH4
2239 * @arg @ref LL_TIM_CHANNEL_CH4N
2240 * @arg @ref LL_TIM_CHANNEL_CH5
2241 * @arg @ref LL_TIM_CHANNEL_CH6
2242 * @retval None
2243 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2244 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2245 {
2246 SET_BIT(TIMx->CCER, Channels);
2247 }
2248
2249 /**
2250 * @brief Disable capture/compare channels.
2251 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2252 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2253 * CCER CC2E LL_TIM_CC_DisableChannel\n
2254 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2255 * CCER CC3E LL_TIM_CC_DisableChannel\n
2256 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2257 * CCER CC4E LL_TIM_CC_DisableChannel\n
2258 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2259 * CCER CC5E LL_TIM_CC_DisableChannel\n
2260 * CCER CC6E LL_TIM_CC_DisableChannel
2261 * @param TIMx Timer instance
2262 * @param Channels This parameter can be a combination of the following values:
2263 * @arg @ref LL_TIM_CHANNEL_CH1
2264 * @arg @ref LL_TIM_CHANNEL_CH1N
2265 * @arg @ref LL_TIM_CHANNEL_CH2
2266 * @arg @ref LL_TIM_CHANNEL_CH2N
2267 * @arg @ref LL_TIM_CHANNEL_CH3
2268 * @arg @ref LL_TIM_CHANNEL_CH3N
2269 * @arg @ref LL_TIM_CHANNEL_CH4
2270 * @arg @ref LL_TIM_CHANNEL_CH4N
2271 * @arg @ref LL_TIM_CHANNEL_CH5
2272 * @arg @ref LL_TIM_CHANNEL_CH6
2273 * @retval None
2274 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2275 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2276 {
2277 CLEAR_BIT(TIMx->CCER, Channels);
2278 }
2279
2280 /**
2281 * @brief Indicate whether channel(s) is(are) enabled.
2282 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2283 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2284 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2285 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2286 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2287 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2288 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2289 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2290 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2291 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2292 * @param TIMx Timer instance
2293 * @param Channels This parameter can be a combination of the following values:
2294 * @arg @ref LL_TIM_CHANNEL_CH1
2295 * @arg @ref LL_TIM_CHANNEL_CH1N
2296 * @arg @ref LL_TIM_CHANNEL_CH2
2297 * @arg @ref LL_TIM_CHANNEL_CH2N
2298 * @arg @ref LL_TIM_CHANNEL_CH3
2299 * @arg @ref LL_TIM_CHANNEL_CH3N
2300 * @arg @ref LL_TIM_CHANNEL_CH4
2301 * @arg @ref LL_TIM_CHANNEL_CH4N
2302 * @arg @ref LL_TIM_CHANNEL_CH5
2303 * @arg @ref LL_TIM_CHANNEL_CH6
2304 * @retval State of bit (1 or 0).
2305 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2306 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2307 {
2308 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2309 }
2310
2311 /**
2312 * @}
2313 */
2314
2315 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2316 * @{
2317 */
2318 /**
2319 * @brief Configure an output channel.
2320 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2321 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2322 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2323 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2324 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2325 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2326 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2327 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2328 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2329 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2330 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2331 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2332 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2333 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2334 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2335 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2336 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2337 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2338 * @param TIMx Timer instance
2339 * @param Channel This parameter can be one of the following values:
2340 * @arg @ref LL_TIM_CHANNEL_CH1
2341 * @arg @ref LL_TIM_CHANNEL_CH2
2342 * @arg @ref LL_TIM_CHANNEL_CH3
2343 * @arg @ref LL_TIM_CHANNEL_CH4
2344 * @arg @ref LL_TIM_CHANNEL_CH5
2345 * @arg @ref LL_TIM_CHANNEL_CH6
2346 * @param Configuration This parameter must be a combination of all the following values:
2347 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2348 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2349 * @retval None
2350 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2351 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2352 {
2353 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2354 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2355 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2356 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2357 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2358 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2359 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2360 }
2361
2362 /**
2363 * @brief Define the behavior of the output reference signal OCxREF from which
2364 * OCx and OCxN (when relevant) are derived.
2365 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2366 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2367 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2368 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2369 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2370 * CCMR3 OC6M LL_TIM_OC_SetMode
2371 * @param TIMx Timer instance
2372 * @param Channel This parameter can be one of the following values:
2373 * @arg @ref LL_TIM_CHANNEL_CH1
2374 * @arg @ref LL_TIM_CHANNEL_CH2
2375 * @arg @ref LL_TIM_CHANNEL_CH3
2376 * @arg @ref LL_TIM_CHANNEL_CH4
2377 * @arg @ref LL_TIM_CHANNEL_CH5
2378 * @arg @ref LL_TIM_CHANNEL_CH6
2379 * @param Mode This parameter can be one of the following values:
2380 * @arg @ref LL_TIM_OCMODE_FROZEN
2381 * @arg @ref LL_TIM_OCMODE_ACTIVE
2382 * @arg @ref LL_TIM_OCMODE_INACTIVE
2383 * @arg @ref LL_TIM_OCMODE_TOGGLE
2384 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2385 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2386 * @arg @ref LL_TIM_OCMODE_PWM1
2387 * @arg @ref LL_TIM_OCMODE_PWM2
2388 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2389 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2390 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2391 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2392 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2393 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2394 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2395 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2396 * @retval None
2397 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2398 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2399 {
2400 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2401 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2402 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2403 }
2404
2405 /**
2406 * @brief Get the output compare mode of an output channel.
2407 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2408 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2409 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2410 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2411 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2412 * CCMR3 OC6M LL_TIM_OC_GetMode
2413 * @param TIMx Timer instance
2414 * @param Channel This parameter can be one of the following values:
2415 * @arg @ref LL_TIM_CHANNEL_CH1
2416 * @arg @ref LL_TIM_CHANNEL_CH2
2417 * @arg @ref LL_TIM_CHANNEL_CH3
2418 * @arg @ref LL_TIM_CHANNEL_CH4
2419 * @arg @ref LL_TIM_CHANNEL_CH5
2420 * @arg @ref LL_TIM_CHANNEL_CH6
2421 * @retval Returned value can be one of the following values:
2422 * @arg @ref LL_TIM_OCMODE_FROZEN
2423 * @arg @ref LL_TIM_OCMODE_ACTIVE
2424 * @arg @ref LL_TIM_OCMODE_INACTIVE
2425 * @arg @ref LL_TIM_OCMODE_TOGGLE
2426 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2427 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2428 * @arg @ref LL_TIM_OCMODE_PWM1
2429 * @arg @ref LL_TIM_OCMODE_PWM2
2430 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2431 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2432 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2433 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2434 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2435 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2436 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2437 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2438 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2439 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2440 {
2441 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2442 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2443 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2444 }
2445
2446 /**
2447 * @brief Set the polarity of an output channel.
2448 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2449 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2450 * CCER CC2P LL_TIM_OC_SetPolarity\n
2451 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2452 * CCER CC3P LL_TIM_OC_SetPolarity\n
2453 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2454 * CCER CC4P LL_TIM_OC_SetPolarity\n
2455 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2456 * CCER CC5P LL_TIM_OC_SetPolarity\n
2457 * CCER CC6P LL_TIM_OC_SetPolarity
2458 * @param TIMx Timer instance
2459 * @param Channel This parameter can be one of the following values:
2460 * @arg @ref LL_TIM_CHANNEL_CH1
2461 * @arg @ref LL_TIM_CHANNEL_CH1N
2462 * @arg @ref LL_TIM_CHANNEL_CH2
2463 * @arg @ref LL_TIM_CHANNEL_CH2N
2464 * @arg @ref LL_TIM_CHANNEL_CH3
2465 * @arg @ref LL_TIM_CHANNEL_CH3N
2466 * @arg @ref LL_TIM_CHANNEL_CH4
2467 * @arg @ref LL_TIM_CHANNEL_CH4N
2468 * @arg @ref LL_TIM_CHANNEL_CH5
2469 * @arg @ref LL_TIM_CHANNEL_CH6
2470 * @param Polarity This parameter can be one of the following values:
2471 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2472 * @arg @ref LL_TIM_OCPOLARITY_LOW
2473 * @retval None
2474 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2475 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2476 {
2477 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2478 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2479 }
2480
2481 /**
2482 * @brief Get the polarity of an output channel.
2483 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2484 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2485 * CCER CC2P LL_TIM_OC_GetPolarity\n
2486 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2487 * CCER CC3P LL_TIM_OC_GetPolarity\n
2488 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2489 * CCER CC4P LL_TIM_OC_GetPolarity\n
2490 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2491 * CCER CC5P LL_TIM_OC_GetPolarity\n
2492 * CCER CC6P LL_TIM_OC_GetPolarity
2493 * @param TIMx Timer instance
2494 * @param Channel This parameter can be one of the following values:
2495 * @arg @ref LL_TIM_CHANNEL_CH1
2496 * @arg @ref LL_TIM_CHANNEL_CH1N
2497 * @arg @ref LL_TIM_CHANNEL_CH2
2498 * @arg @ref LL_TIM_CHANNEL_CH2N
2499 * @arg @ref LL_TIM_CHANNEL_CH3
2500 * @arg @ref LL_TIM_CHANNEL_CH3N
2501 * @arg @ref LL_TIM_CHANNEL_CH4
2502 * @arg @ref LL_TIM_CHANNEL_CH4N
2503 * @arg @ref LL_TIM_CHANNEL_CH5
2504 * @arg @ref LL_TIM_CHANNEL_CH6
2505 * @retval Returned value can be one of the following values:
2506 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2507 * @arg @ref LL_TIM_OCPOLARITY_LOW
2508 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2509 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2510 {
2511 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2512 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2513 }
2514
2515 /**
2516 * @brief Set the IDLE state of an output channel
2517 * @note This function is significant only for the timer instances
2518 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2519 * can be used to check whether or not a timer instance provides
2520 * a break input.
2521 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2522 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2523 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2524 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2525 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2526 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2527 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2528 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2529 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2530 * CR2 OIS6 LL_TIM_OC_SetIdleState
2531 * @param TIMx Timer instance
2532 * @param Channel This parameter can be one of the following values:
2533 * @arg @ref LL_TIM_CHANNEL_CH1
2534 * @arg @ref LL_TIM_CHANNEL_CH1N
2535 * @arg @ref LL_TIM_CHANNEL_CH2
2536 * @arg @ref LL_TIM_CHANNEL_CH2N
2537 * @arg @ref LL_TIM_CHANNEL_CH3
2538 * @arg @ref LL_TIM_CHANNEL_CH3N
2539 * @arg @ref LL_TIM_CHANNEL_CH4
2540 * @arg @ref LL_TIM_CHANNEL_CH4N
2541 * @arg @ref LL_TIM_CHANNEL_CH5
2542 * @arg @ref LL_TIM_CHANNEL_CH6
2543 * @param IdleState This parameter can be one of the following values:
2544 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2545 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2546 * @retval None
2547 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2548 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2549 {
2550 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2551 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2552 }
2553
2554 /**
2555 * @brief Get the IDLE state of an output channel
2556 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2557 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2558 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2559 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2560 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2561 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2562 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2563 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2564 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2565 * CR2 OIS6 LL_TIM_OC_GetIdleState
2566 * @param TIMx Timer instance
2567 * @param Channel This parameter can be one of the following values:
2568 * @arg @ref LL_TIM_CHANNEL_CH1
2569 * @arg @ref LL_TIM_CHANNEL_CH1N
2570 * @arg @ref LL_TIM_CHANNEL_CH2
2571 * @arg @ref LL_TIM_CHANNEL_CH2N
2572 * @arg @ref LL_TIM_CHANNEL_CH3
2573 * @arg @ref LL_TIM_CHANNEL_CH3N
2574 * @arg @ref LL_TIM_CHANNEL_CH4
2575 * @arg @ref LL_TIM_CHANNEL_CH4N
2576 * @arg @ref LL_TIM_CHANNEL_CH5
2577 * @arg @ref LL_TIM_CHANNEL_CH6
2578 * @retval Returned value can be one of the following values:
2579 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2580 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2581 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2582 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2583 {
2584 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2585 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2586 }
2587
2588 /**
2589 * @brief Enable fast mode for the output channel.
2590 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2591 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2592 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2593 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2594 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2595 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2596 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2597 * @param TIMx Timer instance
2598 * @param Channel This parameter can be one of the following values:
2599 * @arg @ref LL_TIM_CHANNEL_CH1
2600 * @arg @ref LL_TIM_CHANNEL_CH2
2601 * @arg @ref LL_TIM_CHANNEL_CH3
2602 * @arg @ref LL_TIM_CHANNEL_CH4
2603 * @arg @ref LL_TIM_CHANNEL_CH5
2604 * @arg @ref LL_TIM_CHANNEL_CH6
2605 * @retval None
2606 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2607 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2608 {
2609 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2610 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2611 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2612
2613 }
2614
2615 /**
2616 * @brief Disable fast mode for the output channel.
2617 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2618 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2619 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2620 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2621 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2622 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2623 * @param TIMx Timer instance
2624 * @param Channel This parameter can be one of the following values:
2625 * @arg @ref LL_TIM_CHANNEL_CH1
2626 * @arg @ref LL_TIM_CHANNEL_CH2
2627 * @arg @ref LL_TIM_CHANNEL_CH3
2628 * @arg @ref LL_TIM_CHANNEL_CH4
2629 * @arg @ref LL_TIM_CHANNEL_CH5
2630 * @arg @ref LL_TIM_CHANNEL_CH6
2631 * @retval None
2632 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2633 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2634 {
2635 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2636 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2637 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2638
2639 }
2640
2641 /**
2642 * @brief Indicates whether fast mode is enabled for the output channel.
2643 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2644 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2645 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2646 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2647 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2648 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2649 * @param TIMx Timer instance
2650 * @param Channel This parameter can be one of the following values:
2651 * @arg @ref LL_TIM_CHANNEL_CH1
2652 * @arg @ref LL_TIM_CHANNEL_CH2
2653 * @arg @ref LL_TIM_CHANNEL_CH3
2654 * @arg @ref LL_TIM_CHANNEL_CH4
2655 * @arg @ref LL_TIM_CHANNEL_CH5
2656 * @arg @ref LL_TIM_CHANNEL_CH6
2657 * @retval State of bit (1 or 0).
2658 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2659 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2660 {
2661 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2662 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2663 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2664 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2665 }
2666
2667 /**
2668 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2669 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2670 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2671 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2672 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2673 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2674 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2675 * @param TIMx Timer instance
2676 * @param Channel This parameter can be one of the following values:
2677 * @arg @ref LL_TIM_CHANNEL_CH1
2678 * @arg @ref LL_TIM_CHANNEL_CH2
2679 * @arg @ref LL_TIM_CHANNEL_CH3
2680 * @arg @ref LL_TIM_CHANNEL_CH4
2681 * @arg @ref LL_TIM_CHANNEL_CH5
2682 * @arg @ref LL_TIM_CHANNEL_CH6
2683 * @retval None
2684 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2685 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2686 {
2687 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2688 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2689 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2690 }
2691
2692 /**
2693 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2694 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2695 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2696 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2697 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2698 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2699 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2700 * @param TIMx Timer instance
2701 * @param Channel This parameter can be one of the following values:
2702 * @arg @ref LL_TIM_CHANNEL_CH1
2703 * @arg @ref LL_TIM_CHANNEL_CH2
2704 * @arg @ref LL_TIM_CHANNEL_CH3
2705 * @arg @ref LL_TIM_CHANNEL_CH4
2706 * @arg @ref LL_TIM_CHANNEL_CH5
2707 * @arg @ref LL_TIM_CHANNEL_CH6
2708 * @retval None
2709 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2710 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2711 {
2712 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2713 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2714 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2715 }
2716
2717 /**
2718 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2719 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2720 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2721 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2722 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2723 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2724 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2725 * @param TIMx Timer instance
2726 * @param Channel This parameter can be one of the following values:
2727 * @arg @ref LL_TIM_CHANNEL_CH1
2728 * @arg @ref LL_TIM_CHANNEL_CH2
2729 * @arg @ref LL_TIM_CHANNEL_CH3
2730 * @arg @ref LL_TIM_CHANNEL_CH4
2731 * @arg @ref LL_TIM_CHANNEL_CH5
2732 * @arg @ref LL_TIM_CHANNEL_CH6
2733 * @retval State of bit (1 or 0).
2734 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2735 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2736 {
2737 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2738 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2739 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2740 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2741 }
2742
2743 /**
2744 * @brief Enable clearing the output channel on an external event.
2745 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2746 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2747 * or not a timer instance can clear the OCxREF signal on an external event.
2748 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2749 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2750 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2751 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2752 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2753 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2754 * @param TIMx Timer instance
2755 * @param Channel This parameter can be one of the following values:
2756 * @arg @ref LL_TIM_CHANNEL_CH1
2757 * @arg @ref LL_TIM_CHANNEL_CH2
2758 * @arg @ref LL_TIM_CHANNEL_CH3
2759 * @arg @ref LL_TIM_CHANNEL_CH4
2760 * @arg @ref LL_TIM_CHANNEL_CH5
2761 * @arg @ref LL_TIM_CHANNEL_CH6
2762 * @retval None
2763 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2764 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2765 {
2766 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2767 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2768 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2769 }
2770
2771 /**
2772 * @brief Disable clearing the output channel on an external event.
2773 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2774 * or not a timer instance can clear the OCxREF signal on an external event.
2775 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2776 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2777 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2778 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2779 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2780 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2781 * @param TIMx Timer instance
2782 * @param Channel This parameter can be one of the following values:
2783 * @arg @ref LL_TIM_CHANNEL_CH1
2784 * @arg @ref LL_TIM_CHANNEL_CH2
2785 * @arg @ref LL_TIM_CHANNEL_CH3
2786 * @arg @ref LL_TIM_CHANNEL_CH4
2787 * @arg @ref LL_TIM_CHANNEL_CH5
2788 * @arg @ref LL_TIM_CHANNEL_CH6
2789 * @retval None
2790 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2791 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2792 {
2793 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2794 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2795 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2796 }
2797
2798 /**
2799 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2800 * @note This function enables clearing the output channel on an external event.
2801 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2802 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2803 * or not a timer instance can clear the OCxREF signal on an external event.
2804 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2805 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2806 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2807 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2808 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2809 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2810 * @param TIMx Timer instance
2811 * @param Channel This parameter can be one of the following values:
2812 * @arg @ref LL_TIM_CHANNEL_CH1
2813 * @arg @ref LL_TIM_CHANNEL_CH2
2814 * @arg @ref LL_TIM_CHANNEL_CH3
2815 * @arg @ref LL_TIM_CHANNEL_CH4
2816 * @arg @ref LL_TIM_CHANNEL_CH5
2817 * @arg @ref LL_TIM_CHANNEL_CH6
2818 * @retval State of bit (1 or 0).
2819 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2820 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2821 {
2822 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2823 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2824 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2825 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2826 }
2827
2828 /**
2829 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2830 * the Ocx and OCxN signals).
2831 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2832 * dead-time insertion feature is supported by a timer instance.
2833 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2834 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2835 * @param TIMx Timer instance
2836 * @param DeadTime between Min_Data=0 and Max_Data=255
2837 * @retval None
2838 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2839 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2840 {
2841 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2842 }
2843
2844 /**
2845 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2846 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2847 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2848 * whether or not a timer instance supports a 32 bits counter.
2849 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2850 * output channel 1 is supported by a timer instance.
2851 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2852 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2853 * @param TIMx Timer instance
2854 * @param CompareValue between Min_Data=0 and Max_Data=65535
2855 * @retval None
2856 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2857 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2858 {
2859 WRITE_REG(TIMx->CCR1, CompareValue);
2860 }
2861
2862 /**
2863 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2864 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2865 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2866 * whether or not a timer instance supports a 32 bits counter.
2867 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2868 * output channel 2 is supported by a timer instance.
2869 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2870 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2871 * @param TIMx Timer instance
2872 * @param CompareValue between Min_Data=0 and Max_Data=65535
2873 * @retval None
2874 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2875 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2876 {
2877 WRITE_REG(TIMx->CCR2, CompareValue);
2878 }
2879
2880 /**
2881 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2882 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2883 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2884 * whether or not a timer instance supports a 32 bits counter.
2885 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2886 * output channel is supported by a timer instance.
2887 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2888 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2889 * @param TIMx Timer instance
2890 * @param CompareValue between Min_Data=0 and Max_Data=65535
2891 * @retval None
2892 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2893 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2894 {
2895 WRITE_REG(TIMx->CCR3, CompareValue);
2896 }
2897
2898 /**
2899 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2900 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2901 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2902 * whether or not a timer instance supports a 32 bits counter.
2903 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2904 * output channel 4 is supported by a timer instance.
2905 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2906 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2907 * @param TIMx Timer instance
2908 * @param CompareValue between Min_Data=0 and Max_Data=65535
2909 * @retval None
2910 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2911 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2912 {
2913 WRITE_REG(TIMx->CCR4, CompareValue);
2914 }
2915
2916 /**
2917 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2918 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2919 * output channel 5 is supported by a timer instance.
2920 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2921 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2922 * @param TIMx Timer instance
2923 * @param CompareValue between Min_Data=0 and Max_Data=65535
2924 * @retval None
2925 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)2926 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2927 {
2928 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
2929 }
2930
2931 /**
2932 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2933 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2934 * output channel 6 is supported by a timer instance.
2935 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2936 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2937 * @param TIMx Timer instance
2938 * @param CompareValue between Min_Data=0 and Max_Data=65535
2939 * @retval None
2940 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)2941 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2942 {
2943 WRITE_REG(TIMx->CCR6, CompareValue);
2944 }
2945
2946 /**
2947 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2948 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2949 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2950 * whether or not a timer instance supports a 32 bits counter.
2951 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2952 * output channel 1 is supported by a timer instance.
2953 * @note If dithering is activated, pay attention to the returned value interpretation.
2954 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2955 * @param TIMx Timer instance
2956 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2957 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)2958 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
2959 {
2960 return (uint32_t)(READ_REG(TIMx->CCR1));
2961 }
2962
2963 /**
2964 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2965 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2966 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2967 * whether or not a timer instance supports a 32 bits counter.
2968 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2969 * output channel 2 is supported by a timer instance.
2970 * @note If dithering is activated, pay attention to the returned value interpretation.
2971 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2972 * @param TIMx Timer instance
2973 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2974 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)2975 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
2976 {
2977 return (uint32_t)(READ_REG(TIMx->CCR2));
2978 }
2979
2980 /**
2981 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2982 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2983 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2984 * whether or not a timer instance supports a 32 bits counter.
2985 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2986 * output channel 3 is supported by a timer instance.
2987 * @note If dithering is activated, pay attention to the returned value interpretation.
2988 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2989 * @param TIMx Timer instance
2990 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2991 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)2992 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
2993 {
2994 return (uint32_t)(READ_REG(TIMx->CCR3));
2995 }
2996
2997 /**
2998 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2999 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3000 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3001 * whether or not a timer instance supports a 32 bits counter.
3002 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3003 * output channel 4 is supported by a timer instance.
3004 * @note If dithering is activated, pay attention to the returned value interpretation.
3005 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3006 * @param TIMx Timer instance
3007 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3008 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3009 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3010 {
3011 return (uint32_t)(READ_REG(TIMx->CCR4));
3012 }
3013
3014 /**
3015 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3016 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3017 * output channel 5 is supported by a timer instance.
3018 * @note If dithering is activated, pay attention to the returned value interpretation.
3019 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3020 * @param TIMx Timer instance
3021 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3022 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3023 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3024 {
3025 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3026 }
3027
3028 /**
3029 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3030 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3031 * output channel 6 is supported by a timer instance.
3032 * @note If dithering is activated, pay attention to the returned value interpretation.
3033 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3034 * @param TIMx Timer instance
3035 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3036 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3037 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3038 {
3039 return (uint32_t)(READ_REG(TIMx->CCR6));
3040 }
3041
3042 /**
3043 * @brief Select on which reference signal the OC5REF is combined to.
3044 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3045 * whether or not a timer instance supports the combined 3-phase PWM mode.
3046 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3047 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3048 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3049 * @param TIMx Timer instance
3050 * @param GroupCH5 This parameter can be a combination of the following values:
3051 * @arg @ref LL_TIM_GROUPCH5_NONE
3052 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3053 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3054 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3055 * @retval None
3056 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3057 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3058 {
3059 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3060 }
3061
3062 /**
3063 * @brief Set the pulse on compare pulse width prescaler.
3064 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3065 * whether or not the pulse on compare feature is supported by the timer
3066 * instance.
3067 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3068 * @param TIMx Timer instance
3069 * @param PulseWidthPrescaler This parameter can be one of the following values:
3070 * @arg @ref LL_TIM_PWPRSC_X1
3071 * @arg @ref LL_TIM_PWPRSC_X2
3072 * @arg @ref LL_TIM_PWPRSC_X4
3073 * @arg @ref LL_TIM_PWPRSC_X8
3074 * @arg @ref LL_TIM_PWPRSC_X16
3075 * @arg @ref LL_TIM_PWPRSC_X32
3076 * @arg @ref LL_TIM_PWPRSC_X64
3077 * @arg @ref LL_TIM_PWPRSC_X128
3078 * @retval None
3079 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3080 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3081 {
3082 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3083 }
3084
3085 /**
3086 * @brief Get the pulse on compare pulse width prescaler.
3087 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3088 * whether or not the pulse on compare feature is supported by the timer
3089 * instance.
3090 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3091 * @param TIMx Timer instance
3092 * @retval Returned value can be one of the following values:
3093 * @arg @ref LL_TIM_PWPRSC_X1
3094 * @arg @ref LL_TIM_PWPRSC_X2
3095 * @arg @ref LL_TIM_PWPRSC_X4
3096 * @arg @ref LL_TIM_PWPRSC_X8
3097 * @arg @ref LL_TIM_PWPRSC_X16
3098 * @arg @ref LL_TIM_PWPRSC_X32
3099 * @arg @ref LL_TIM_PWPRSC_X64
3100 * @arg @ref LL_TIM_PWPRSC_X128
3101 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3102 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3103 {
3104 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3105 }
3106
3107 /**
3108 * @brief Set the pulse on compare pulse width duration.
3109 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3110 * whether or not the pulse on compare feature is supported by the timer
3111 * instance.
3112 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3113 * @param TIMx Timer instance
3114 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3115 * @retval None
3116 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3117 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3118 {
3119 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3120 }
3121
3122 /**
3123 * @brief Get the pulse on compare pulse width duration.
3124 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3125 * whether or not the pulse on compare feature is supported by the timer
3126 * instance.
3127 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3128 * @param TIMx Timer instance
3129 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3130 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3131 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3132 {
3133 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3134 }
3135
3136 /**
3137 * @}
3138 */
3139
3140 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3141 * @{
3142 */
3143 /**
3144 * @brief Configure input channel.
3145 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3146 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3147 * CCMR1 IC1F LL_TIM_IC_Config\n
3148 * CCMR1 CC2S LL_TIM_IC_Config\n
3149 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3150 * CCMR1 IC2F LL_TIM_IC_Config\n
3151 * CCMR2 CC3S LL_TIM_IC_Config\n
3152 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3153 * CCMR2 IC3F LL_TIM_IC_Config\n
3154 * CCMR2 CC4S LL_TIM_IC_Config\n
3155 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3156 * CCMR2 IC4F LL_TIM_IC_Config\n
3157 * CCER CC1P LL_TIM_IC_Config\n
3158 * CCER CC1NP LL_TIM_IC_Config\n
3159 * CCER CC2P LL_TIM_IC_Config\n
3160 * CCER CC2NP LL_TIM_IC_Config\n
3161 * CCER CC3P LL_TIM_IC_Config\n
3162 * CCER CC3NP LL_TIM_IC_Config\n
3163 * CCER CC4P LL_TIM_IC_Config\n
3164 * CCER CC4NP LL_TIM_IC_Config
3165 * @param TIMx Timer instance
3166 * @param Channel This parameter can be one of the following values:
3167 * @arg @ref LL_TIM_CHANNEL_CH1
3168 * @arg @ref LL_TIM_CHANNEL_CH2
3169 * @arg @ref LL_TIM_CHANNEL_CH3
3170 * @arg @ref LL_TIM_CHANNEL_CH4
3171 * @param Configuration This parameter must be a combination of all the following values:
3172 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3173 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3174 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3175 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3176 * @retval None
3177 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3178 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3179 {
3180 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3181 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3182 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3183 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3184 << SHIFT_TAB_ICxx[iChannel]);
3185 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3186 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3187 }
3188
3189 /**
3190 * @brief Set the active input.
3191 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3192 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3193 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3194 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3195 * @param TIMx Timer instance
3196 * @param Channel This parameter can be one of the following values:
3197 * @arg @ref LL_TIM_CHANNEL_CH1
3198 * @arg @ref LL_TIM_CHANNEL_CH2
3199 * @arg @ref LL_TIM_CHANNEL_CH3
3200 * @arg @ref LL_TIM_CHANNEL_CH4
3201 * @param ICActiveInput This parameter can be one of the following values:
3202 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3203 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3204 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3205 * @retval None
3206 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3207 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3208 {
3209 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3210 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3211 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3212 }
3213
3214 /**
3215 * @brief Get the current active input.
3216 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3217 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3218 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3219 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3220 * @param TIMx Timer instance
3221 * @param Channel This parameter can be one of the following values:
3222 * @arg @ref LL_TIM_CHANNEL_CH1
3223 * @arg @ref LL_TIM_CHANNEL_CH2
3224 * @arg @ref LL_TIM_CHANNEL_CH3
3225 * @arg @ref LL_TIM_CHANNEL_CH4
3226 * @retval Returned value can be one of the following values:
3227 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3228 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3229 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3230 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3231 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3232 {
3233 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3234 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3235 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3236 }
3237
3238 /**
3239 * @brief Set the prescaler of input channel.
3240 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3241 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3242 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3243 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3244 * @param TIMx Timer instance
3245 * @param Channel This parameter can be one of the following values:
3246 * @arg @ref LL_TIM_CHANNEL_CH1
3247 * @arg @ref LL_TIM_CHANNEL_CH2
3248 * @arg @ref LL_TIM_CHANNEL_CH3
3249 * @arg @ref LL_TIM_CHANNEL_CH4
3250 * @param ICPrescaler This parameter can be one of the following values:
3251 * @arg @ref LL_TIM_ICPSC_DIV1
3252 * @arg @ref LL_TIM_ICPSC_DIV2
3253 * @arg @ref LL_TIM_ICPSC_DIV4
3254 * @arg @ref LL_TIM_ICPSC_DIV8
3255 * @retval None
3256 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3257 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3258 {
3259 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3260 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3261 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3262 }
3263
3264 /**
3265 * @brief Get the current prescaler value acting on an input channel.
3266 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3267 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3268 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3269 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3270 * @param TIMx Timer instance
3271 * @param Channel This parameter can be one of the following values:
3272 * @arg @ref LL_TIM_CHANNEL_CH1
3273 * @arg @ref LL_TIM_CHANNEL_CH2
3274 * @arg @ref LL_TIM_CHANNEL_CH3
3275 * @arg @ref LL_TIM_CHANNEL_CH4
3276 * @retval Returned value can be one of the following values:
3277 * @arg @ref LL_TIM_ICPSC_DIV1
3278 * @arg @ref LL_TIM_ICPSC_DIV2
3279 * @arg @ref LL_TIM_ICPSC_DIV4
3280 * @arg @ref LL_TIM_ICPSC_DIV8
3281 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3282 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3283 {
3284 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3285 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3286 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3287 }
3288
3289 /**
3290 * @brief Set the input filter duration.
3291 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3292 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3293 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3294 * CCMR2 IC4F LL_TIM_IC_SetFilter
3295 * @param TIMx Timer instance
3296 * @param Channel This parameter can be one of the following values:
3297 * @arg @ref LL_TIM_CHANNEL_CH1
3298 * @arg @ref LL_TIM_CHANNEL_CH2
3299 * @arg @ref LL_TIM_CHANNEL_CH3
3300 * @arg @ref LL_TIM_CHANNEL_CH4
3301 * @param ICFilter This parameter can be one of the following values:
3302 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3303 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3304 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3305 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3306 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3307 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3308 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3309 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3310 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3311 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3312 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3313 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3314 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3315 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3316 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3317 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3318 * @retval None
3319 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3320 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3321 {
3322 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3323 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3324 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3325 }
3326
3327 /**
3328 * @brief Get the input filter duration.
3329 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3330 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3331 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3332 * CCMR2 IC4F LL_TIM_IC_GetFilter
3333 * @param TIMx Timer instance
3334 * @param Channel This parameter can be one of the following values:
3335 * @arg @ref LL_TIM_CHANNEL_CH1
3336 * @arg @ref LL_TIM_CHANNEL_CH2
3337 * @arg @ref LL_TIM_CHANNEL_CH3
3338 * @arg @ref LL_TIM_CHANNEL_CH4
3339 * @retval Returned value can be one of the following values:
3340 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3341 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3342 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3343 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3344 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3345 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3346 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3347 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3348 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3349 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3350 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3351 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3352 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3353 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3354 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3355 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3356 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3357 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3358 {
3359 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3360 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3361 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3362 }
3363
3364 /**
3365 * @brief Set the input channel polarity.
3366 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3367 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3368 * CCER CC2P LL_TIM_IC_SetPolarity\n
3369 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3370 * CCER CC3P LL_TIM_IC_SetPolarity\n
3371 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3372 * CCER CC4P LL_TIM_IC_SetPolarity\n
3373 * CCER CC4NP LL_TIM_IC_SetPolarity
3374 * @param TIMx Timer instance
3375 * @param Channel This parameter can be one of the following values:
3376 * @arg @ref LL_TIM_CHANNEL_CH1
3377 * @arg @ref LL_TIM_CHANNEL_CH2
3378 * @arg @ref LL_TIM_CHANNEL_CH3
3379 * @arg @ref LL_TIM_CHANNEL_CH4
3380 * @param ICPolarity This parameter can be one of the following values:
3381 * @arg @ref LL_TIM_IC_POLARITY_RISING
3382 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3383 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3384 * @retval None
3385 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3386 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3387 {
3388 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3389 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3390 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3391 }
3392
3393 /**
3394 * @brief Get the current input channel polarity.
3395 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3396 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3397 * CCER CC2P LL_TIM_IC_GetPolarity\n
3398 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3399 * CCER CC3P LL_TIM_IC_GetPolarity\n
3400 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3401 * CCER CC4P LL_TIM_IC_GetPolarity\n
3402 * CCER CC4NP LL_TIM_IC_GetPolarity
3403 * @param TIMx Timer instance
3404 * @param Channel This parameter can be one of the following values:
3405 * @arg @ref LL_TIM_CHANNEL_CH1
3406 * @arg @ref LL_TIM_CHANNEL_CH2
3407 * @arg @ref LL_TIM_CHANNEL_CH3
3408 * @arg @ref LL_TIM_CHANNEL_CH4
3409 * @retval Returned value can be one of the following values:
3410 * @arg @ref LL_TIM_IC_POLARITY_RISING
3411 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3412 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3413 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3414 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3415 {
3416 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3417 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3418 SHIFT_TAB_CCxP[iChannel]);
3419 }
3420
3421 /**
3422 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3423 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3424 * a timer instance provides an XOR input.
3425 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3426 * @param TIMx Timer instance
3427 * @retval None
3428 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3429 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3430 {
3431 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3432 }
3433
3434 /**
3435 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3436 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3437 * a timer instance provides an XOR input.
3438 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3439 * @param TIMx Timer instance
3440 * @retval None
3441 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3442 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3443 {
3444 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3445 }
3446
3447 /**
3448 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3449 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3450 * a timer instance provides an XOR input.
3451 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3452 * @param TIMx Timer instance
3453 * @retval State of bit (1 or 0).
3454 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3455 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3456 {
3457 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3458 }
3459
3460 /**
3461 * @brief Get captured value for input channel 1.
3462 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3463 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3464 * whether or not a timer instance supports a 32 bits counter.
3465 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3466 * input channel 1 is supported by a timer instance.
3467 * @note If dithering is activated, pay attention to the returned value interpretation.
3468 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3469 * @param TIMx Timer instance
3470 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3471 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3472 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3473 {
3474 return (uint32_t)(READ_REG(TIMx->CCR1));
3475 }
3476
3477 /**
3478 * @brief Get captured value for input channel 2.
3479 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3480 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3481 * whether or not a timer instance supports a 32 bits counter.
3482 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3483 * input channel 2 is supported by a timer instance.
3484 * @note If dithering is activated, pay attention to the returned value interpretation.
3485 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3486 * @param TIMx Timer instance
3487 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3488 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3489 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3490 {
3491 return (uint32_t)(READ_REG(TIMx->CCR2));
3492 }
3493
3494 /**
3495 * @brief Get captured value for input channel 3.
3496 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3497 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3498 * whether or not a timer instance supports a 32 bits counter.
3499 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3500 * input channel 3 is supported by a timer instance.
3501 * @note If dithering is activated, pay attention to the returned value interpretation.
3502 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3503 * @param TIMx Timer instance
3504 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3505 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3506 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3507 {
3508 return (uint32_t)(READ_REG(TIMx->CCR3));
3509 }
3510
3511 /**
3512 * @brief Get captured value for input channel 4.
3513 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3514 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3515 * whether or not a timer instance supports a 32 bits counter.
3516 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3517 * input channel 4 is supported by a timer instance.
3518 * @note If dithering is activated, pay attention to the returned value interpretation.
3519 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3520 * @param TIMx Timer instance
3521 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3522 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3523 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3524 {
3525 return (uint32_t)(READ_REG(TIMx->CCR4));
3526 }
3527
3528 /**
3529 * @}
3530 */
3531
3532 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3533 * @{
3534 */
3535 /**
3536 * @brief Enable external clock mode 2.
3537 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3538 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3539 * whether or not a timer instance supports external clock mode2.
3540 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3541 * @param TIMx Timer instance
3542 * @retval None
3543 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3544 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3545 {
3546 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3547 }
3548
3549 /**
3550 * @brief Disable external clock mode 2.
3551 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3552 * whether or not a timer instance supports external clock mode2.
3553 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3554 * @param TIMx Timer instance
3555 * @retval None
3556 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3557 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3558 {
3559 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3560 }
3561
3562 /**
3563 * @brief Indicate whether external clock mode 2 is enabled.
3564 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3565 * whether or not a timer instance supports external clock mode2.
3566 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3567 * @param TIMx Timer instance
3568 * @retval State of bit (1 or 0).
3569 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3570 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3571 {
3572 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3573 }
3574
3575 /**
3576 * @brief Set the clock source of the counter clock.
3577 * @note when selected clock source is external clock mode 1, the timer input
3578 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3579 * function. This timer input must be configured by calling
3580 * the @ref LL_TIM_IC_Config() function.
3581 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3582 * whether or not a timer instance supports external clock mode1.
3583 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3584 * whether or not a timer instance supports external clock mode2.
3585 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3586 * SMCR ECE LL_TIM_SetClockSource
3587 * @param TIMx Timer instance
3588 * @param ClockSource This parameter can be one of the following values:
3589 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3590 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3591 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3592 * @retval None
3593 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3594 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3595 {
3596 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3597 }
3598
3599 /**
3600 * @brief Set the encoder interface mode.
3601 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3602 * whether or not a timer instance supports the encoder mode.
3603 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3604 * @param TIMx Timer instance
3605 * @param EncoderMode This parameter can be one of the following values:
3606 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3607 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3608 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3609 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3610 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3611 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3612 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3613 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3614 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3615 * @retval None
3616 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3617 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3618 {
3619 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3620 }
3621
3622 /**
3623 * @}
3624 */
3625
3626 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3627 * @{
3628 */
3629 /**
3630 * @brief Set the trigger output (TRGO) used for timer synchronization .
3631 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3632 * whether or not a timer instance can operate as a master timer.
3633 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3634 * @param TIMx Timer instance
3635 * @param TimerSynchronization This parameter can be one of the following values:
3636 * @arg @ref LL_TIM_TRGO_RESET
3637 * @arg @ref LL_TIM_TRGO_ENABLE
3638 * @arg @ref LL_TIM_TRGO_UPDATE
3639 * @arg @ref LL_TIM_TRGO_CC1IF
3640 * @arg @ref LL_TIM_TRGO_OC1REF
3641 * @arg @ref LL_TIM_TRGO_OC2REF
3642 * @arg @ref LL_TIM_TRGO_OC3REF
3643 * @arg @ref LL_TIM_TRGO_OC4REF
3644 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3645 * @retval None
3646 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3647 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3648 {
3649 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3650 }
3651
3652 /**
3653 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3654 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3655 * whether or not a timer instance can be used for ADC synchronization.
3656 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3657 * @param TIMx Timer Instance
3658 * @param ADCSynchronization This parameter can be one of the following values:
3659 * @arg @ref LL_TIM_TRGO2_RESET
3660 * @arg @ref LL_TIM_TRGO2_ENABLE
3661 * @arg @ref LL_TIM_TRGO2_UPDATE
3662 * @arg @ref LL_TIM_TRGO2_CC1F
3663 * @arg @ref LL_TIM_TRGO2_OC1
3664 * @arg @ref LL_TIM_TRGO2_OC2
3665 * @arg @ref LL_TIM_TRGO2_OC3
3666 * @arg @ref LL_TIM_TRGO2_OC4
3667 * @arg @ref LL_TIM_TRGO2_OC5
3668 * @arg @ref LL_TIM_TRGO2_OC6
3669 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3670 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3671 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3672 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3673 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3674 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3675 * @retval None
3676 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3677 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3678 {
3679 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3680 }
3681
3682 /**
3683 * @brief Set the synchronization mode of a slave timer.
3684 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3685 * a timer instance can operate as a slave timer.
3686 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3687 * @param TIMx Timer instance
3688 * @param SlaveMode This parameter can be one of the following values:
3689 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3690 * @arg @ref LL_TIM_SLAVEMODE_RESET
3691 * @arg @ref LL_TIM_SLAVEMODE_GATED
3692 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3693 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3694 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3695 * @retval None
3696 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3697 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3698 {
3699 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3700 }
3701
3702 /**
3703 * @brief Set the selects the trigger input to be used to synchronize the counter.
3704 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3705 * a timer instance can operate as a slave timer.
3706 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3707 * @param TIMx Timer instance
3708 * @param TriggerInput This parameter can be one of the following values:
3709 * @arg @ref LL_TIM_TS_ITR0
3710 * @arg @ref LL_TIM_TS_ITR1
3711 * @arg @ref LL_TIM_TS_ITR2
3712 * @arg @ref LL_TIM_TS_ITR3
3713 * @arg @ref LL_TIM_TS_ITR4
3714 * @arg @ref LL_TIM_TS_ITR5
3715 * @arg @ref LL_TIM_TS_ITR6
3716 * @arg @ref LL_TIM_TS_ITR7
3717 * @arg @ref LL_TIM_TS_ITR8
3718 * @arg @ref LL_TIM_TS_ITR9
3719 * @arg @ref LL_TIM_TS_ITR10
3720 * @arg @ref LL_TIM_TS_ITR11
3721 * @arg @ref LL_TIM_TS_ITR12
3722 * @arg @ref LL_TIM_TS_ITR13
3723 * @arg @ref LL_TIM_TS_ITR14
3724 * @arg @ref LL_TIM_TS_TI1F_ED
3725 * @arg @ref LL_TIM_TS_TI1FP1
3726 * @arg @ref LL_TIM_TS_TI2FP2
3727 * @arg @ref LL_TIM_TS_ETRF
3728 * @retval None
3729 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3730 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3731 {
3732 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3733 }
3734
3735 /**
3736 * @brief Enable the Master/Slave mode.
3737 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3738 * a timer instance can operate as a slave timer.
3739 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3740 * @param TIMx Timer instance
3741 * @retval None
3742 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3743 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3744 {
3745 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3746 }
3747
3748 /**
3749 * @brief Disable the Master/Slave mode.
3750 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3751 * a timer instance can operate as a slave timer.
3752 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3753 * @param TIMx Timer instance
3754 * @retval None
3755 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3756 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3757 {
3758 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3759 }
3760
3761 /**
3762 * @brief Indicates whether the Master/Slave mode is enabled.
3763 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3764 * a timer instance can operate as a slave timer.
3765 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3766 * @param TIMx Timer instance
3767 * @retval State of bit (1 or 0).
3768 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3769 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3770 {
3771 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3772 }
3773
3774 /**
3775 * @brief Configure the external trigger (ETR) input.
3776 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3777 * a timer instance provides an external trigger input.
3778 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3779 * SMCR ETPS LL_TIM_ConfigETR\n
3780 * SMCR ETF LL_TIM_ConfigETR
3781 * @param TIMx Timer instance
3782 * @param ETRPolarity This parameter can be one of the following values:
3783 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3784 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3785 * @param ETRPrescaler This parameter can be one of the following values:
3786 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3787 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3788 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3789 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3790 * @param ETRFilter This parameter can be one of the following values:
3791 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3792 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3793 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3794 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3795 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3796 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3797 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3798 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3799 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3800 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3801 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3802 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3803 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3804 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3805 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3806 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3807 * @retval None
3808 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3809 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3810 uint32_t ETRFilter)
3811 {
3812 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3813 }
3814
3815 /**
3816 * @brief Select the external trigger (ETR) input source.
3817 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3818 * not a timer instance supports ETR source selection.
3819 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3820 * @param TIMx Timer instance
3821 * @param ETRSource This parameter can be one of the following values:
3822 *
3823 * For TIM1, the parameter is one of the following values:
3824 *
3825 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3826 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
3827 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
3828 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
3829 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1
3830 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2
3831 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3
3832 *
3833 * For TIM2, the parameter is one of the following values:
3834 *
3835 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3836 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC
3837 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC
3838 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA
3839 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB
3840 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE
3841 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC
3842 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC
3843 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
3844 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
3845 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
3846 * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS
3847 *
3848 * For TIM3, the parameter is one of the following values:
3849 *
3850 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3851 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC
3852 * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC
3853 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE
3854 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC
3855 * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC
3856 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
3857 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
3858 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR
3859 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS
3860 *
3861 * For TIM4, the parameter is one of the following values:
3862 *
3863 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
3864 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC
3865 * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC
3866 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE
3867 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC
3868 * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC
3869 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
3870 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
3871 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
3872 *
3873 * For TIM5, the parameter is one of the following values:
3874 *
3875 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
3876 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
3877 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
3878 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC
3879 * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC
3880 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE
3881 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC
3882 * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC
3883 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
3884 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
3885 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
3886 * @retval None
3887 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3888 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3889 {
3890 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3891 }
3892
3893 /**
3894 * @brief Enable SMS preload.
3895 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3896 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3897 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
3898 * @param TIMx Timer instance
3899 * @retval None
3900 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)3901 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
3902 {
3903 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3904 }
3905
3906 /**
3907 * @brief Disable SMS preload.
3908 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3909 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3910 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
3911 * @param TIMx Timer instance
3912 * @retval None
3913 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)3914 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
3915 {
3916 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3917 }
3918
3919 /**
3920 * @brief Indicate whether SMS preload is enabled.
3921 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3922 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3923 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
3924 * @param TIMx Timer instance
3925 * @retval State of bit (1 or 0).
3926 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)3927 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
3928 {
3929 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
3930 }
3931
3932 /**
3933 * @brief Set the preload source of SMS.
3934 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3935 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3936 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
3937 * @param TIMx Timer instance
3938 * @param PreloadSource This parameter can be one of the following values:
3939 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
3940 * @arg @ref LL_TIM_SMSPS_INDEX
3941 * @retval None
3942 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)3943 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
3944 {
3945 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
3946 }
3947
3948 /**
3949 * @brief Get the preload source of SMS.
3950 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3951 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3952 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
3953 * @param TIMx Timer instance
3954 * @retval Returned value can be one of the following values:
3955 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
3956 * @arg @ref LL_TIM_SMSPS_INDEX
3957 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)3958 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
3959 {
3960 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
3961 }
3962
3963 /**
3964 * @}
3965 */
3966
3967 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3968 * @{
3969 */
3970 /**
3971 * @brief Enable the break function.
3972 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3973 * a timer instance provides a break input.
3974 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3975 * @param TIMx Timer instance
3976 * @retval None
3977 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)3978 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3979 {
3980 __IO uint32_t tmpreg;
3981 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3982 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
3983 tmpreg = READ_REG(TIMx->BDTR);
3984 (void)(tmpreg);
3985 }
3986
3987 /**
3988 * @brief Disable the break function.
3989 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3990 * @param TIMx Timer instance
3991 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3992 * a timer instance provides a break input.
3993 * @retval None
3994 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)3995 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3996 {
3997 __IO uint32_t tmpreg;
3998 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3999 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4000 tmpreg = READ_REG(TIMx->BDTR);
4001 (void)(tmpreg);
4002 }
4003
4004 /**
4005 * @brief Configure the break input.
4006 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4007 * a timer instance provides a break input.
4008 * @note Bidirectional mode is only supported by advanced timer instances.
4009 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4010 * a timer instance is an advanced-control timer.
4011 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4012 * in input mode and in open drain output mode. Any active Break event will
4013 * assert a low logic level on the Break input to indicate an internal break
4014 * event to external devices.
4015 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4016 * LL_TIM_BREAK_AFMODE_INPUT.
4017 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4018 * BDTR BKF LL_TIM_ConfigBRK\n
4019 * BDTR BKBID LL_TIM_ConfigBRK
4020 * @param TIMx Timer instance
4021 * @param BreakPolarity This parameter can be one of the following values:
4022 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4023 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4024 * @param BreakFilter This parameter can be one of the following values:
4025 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4026 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4027 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4028 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4029 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4030 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4031 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4032 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4033 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4034 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4035 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4036 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4037 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4038 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4039 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4040 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4041 * @param BreakAFMode This parameter can be one of the following values:
4042 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4043 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4044 * @retval None
4045 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4046 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4047 uint32_t BreakAFMode)
4048 {
4049 __IO uint32_t tmpreg;
4050 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4051 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
4052 tmpreg = READ_REG(TIMx->BDTR);
4053 (void)(tmpreg);
4054 }
4055
4056 /**
4057 * @brief Disarm the break input (when it operates in bidirectional mode).
4058 * @note The break input can be disarmed only when it is configured in
4059 * bidirectional mode and when when MOE is reset.
4060 * @note Purpose is to be able to have the input voltage back to high-state,
4061 * whatever the time constant on the output .
4062 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4063 * @param TIMx Timer instance
4064 * @retval None
4065 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4066 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4067 {
4068 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4069 }
4070
4071 /**
4072 * @brief Enable the break 2 function.
4073 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4074 * a timer instance provides a second break input.
4075 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4076 * @param TIMx Timer instance
4077 * @retval None
4078 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4079 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4080 {
4081 __IO uint32_t tmpreg;
4082 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4083 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4084 tmpreg = READ_REG(TIMx->BDTR);
4085 (void)(tmpreg);
4086 }
4087
4088 /**
4089 * @brief Disable the break 2 function.
4090 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4091 * a timer instance provides a second break input.
4092 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4093 * @param TIMx Timer instance
4094 * @retval None
4095 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4096 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4097 {
4098 __IO uint32_t tmpreg;
4099 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4100 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4101 tmpreg = READ_REG(TIMx->BDTR);
4102 (void)(tmpreg);
4103 }
4104
4105 /**
4106 * @brief Configure the break 2 input.
4107 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4108 * a timer instance provides a second break input.
4109 * @note Bidirectional mode is only supported by advanced timer instances.
4110 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4111 * a timer instance is an advanced-control timer.
4112 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4113 * in input mode and in open drain output mode. Any active Break event will
4114 * assert a low logic level on the Break 2 input to indicate an internal break
4115 * event to external devices.
4116 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4117 * LL_TIM_BREAK2_AFMODE_INPUT.
4118 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4119 * BDTR BK2F LL_TIM_ConfigBRK2\n
4120 * BDTR BK2BID LL_TIM_ConfigBRK2
4121 * @param TIMx Timer instance
4122 * @param Break2Polarity This parameter can be one of the following values:
4123 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4124 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4125 * @param Break2Filter This parameter can be one of the following values:
4126 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4127 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4128 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4129 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4130 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4131 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4132 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4133 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4134 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4135 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4136 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4137 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4138 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4139 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4140 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4141 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4142 * @param Break2AFMode This parameter can be one of the following values:
4143 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4144 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4145 * @retval None
4146 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4147 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4148 uint32_t Break2AFMode)
4149 {
4150 __IO uint32_t tmpreg;
4151 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4152 /* Note: Any write operation to BK2P bit takes a delay of 1 APB clock cycle to become effective. */
4153 tmpreg = READ_REG(TIMx->BDTR);
4154 (void)(tmpreg);
4155 }
4156
4157 /**
4158 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4159 * @note The break 2 input can be disarmed only when it is configured in
4160 * bidirectional mode and when when MOE is reset.
4161 * @note Purpose is to be able to have the input voltage back to high-state,
4162 * whatever the time constant on the output.
4163 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4164 * @param TIMx Timer instance
4165 * @retval None
4166 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4167 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4168 {
4169 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4170 }
4171
4172 /**
4173 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4174 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4175 * a timer instance provides a break input.
4176 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4177 * BDTR OSSR LL_TIM_SetOffStates
4178 * @param TIMx Timer instance
4179 * @param OffStateIdle This parameter can be one of the following values:
4180 * @arg @ref LL_TIM_OSSI_DISABLE
4181 * @arg @ref LL_TIM_OSSI_ENABLE
4182 * @param OffStateRun This parameter can be one of the following values:
4183 * @arg @ref LL_TIM_OSSR_DISABLE
4184 * @arg @ref LL_TIM_OSSR_ENABLE
4185 * @retval None
4186 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4187 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4188 {
4189 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4190 }
4191
4192 /**
4193 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4194 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4195 * a timer instance provides a break input.
4196 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4197 * @param TIMx Timer instance
4198 * @retval None
4199 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4200 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4201 {
4202 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4203 }
4204
4205 /**
4206 * @brief Disable automatic output (MOE can be set only by software).
4207 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4208 * a timer instance provides a break input.
4209 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4210 * @param TIMx Timer instance
4211 * @retval None
4212 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4213 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4214 {
4215 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4216 }
4217
4218 /**
4219 * @brief Indicate whether automatic output is enabled.
4220 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4221 * a timer instance provides a break input.
4222 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4223 * @param TIMx Timer instance
4224 * @retval State of bit (1 or 0).
4225 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4226 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4227 {
4228 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4229 }
4230
4231 /**
4232 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4233 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4234 * software and is reset in case of break or break2 event
4235 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4236 * a timer instance provides a break input.
4237 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4238 * @param TIMx Timer instance
4239 * @retval None
4240 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4241 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4242 {
4243 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4244 }
4245
4246 /**
4247 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4248 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4249 * software and is reset in case of break or break2 event.
4250 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4251 * a timer instance provides a break input.
4252 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4253 * @param TIMx Timer instance
4254 * @retval None
4255 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4256 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4257 {
4258 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4259 }
4260
4261 /**
4262 * @brief Indicates whether outputs are enabled.
4263 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4264 * a timer instance provides a break input.
4265 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4266 * @param TIMx Timer instance
4267 * @retval State of bit (1 or 0).
4268 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4269 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4270 {
4271 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4272 }
4273
4274 /**
4275 * @brief Enable the signals connected to the designated timer break input.
4276 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4277 * or not a timer instance allows for break input selection.
4278 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4279 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4280 * @param TIMx Timer instance
4281 * @param BreakInput This parameter can be one of the following values:
4282 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4283 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4284 * @param Source This parameter can be one of the following values:
4285 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4286 * @retval None
4287 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4288 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4289 {
4290 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4291 SET_BIT(*pReg, Source);
4292 }
4293
4294 /**
4295 * @brief Disable the signals connected to the designated timer break input.
4296 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4297 * or not a timer instance allows for break input selection.
4298 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4299 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4300 * @param TIMx Timer instance
4301 * @param BreakInput This parameter can be one of the following values:
4302 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4303 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4304 * @param Source This parameter can be one of the following values:
4305 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4306 * @retval None
4307 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4308 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4309 {
4310 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4311 CLEAR_BIT(*pReg, Source);
4312 }
4313
4314 /**
4315 * @brief Set the polarity of the break signal for the timer break input.
4316 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4317 * or not a timer instance allows for break input selection.
4318 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4319 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4320 * @param TIMx Timer instance
4321 * @param BreakInput This parameter can be one of the following values:
4322 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4323 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4324 * @param Source This parameter can be one of the following values:
4325 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4326 * @param Polarity This parameter can be one of the following values:
4327 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4328 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4329 * @retval None
4330 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4331 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4332 uint32_t Polarity)
4333 {
4334 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4335 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4336 }
4337 /**
4338 * @brief Enable asymmetrical deadtime.
4339 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4340 * a timer instance provides asymmetrical deadtime.
4341 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4342 * @param TIMx Timer instance
4343 * @retval None
4344 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4345 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4346 {
4347 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4348 }
4349
4350 /**
4351 * @brief Disable asymmetrical dead-time.
4352 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4353 * a timer instance provides asymmetrical deadtime.
4354 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4355 * @param TIMx Timer instance
4356 * @retval None
4357 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4358 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4359 {
4360 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4361 }
4362
4363 /**
4364 * @brief Indicates whether asymmetrical deadtime is activated.
4365 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4366 * a timer instance provides asymmetrical deadtime.
4367 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4368 * @param TIMx Timer instance
4369 * @retval State of bit (1 or 0).
4370 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4371 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4372 {
4373 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4374 }
4375
4376 /**
4377 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4378 * rising edge of OCxN signals).
4379 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4380 * asymmetrical dead-time insertion feature is supported by a timer instance.
4381 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4382 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4383 * (LOCK bits in TIMx_BDTR register).
4384 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4385 * @param TIMx Timer instance
4386 * @param DeadTime between Min_Data=0 and Max_Data=255
4387 * @retval None
4388 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4389 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4390 {
4391 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4392 }
4393
4394 /**
4395 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4396 * the rising edge of OCxN signals).
4397 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4398 * asymmetrical dead-time insertion feature is supported by a timer instance.
4399 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4400 * (LOCK bits in TIMx_BDTR register).
4401 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4402 * @param TIMx Timer instance
4403 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4404 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4405 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4406 {
4407 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4408 }
4409
4410 /**
4411 * @brief Enable deadtime preload.
4412 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4413 * a timer instance provides deadtime preload.
4414 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4415 * @param TIMx Timer instance
4416 * @retval None
4417 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4418 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4419 {
4420 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4421 }
4422
4423 /**
4424 * @brief Disable dead-time preload.
4425 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4426 * a timer instance provides deadtime preload.
4427 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4428 * @param TIMx Timer instance
4429 * @retval None
4430 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4431 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4432 {
4433 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4434 }
4435
4436 /**
4437 * @brief Indicates whether deadtime preload is activated.
4438 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4439 * a timer instance provides deadtime preload.
4440 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4441 * @param TIMx Timer instance
4442 * @retval State of bit (1 or 0).
4443 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4444 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4445 {
4446 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4447 }
4448
4449 /**
4450 * @}
4451 */
4452
4453 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4454 * @{
4455 */
4456 /**
4457 * @brief Configures the timer DMA burst feature.
4458 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4459 * not a timer instance supports the DMA burst mode.
4460 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4461 * DCR DBA LL_TIM_ConfigDMABurst
4462 * @param TIMx Timer instance
4463 * @param DMABurstBaseAddress This parameter can be one of the following values:
4464 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4465 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4466 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4467 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4468 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4469 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4470 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4471 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4472 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4473 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4474 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4475 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4476 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4477 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4478 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4479 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4480 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4481 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4482 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4483 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4484 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4485 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4486 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4487 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4488 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4489 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4490 * @param DMABurstLength This parameter can be one of the following values:
4491 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4492 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4493 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4494 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4495 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4496 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4497 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4498 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4499 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4500 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4501 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4502 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4503 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4504 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4505 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4506 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4507 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4508 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4509 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4510 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4511 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4512 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4513 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4514 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4515 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4516 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4517 * @param DMABurstSource This parameter can be one of the following values:
4518 * @arg @ref LL_TIM_DMA_UPDATE
4519 * @arg @ref LL_TIM_DMA_CC1
4520 * @arg @ref LL_TIM_DMA_CC2
4521 * @arg @ref LL_TIM_DMA_CC3
4522 * @arg @ref LL_TIM_DMA_CC4
4523 * @arg @ref LL_TIM_DMA_COM
4524 * @arg @ref LL_TIM_DMA_TRIGGER
4525 * @retval None
4526 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4527 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4528 uint32_t DMABurstSource)
4529 {
4530 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4531 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4532 }
4533
4534 /**
4535 * @}
4536 */
4537
4538 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4539 * @{
4540 */
4541
4542 /**
4543 * @brief Enable encoder index.
4544 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4545 * a timer instance provides an index input.
4546 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4547 * @param TIMx Timer instance
4548 * @retval None
4549 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4550 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4551 {
4552 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4553 }
4554
4555 /**
4556 * @brief Disable encoder index.
4557 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4558 * a timer instance provides an index input.
4559 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4560 * @param TIMx Timer instance
4561 * @retval None
4562 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4563 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4564 {
4565 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4566 }
4567
4568 /**
4569 * @brief Indicate whether encoder index is enabled.
4570 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4571 * a timer instance provides an index input.
4572 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4573 * @param TIMx Timer instance
4574 * @retval State of bit (1 or 0).
4575 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4576 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4577 {
4578 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4579 }
4580
4581 /**
4582 * @brief Set index direction
4583 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4584 * a timer instance provides an index input.
4585 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4586 * @param TIMx Timer instance
4587 * @param IndexDirection This parameter can be one of the following values:
4588 * @arg @ref LL_TIM_INDEX_UP_DOWN
4589 * @arg @ref LL_TIM_INDEX_UP
4590 * @arg @ref LL_TIM_INDEX_DOWN
4591 * @retval None
4592 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4593 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4594 {
4595 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4596 }
4597
4598 /**
4599 * @brief Get actual index direction
4600 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4601 * a timer instance provides an index input.
4602 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4603 * @param TIMx Timer instance
4604 * @retval Returned value can be one of the following values:
4605 * @arg @ref LL_TIM_INDEX_UP_DOWN
4606 * @arg @ref LL_TIM_INDEX_UP
4607 * @arg @ref LL_TIM_INDEX_DOWN
4608 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4609 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4610 {
4611 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4612 }
4613
4614 /**
4615 * @brief Set index blanking
4616 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4617 * a timer instance provides an index input.
4618 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4619 * @param TIMx Timer instance
4620 * @param Indexblanking This parameter can be one of the following values:
4621 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4622 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4623 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4624 * @retval None
4625 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4626 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4627 {
4628 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4629 }
4630
4631 /**
4632 * @brief Get actual index blanking
4633 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4634 * a timer instance provides an index input.
4635 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4636 * @param TIMx Timer instance
4637 * @retval Returned value can be one of the following values:
4638 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4639 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4640 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4641 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4642 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4643 {
4644 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4645 }
4646
4647
4648 /**
4649 * @brief Enable first index.
4650 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4651 * a timer instance provides an index input.
4652 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4653 * @param TIMx Timer instance
4654 * @retval None
4655 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4656 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4657 {
4658 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4659 }
4660
4661 /**
4662 * @brief Disable first index.
4663 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4664 * a timer instance provides an index input.
4665 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4666 * @param TIMx Timer instance
4667 * @retval None
4668 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4669 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4670 {
4671 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4672 }
4673
4674 /**
4675 * @brief Indicates whether first index is enabled.
4676 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4677 * a timer instance provides an index input.
4678 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4679 * @param TIMx Timer instance
4680 * @retval State of bit (1 or 0).
4681 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4682 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4683 {
4684 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4685 }
4686
4687 /**
4688 * @brief Set index positioning
4689 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4690 * a timer instance provides an index input.
4691 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4692 * @param TIMx Timer instance
4693 * @param IndexPositionning This parameter can be one of the following values:
4694 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4695 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4696 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4697 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4698 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4699 * @arg @ref LL_TIM_INDEX_POSITION_UP
4700 * @retval None
4701 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4702 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4703 {
4704 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4705 }
4706
4707 /**
4708 * @brief Get actual index positioning
4709 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4710 * a timer instance provides an index input.
4711 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4712 * @param TIMx Timer instance
4713 * @retval Returned value can be one of the following values:
4714 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4715 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4716 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4717 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4718 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4719 * @arg @ref LL_TIM_INDEX_POSITION_UP
4720 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4721 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4722 {
4723 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
4724 }
4725
4726 /**
4727 * @brief Configure encoder index.
4728 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4729 * a timer instance provides an index input.
4730 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
4731 * ECR IBLK LL_TIM_ConfigIDX\n
4732 * ECR FIDX LL_TIM_ConfigIDX\n
4733 * ECR IPOS LL_TIM_ConfigIDX
4734 * @param TIMx Timer instance
4735 * @param Configuration This parameter must be a combination of all the following values:
4736 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
4737 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
4738 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
4739 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
4740 * @retval None
4741 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)4742 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
4743 {
4744 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
4745 }
4746
4747 /**
4748 * @}
4749 */
4750
4751 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4752 * @{
4753 */
4754 /**
4755 * @brief Remap TIM inputs (input channel, internal/external triggers).
4756 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4757 * a some timer inputs can be remapped.
4758 * @rmtoll TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4759 * TIM9_TISEL TI1SEL LL_TIM_SetRemap\n
4760 * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n
4761 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
4762 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4763 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
4764 *
4765 * @param TIMx Timer instance
4766 * @param Remap Remap param depends on the TIMx. Description available only
4767 * in CHM version of the User Manual (not in .pdf).
4768 * Otherwise see Reference Manual description of TISEL registers.
4769 *
4770 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4771 *
4772 * TIM3: one of the following values:
4773 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
4774 * @arg @ref LL_TIM_TIM3_TI1_RMP_ETH_PPS
4775 *
4776 * TIM9: one of the following values:
4777 * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
4778 * @arg @ref LL_TIM_TIM9_TI1_RMP_MCO1
4779 * @arg @ref LL_TIM_TIM9_TI1_RMP_MCO2
4780 *
4781 * TIM12: one of the following values:
4782 * @arg @ref LL_TIM_TIM12_TI1_RMP_GPIO
4783 * @arg @ref LL_TIM_TIM12_TI1_RMP_SPDIF_FS
4784 * @arg @ref LL_TIM_TIM12_TI1_RMP_HSI_1024
4785 * @arg @ref LL_TIM_TIM12_TI1_RMP_CSI_128
4786 * @arg @ref LL_TIM_TIM12_TI1_RMP_MCO1
4787 * @arg @ref LL_TIM_TIM12_TI1_RMP_MCO2
4788 *
4789 * TIM15: any combination of TI1_RMP and TI2_RMP where
4790 *
4791 * . . TI1_RMP can be one of the following values
4792 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
4793 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_CH1
4794 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_CH1
4795 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM4_CH1
4796 * @arg @ref LL_TIM_TIM15_TI1_RMP_MCO1
4797 * @arg @ref LL_TIM_TIM15_TI1_RMP_MCO2
4798 *
4799 * . . TI2_RMP can be one of the following values
4800 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
4801 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_CH2
4802 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_CH2
4803 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM4_CH2
4804 *
4805 * TIM16: one of the following values:
4806 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4807 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WKUP
4808 *
4809 * TIM17: one of the following values:
4810 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
4811 * @arg @ref LL_TIM_TIM17_TI1_RMP_SPDIF_FS
4812 * @retval None
4813 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4814 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4815 {
4816 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4817 }
4818
4819 /**
4820 * @}
4821 */
4822
4823 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4824 * @{
4825 */
4826 /**
4827 * @brief Clear the update interrupt flag (UIF).
4828 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4829 * @param TIMx Timer instance
4830 * @retval None
4831 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)4832 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
4833 {
4834 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
4835 }
4836
4837 /**
4838 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
4839 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
4840 * @param TIMx Timer instance
4841 * @retval State of bit (1 or 0).
4842 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)4843 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
4844 {
4845 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
4846 }
4847
4848 /**
4849 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
4850 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
4851 * @param TIMx Timer instance
4852 * @retval None
4853 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)4854 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
4855 {
4856 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
4857 }
4858
4859 /**
4860 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
4861 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
4862 * @param TIMx Timer instance
4863 * @retval State of bit (1 or 0).
4864 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)4865 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
4866 {
4867 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
4868 }
4869
4870 /**
4871 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
4872 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
4873 * @param TIMx Timer instance
4874 * @retval None
4875 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)4876 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
4877 {
4878 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
4879 }
4880
4881 /**
4882 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
4883 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
4884 * @param TIMx Timer instance
4885 * @retval State of bit (1 or 0).
4886 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)4887 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
4888 {
4889 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
4890 }
4891
4892 /**
4893 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
4894 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
4895 * @param TIMx Timer instance
4896 * @retval None
4897 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)4898 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
4899 {
4900 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
4901 }
4902
4903 /**
4904 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
4905 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
4906 * @param TIMx Timer instance
4907 * @retval State of bit (1 or 0).
4908 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)4909 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
4910 {
4911 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
4912 }
4913
4914 /**
4915 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
4916 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
4917 * @param TIMx Timer instance
4918 * @retval None
4919 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)4920 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
4921 {
4922 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
4923 }
4924
4925 /**
4926 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
4927 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
4928 * @param TIMx Timer instance
4929 * @retval State of bit (1 or 0).
4930 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)4931 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
4932 {
4933 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
4934 }
4935
4936 /**
4937 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
4938 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
4939 * @param TIMx Timer instance
4940 * @retval None
4941 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)4942 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
4943 {
4944 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
4945 }
4946
4947 /**
4948 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
4949 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
4950 * @param TIMx Timer instance
4951 * @retval State of bit (1 or 0).
4952 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)4953 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
4954 {
4955 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
4956 }
4957
4958 /**
4959 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
4960 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
4961 * @param TIMx Timer instance
4962 * @retval None
4963 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)4964 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
4965 {
4966 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
4967 }
4968
4969 /**
4970 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
4971 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
4972 * @param TIMx Timer instance
4973 * @retval State of bit (1 or 0).
4974 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)4975 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
4976 {
4977 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
4978 }
4979
4980 /**
4981 * @brief Clear the commutation interrupt flag (COMIF).
4982 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
4983 * @param TIMx Timer instance
4984 * @retval None
4985 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)4986 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
4987 {
4988 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
4989 }
4990
4991 /**
4992 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
4993 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
4994 * @param TIMx Timer instance
4995 * @retval State of bit (1 or 0).
4996 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)4997 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
4998 {
4999 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5000 }
5001
5002 /**
5003 * @brief Clear the trigger interrupt flag (TIF).
5004 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5005 * @param TIMx Timer instance
5006 * @retval None
5007 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5008 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5009 {
5010 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5011 }
5012
5013 /**
5014 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5015 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5016 * @param TIMx Timer instance
5017 * @retval State of bit (1 or 0).
5018 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5019 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5020 {
5021 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5022 }
5023
5024 /**
5025 * @brief Clear the break interrupt flag (BIF).
5026 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5027 * @param TIMx Timer instance
5028 * @retval None
5029 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5030 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5031 {
5032 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5033 }
5034
5035 /**
5036 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5037 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5038 * @param TIMx Timer instance
5039 * @retval State of bit (1 or 0).
5040 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5041 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5042 {
5043 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5044 }
5045
5046 /**
5047 * @brief Clear the break 2 interrupt flag (B2IF).
5048 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5049 * @param TIMx Timer instance
5050 * @retval None
5051 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5052 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5053 {
5054 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5055 }
5056
5057 /**
5058 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5059 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5060 * @param TIMx Timer instance
5061 * @retval State of bit (1 or 0).
5062 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5063 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5064 {
5065 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5066 }
5067
5068 /**
5069 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5070 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5071 * @param TIMx Timer instance
5072 * @retval None
5073 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5074 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5075 {
5076 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5077 }
5078
5079 /**
5080 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5081 * (Capture/Compare 1 interrupt is pending).
5082 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5083 * @param TIMx Timer instance
5084 * @retval State of bit (1 or 0).
5085 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5086 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5087 {
5088 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5089 }
5090
5091 /**
5092 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5093 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5094 * @param TIMx Timer instance
5095 * @retval None
5096 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5097 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5098 {
5099 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5100 }
5101
5102 /**
5103 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5104 * (Capture/Compare 2 over-capture interrupt is pending).
5105 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5106 * @param TIMx Timer instance
5107 * @retval State of bit (1 or 0).
5108 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5109 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5110 {
5111 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5112 }
5113
5114 /**
5115 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5116 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5117 * @param TIMx Timer instance
5118 * @retval None
5119 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5120 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5121 {
5122 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5123 }
5124
5125 /**
5126 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5127 * (Capture/Compare 3 over-capture interrupt is pending).
5128 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5129 * @param TIMx Timer instance
5130 * @retval State of bit (1 or 0).
5131 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5132 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5133 {
5134 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5135 }
5136
5137 /**
5138 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5139 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5140 * @param TIMx Timer instance
5141 * @retval None
5142 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5143 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5144 {
5145 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5146 }
5147
5148 /**
5149 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5150 * (Capture/Compare 4 over-capture interrupt is pending).
5151 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5152 * @param TIMx Timer instance
5153 * @retval State of bit (1 or 0).
5154 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5155 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5156 {
5157 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5158 }
5159
5160 /**
5161 * @brief Clear the system break interrupt flag (SBIF).
5162 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5163 * @param TIMx Timer instance
5164 * @retval None
5165 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5166 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5167 {
5168 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5169 }
5170
5171 /**
5172 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5173 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5174 * @param TIMx Timer instance
5175 * @retval State of bit (1 or 0).
5176 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5177 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5178 {
5179 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5180 }
5181
5182 /**
5183 * @brief Clear the transition error interrupt flag (TERRF).
5184 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5185 * a timer instance provides encoder error management.
5186 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5187 * @param TIMx Timer instance
5188 * @retval None
5189 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5190 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5191 {
5192 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5193 }
5194
5195 /**
5196 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5197 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5198 * a timer instance provides encoder error management.
5199 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5200 * @param TIMx Timer instance
5201 * @retval State of bit (1 or 0).
5202 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5203 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5204 {
5205 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5206 }
5207
5208 /**
5209 * @brief Clear the index error interrupt flag (IERRF).
5210 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5211 * a timer instance provides encoder error management.
5212 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5213 * @param TIMx Timer instance
5214 * @retval None
5215 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5216 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5217 {
5218 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5219 }
5220
5221 /**
5222 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5223 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5224 * a timer instance provides encoder error management.
5225 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5226 * @param TIMx Timer instance
5227 * @retval State of bit (1 or 0).
5228 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5229 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5230 {
5231 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5232 }
5233
5234 /**
5235 * @brief Clear the direction change interrupt flag (DIRF).
5236 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5237 * a timer instance provides encoder interrupt management.
5238 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5239 * @param TIMx Timer instance
5240 * @retval None
5241 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5242 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5243 {
5244 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5245 }
5246
5247 /**
5248 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5249 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5250 * a timer instance provides encoder interrupt management.
5251 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5252 * @param TIMx Timer instance
5253 * @retval State of bit (1 or 0).
5254 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5255 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5256 {
5257 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5258 }
5259
5260 /**
5261 * @brief Clear the index interrupt flag (IDXF).
5262 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5263 * a timer instance provides encoder interrupt management.
5264 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5265 * @param TIMx Timer instance
5266 * @retval None
5267 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5268 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5269 {
5270 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5271 }
5272
5273 /**
5274 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5275 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5276 * a timer instance provides encoder interrupt management.
5277 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5278 * @param TIMx Timer instance
5279 * @retval State of bit (1 or 0).
5280 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5281 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5282 {
5283 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5284 }
5285 /**
5286 * @}
5287 */
5288
5289 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5290 * @{
5291 */
5292 /**
5293 * @brief Enable update interrupt (UIE).
5294 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5295 * @param TIMx Timer instance
5296 * @retval None
5297 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5298 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5299 {
5300 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5301 }
5302
5303 /**
5304 * @brief Disable update interrupt (UIE).
5305 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5306 * @param TIMx Timer instance
5307 * @retval None
5308 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5309 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5310 {
5311 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5312 }
5313
5314 /**
5315 * @brief Indicates whether the update interrupt (UIE) is enabled.
5316 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5317 * @param TIMx Timer instance
5318 * @retval State of bit (1 or 0).
5319 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5320 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5321 {
5322 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5323 }
5324
5325 /**
5326 * @brief Enable capture/compare 1 interrupt (CC1IE).
5327 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5328 * @param TIMx Timer instance
5329 * @retval None
5330 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5331 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5332 {
5333 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5334 }
5335
5336 /**
5337 * @brief Disable capture/compare 1 interrupt (CC1IE).
5338 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5339 * @param TIMx Timer instance
5340 * @retval None
5341 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5342 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5343 {
5344 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5345 }
5346
5347 /**
5348 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5349 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5350 * @param TIMx Timer instance
5351 * @retval State of bit (1 or 0).
5352 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5353 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5354 {
5355 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5356 }
5357
5358 /**
5359 * @brief Enable capture/compare 2 interrupt (CC2IE).
5360 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5361 * @param TIMx Timer instance
5362 * @retval None
5363 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5364 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5365 {
5366 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5367 }
5368
5369 /**
5370 * @brief Disable capture/compare 2 interrupt (CC2IE).
5371 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5372 * @param TIMx Timer instance
5373 * @retval None
5374 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5375 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5376 {
5377 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5378 }
5379
5380 /**
5381 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5382 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5383 * @param TIMx Timer instance
5384 * @retval State of bit (1 or 0).
5385 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5386 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5387 {
5388 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5389 }
5390
5391 /**
5392 * @brief Enable capture/compare 3 interrupt (CC3IE).
5393 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5394 * @param TIMx Timer instance
5395 * @retval None
5396 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5397 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5398 {
5399 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5400 }
5401
5402 /**
5403 * @brief Disable capture/compare 3 interrupt (CC3IE).
5404 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5405 * @param TIMx Timer instance
5406 * @retval None
5407 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5408 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5409 {
5410 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5411 }
5412
5413 /**
5414 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5415 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5416 * @param TIMx Timer instance
5417 * @retval State of bit (1 or 0).
5418 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5419 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5420 {
5421 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5422 }
5423
5424 /**
5425 * @brief Enable capture/compare 4 interrupt (CC4IE).
5426 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5427 * @param TIMx Timer instance
5428 * @retval None
5429 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5430 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5431 {
5432 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5433 }
5434
5435 /**
5436 * @brief Disable capture/compare 4 interrupt (CC4IE).
5437 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5438 * @param TIMx Timer instance
5439 * @retval None
5440 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5441 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5442 {
5443 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5444 }
5445
5446 /**
5447 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5448 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5449 * @param TIMx Timer instance
5450 * @retval State of bit (1 or 0).
5451 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5452 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5453 {
5454 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5455 }
5456
5457 /**
5458 * @brief Enable commutation interrupt (COMIE).
5459 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5460 * @param TIMx Timer instance
5461 * @retval None
5462 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5463 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5464 {
5465 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5466 }
5467
5468 /**
5469 * @brief Disable commutation interrupt (COMIE).
5470 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5471 * @param TIMx Timer instance
5472 * @retval None
5473 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5474 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5475 {
5476 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5477 }
5478
5479 /**
5480 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5481 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5482 * @param TIMx Timer instance
5483 * @retval State of bit (1 or 0).
5484 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5485 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5486 {
5487 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5488 }
5489
5490 /**
5491 * @brief Enable trigger interrupt (TIE).
5492 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5493 * @param TIMx Timer instance
5494 * @retval None
5495 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5496 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5497 {
5498 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5499 }
5500
5501 /**
5502 * @brief Disable trigger interrupt (TIE).
5503 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5504 * @param TIMx Timer instance
5505 * @retval None
5506 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5507 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5508 {
5509 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5510 }
5511
5512 /**
5513 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5514 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5515 * @param TIMx Timer instance
5516 * @retval State of bit (1 or 0).
5517 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5518 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5519 {
5520 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5521 }
5522
5523 /**
5524 * @brief Enable break interrupt (BIE).
5525 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5526 * @param TIMx Timer instance
5527 * @retval None
5528 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5529 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5530 {
5531 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5532 }
5533
5534 /**
5535 * @brief Disable break interrupt (BIE).
5536 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5537 * @param TIMx Timer instance
5538 * @retval None
5539 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5540 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5541 {
5542 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5543 }
5544
5545 /**
5546 * @brief Indicates whether the break interrupt (BIE) is enabled.
5547 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5548 * @param TIMx Timer instance
5549 * @retval State of bit (1 or 0).
5550 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5551 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5552 {
5553 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5554 }
5555
5556 /**
5557 * @brief Enable transition error interrupt (TERRIE).
5558 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5559 * a timer instance provides encoder error management.
5560 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5561 * @param TIMx Timer instance
5562 * @retval None
5563 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5564 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5565 {
5566 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5567 }
5568
5569 /**
5570 * @brief Disable transition error interrupt (TERRIE).
5571 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5572 * a timer instance provides encoder error management.
5573 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5574 * @param TIMx Timer instance
5575 * @retval None
5576 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5577 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5578 {
5579 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5580 }
5581
5582 /**
5583 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5584 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5585 * a timer instance provides encoder error management.
5586 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5587 * @param TIMx Timer instance
5588 * @retval State of bit (1 or 0).
5589 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5590 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5591 {
5592 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5593 }
5594
5595 /**
5596 * @brief Enable index error interrupt (IERRIE).
5597 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5598 * a timer instance provides encoder error management.
5599 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5600 * @param TIMx Timer instance
5601 * @retval None
5602 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5603 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5604 {
5605 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5606 }
5607
5608 /**
5609 * @brief Disable index error interrupt (IERRIE).
5610 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5611 * a timer instance provides encoder error management.
5612 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
5613 * @param TIMx Timer instance
5614 * @retval None
5615 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)5616 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
5617 {
5618 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5619 }
5620
5621 /**
5622 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
5623 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5624 * a timer instance provides encoder error management.
5625 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
5626 * @param TIMx Timer instance
5627 * @retval State of bit (1 or 0).
5628 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)5629 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
5630 {
5631 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
5632 }
5633
5634 /**
5635 * @brief Enable direction change interrupt (DIRIE).
5636 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5637 * a timer instance provides encoder interrupt management.
5638 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
5639 * @param TIMx Timer instance
5640 * @retval None
5641 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)5642 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
5643 {
5644 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5645 }
5646
5647 /**
5648 * @brief Disable direction change interrupt (DIRIE).
5649 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5650 * a timer instance provides encoder interrupt management.
5651 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
5652 * @param TIMx Timer instance
5653 * @retval None
5654 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)5655 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
5656 {
5657 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5658 }
5659
5660 /**
5661 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
5662 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5663 * a timer instance provides encoder interrupt management.
5664 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
5665 * @param TIMx Timer instance
5666 * @retval State of bit (1 or 0).
5667 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)5668 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
5669 {
5670 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
5671 }
5672
5673 /**
5674 * @brief Enable index interrupt (IDXIE).
5675 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5676 * a timer instance provides encoder interrupt management.
5677 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
5678 * @param TIMx Timer instance
5679 * @retval None
5680 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)5681 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
5682 {
5683 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5684 }
5685
5686 /**
5687 * @brief Disable index interrupt (IDXIE).
5688 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5689 * a timer instance provides encoder interrupt management.
5690 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
5691 * @param TIMx Timer instance
5692 * @retval None
5693 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)5694 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
5695 {
5696 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5697 }
5698
5699 /**
5700 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
5701 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5702 * a timer instance provides encoder interrupt management.
5703 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
5704 * @param TIMx Timer instance
5705 * @retval State of bit (1 or 0).
5706 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)5707 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
5708 {
5709 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
5710 }
5711
5712 /**
5713 * @}
5714 */
5715
5716 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
5717 * @{
5718 */
5719 /**
5720 * @brief Enable update DMA request (UDE).
5721 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
5722 * @param TIMx Timer instance
5723 * @retval None
5724 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)5725 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5726 {
5727 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
5728 }
5729
5730 /**
5731 * @brief Disable update DMA request (UDE).
5732 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
5733 * @param TIMx Timer instance
5734 * @retval None
5735 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)5736 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5737 {
5738 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
5739 }
5740
5741 /**
5742 * @brief Indicates whether the update DMA request (UDE) is enabled.
5743 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
5744 * @param TIMx Timer instance
5745 * @retval State of bit (1 or 0).
5746 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)5747 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
5748 {
5749 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
5750 }
5751
5752 /**
5753 * @brief Enable capture/compare 1 DMA request (CC1DE).
5754 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
5755 * @param TIMx Timer instance
5756 * @retval None
5757 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)5758 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
5759 {
5760 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5761 }
5762
5763 /**
5764 * @brief Disable capture/compare 1 DMA request (CC1DE).
5765 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
5766 * @param TIMx Timer instance
5767 * @retval None
5768 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)5769 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
5770 {
5771 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5772 }
5773
5774 /**
5775 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
5776 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
5777 * @param TIMx Timer instance
5778 * @retval State of bit (1 or 0).
5779 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)5780 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
5781 {
5782 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
5783 }
5784
5785 /**
5786 * @brief Enable capture/compare 2 DMA request (CC2DE).
5787 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
5788 * @param TIMx Timer instance
5789 * @retval None
5790 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)5791 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
5792 {
5793 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5794 }
5795
5796 /**
5797 * @brief Disable capture/compare 2 DMA request (CC2DE).
5798 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
5799 * @param TIMx Timer instance
5800 * @retval None
5801 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)5802 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
5803 {
5804 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5805 }
5806
5807 /**
5808 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
5809 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
5810 * @param TIMx Timer instance
5811 * @retval State of bit (1 or 0).
5812 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)5813 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
5814 {
5815 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
5816 }
5817
5818 /**
5819 * @brief Enable capture/compare 3 DMA request (CC3DE).
5820 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
5821 * @param TIMx Timer instance
5822 * @retval None
5823 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)5824 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
5825 {
5826 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5827 }
5828
5829 /**
5830 * @brief Disable capture/compare 3 DMA request (CC3DE).
5831 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
5832 * @param TIMx Timer instance
5833 * @retval None
5834 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)5835 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
5836 {
5837 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5838 }
5839
5840 /**
5841 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
5842 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
5843 * @param TIMx Timer instance
5844 * @retval State of bit (1 or 0).
5845 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)5846 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
5847 {
5848 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
5849 }
5850
5851 /**
5852 * @brief Enable capture/compare 4 DMA request (CC4DE).
5853 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
5854 * @param TIMx Timer instance
5855 * @retval None
5856 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)5857 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
5858 {
5859 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5860 }
5861
5862 /**
5863 * @brief Disable capture/compare 4 DMA request (CC4DE).
5864 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
5865 * @param TIMx Timer instance
5866 * @retval None
5867 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)5868 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
5869 {
5870 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
5871 }
5872
5873 /**
5874 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
5875 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
5876 * @param TIMx Timer instance
5877 * @retval State of bit (1 or 0).
5878 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)5879 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
5880 {
5881 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
5882 }
5883
5884 /**
5885 * @brief Enable commutation DMA request (COMDE).
5886 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
5887 * @param TIMx Timer instance
5888 * @retval None
5889 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)5890 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
5891 {
5892 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
5893 }
5894
5895 /**
5896 * @brief Disable commutation DMA request (COMDE).
5897 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
5898 * @param TIMx Timer instance
5899 * @retval None
5900 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)5901 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
5902 {
5903 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
5904 }
5905
5906 /**
5907 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
5908 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
5909 * @param TIMx Timer instance
5910 * @retval State of bit (1 or 0).
5911 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)5912 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
5913 {
5914 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
5915 }
5916
5917 /**
5918 * @brief Enable trigger interrupt (TDE).
5919 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
5920 * @param TIMx Timer instance
5921 * @retval None
5922 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)5923 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
5924 {
5925 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
5926 }
5927
5928 /**
5929 * @brief Disable trigger interrupt (TDE).
5930 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
5931 * @param TIMx Timer instance
5932 * @retval None
5933 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)5934 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
5935 {
5936 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
5937 }
5938
5939 /**
5940 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
5941 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
5942 * @param TIMx Timer instance
5943 * @retval State of bit (1 or 0).
5944 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)5945 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
5946 {
5947 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
5948 }
5949
5950 /**
5951 * @}
5952 */
5953
5954 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
5955 * @{
5956 */
5957 /**
5958 * @brief Generate an update event.
5959 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
5960 * @param TIMx Timer instance
5961 * @retval None
5962 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)5963 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
5964 {
5965 SET_BIT(TIMx->EGR, TIM_EGR_UG);
5966 }
5967
5968 /**
5969 * @brief Generate Capture/Compare 1 event.
5970 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
5971 * @param TIMx Timer instance
5972 * @retval None
5973 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)5974 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
5975 {
5976 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
5977 }
5978
5979 /**
5980 * @brief Generate Capture/Compare 2 event.
5981 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
5982 * @param TIMx Timer instance
5983 * @retval None
5984 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)5985 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
5986 {
5987 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
5988 }
5989
5990 /**
5991 * @brief Generate Capture/Compare 3 event.
5992 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
5993 * @param TIMx Timer instance
5994 * @retval None
5995 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)5996 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
5997 {
5998 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
5999 }
6000
6001 /**
6002 * @brief Generate Capture/Compare 4 event.
6003 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6004 * @param TIMx Timer instance
6005 * @retval None
6006 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6007 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6008 {
6009 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6010 }
6011
6012 /**
6013 * @brief Generate commutation event.
6014 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6015 * @param TIMx Timer instance
6016 * @retval None
6017 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6018 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6019 {
6020 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6021 }
6022
6023 /**
6024 * @brief Generate trigger event.
6025 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6026 * @param TIMx Timer instance
6027 * @retval None
6028 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6029 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6030 {
6031 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6032 }
6033
6034 /**
6035 * @brief Generate break event.
6036 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6037 * @param TIMx Timer instance
6038 * @retval None
6039 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6040 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6041 {
6042 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6043 }
6044
6045 /**
6046 * @brief Generate break 2 event.
6047 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6048 * @param TIMx Timer instance
6049 * @retval None
6050 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6051 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6052 {
6053 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6054 }
6055
6056 /**
6057 * @}
6058 */
6059
6060 #if defined(USE_FULL_LL_DRIVER)
6061 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6062 * @{
6063 */
6064
6065 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6066 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6067 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6068 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6069 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6070 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6071 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6072 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6073 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6074 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6075 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6076 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6077 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6078 /**
6079 * @}
6080 */
6081 #endif /* USE_FULL_LL_DRIVER */
6082
6083 /**
6084 * @}
6085 */
6086
6087 /**
6088 * @}
6089 */
6090
6091 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM9 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
6092
6093 /**
6094 * @}
6095 */
6096
6097 #ifdef __cplusplus
6098 }
6099 #endif
6100
6101 #endif /* __STM32H7RSxx_LL_TIM_H */
6102
