1 /**
2 ******************************************************************************
3 * @file stm32u5xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32U5xx_LL_TIM_H
21 #define __STM32U5xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32u5xx.h"
29
30 /** @addtogroup STM32U5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM15) \
43 || defined (TIM16) \
44 || defined (TIM17) \
45 || defined (TIM20)
46
47 /** @defgroup TIM_LL TIM
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
54 * @{
55 */
56 static const uint8_t OFFSET_TAB_CCMRx[] =
57 {
58 0x00U, /* 0: TIMx_CH1 */
59 0x00U, /* 1: TIMx_CH1N */
60 0x00U, /* 2: TIMx_CH2 */
61 0x00U, /* 3: TIMx_CH2N */
62 0x04U, /* 4: TIMx_CH3 */
63 0x04U, /* 5: TIMx_CH3N */
64 0x04U, /* 6: TIMx_CH4 */
65 0x04U, /* 7: TIMx_CH4N */
66 0x38U, /* 8: TIMx_CH5 */
67 0x38U /* 9: TIMx_CH6 */
68
69 };
70
71 static const uint8_t SHIFT_TAB_OCxx[] =
72 {
73 0U, /* 0: OC1M, OC1FE, OC1PE */
74 0U, /* 1: - NA */
75 8U, /* 2: OC2M, OC2FE, OC2PE */
76 0U, /* 3: - NA */
77 0U, /* 4: OC3M, OC3FE, OC3PE */
78 0U, /* 5: - NA */
79 8U, /* 6: OC4M, OC4FE, OC4PE */
80 0U, /* 7: - NA */
81 0U, /* 8: OC5M, OC5FE, OC5PE */
82 8U /* 9: OC6M, OC6FE, OC6PE */
83 };
84
85 static const uint8_t SHIFT_TAB_ICxx[] =
86 {
87 0U, /* 0: CC1S, IC1PSC, IC1F */
88 0U, /* 1: - NA */
89 8U, /* 2: CC2S, IC2PSC, IC2F */
90 0U, /* 3: - NA */
91 0U, /* 4: CC3S, IC3PSC, IC3F */
92 0U, /* 5: - NA */
93 8U, /* 6: CC4S, IC4PSC, IC4F */
94 0U, /* 7: - NA */
95 0U, /* 8: - NA */
96 0U /* 9: - NA */
97 };
98
99 static const uint8_t SHIFT_TAB_CCxP[] =
100 {
101 0U, /* 0: CC1P */
102 2U, /* 1: CC1NP */
103 4U, /* 2: CC2P */
104 6U, /* 3: CC2NP */
105 8U, /* 4: CC3P */
106 10U, /* 5: CC3NP */
107 12U, /* 6: CC4P */
108 14U, /* 7: CC4NP */
109 16U, /* 8: CC5P */
110 20U /* 9: CC6P */
111 };
112
113 static const uint8_t SHIFT_TAB_OISx[] =
114 {
115 0U, /* 0: OIS1 */
116 1U, /* 1: OIS1N */
117 2U, /* 2: OIS2 */
118 3U, /* 3: OIS2N */
119 4U, /* 4: OIS3 */
120 5U, /* 5: OIS3N */
121 6U, /* 6: OIS4 */
122 7U, /* 7: OIS4N */
123 8U, /* 8: OIS5 */
124 10U /* 9: OIS6 */
125 };
126 /**
127 * @}
128 */
129
130 /* Private constants ---------------------------------------------------------*/
131 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
132 * @{
133 */
134
135 /* Defines used for the bit position in the register and perform offsets */
136 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
137
138 /* Generic bit definitions for TIMx_AF1 register */
139 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
140 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
141
142
143 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
144 #define DT_DELAY_1 ((uint8_t)0x7F)
145 #define DT_DELAY_2 ((uint8_t)0x3F)
146 #define DT_DELAY_3 ((uint8_t)0x1F)
147 #define DT_DELAY_4 ((uint8_t)0x1F)
148
149 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
150 #define DT_RANGE_1 ((uint8_t)0x00)
151 #define DT_RANGE_2 ((uint8_t)0x80)
152 #define DT_RANGE_3 ((uint8_t)0xC0)
153 #define DT_RANGE_4 ((uint8_t)0xE0)
154
155 /** Legacy definitions for compatibility purpose
156 @cond 0
157 */
158 /**
159 @endcond
160 */
161
162 #define OCREF_CLEAR_SELECT_POS (28U)
163 #define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */
164 /**
165 * @}
166 */
167
168 /* Private macros ------------------------------------------------------------*/
169 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
170 * @{
171 */
172 /** @brief Convert channel id into channel index.
173 * @param __CHANNEL__ This parameter can be one of the following values:
174 * @arg @ref LL_TIM_CHANNEL_CH1
175 * @arg @ref LL_TIM_CHANNEL_CH1N
176 * @arg @ref LL_TIM_CHANNEL_CH2
177 * @arg @ref LL_TIM_CHANNEL_CH2N
178 * @arg @ref LL_TIM_CHANNEL_CH3
179 * @arg @ref LL_TIM_CHANNEL_CH3N
180 * @arg @ref LL_TIM_CHANNEL_CH4
181 * @arg @ref LL_TIM_CHANNEL_CH4N
182 * @arg @ref LL_TIM_CHANNEL_CH5
183 * @arg @ref LL_TIM_CHANNEL_CH6
184 * @retval none
185 */
186 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
187 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
189 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
196
197 /** @brief Calculate the deadtime sampling period(in ps).
198 * @param __TIMCLK__ timer input clock frequency (in Hz).
199 * @param __CKD__ This parameter can be one of the following values:
200 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
201 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
203 * @retval none
204 */
205 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
206 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
207 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
208 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
209 /**
210 * @}
211 */
212
213
214 /* Exported types ------------------------------------------------------------*/
215 #if defined(USE_FULL_LL_DRIVER)
216 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
217 * @{
218 */
219
220 /**
221 * @brief TIM Time Base configuration structure definition.
222 */
223 typedef struct
224 {
225 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
226 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
227
228 This feature can be modified afterwards using unitary function
229 @ref LL_TIM_SetPrescaler().*/
230
231 uint32_t CounterMode; /*!< Specifies the counter mode.
232 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_SetCounterMode().*/
236
237 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
238 Auto-Reload Register at the next update event.
239 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
240 Some timer instances may support 32 bits counters. In that case this parameter must
241 be a number between 0x0000 and 0xFFFFFFFF.
242
243 This feature can be modified afterwards using unitary function
244 @ref LL_TIM_SetAutoReload().*/
245
246 uint32_t ClockDivision; /*!< Specifies the clock division.
247 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
248
249 This feature can be modified afterwards using unitary function
250 @ref LL_TIM_SetClockDivision().*/
251
252 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
253 reaches zero, an update event is generated and counting restarts
254 from the RCR value (N).
255 This means in PWM mode that (N+1) corresponds to:
256 - the number of PWM periods in edge-aligned mode
257 - the number of half PWM period in center-aligned mode
258 GP timers: this parameter must be a number between Min_Data = 0x00 and
259 Max_Data = 0xFF.
260 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
261 Max_Data = 0xFFFF.
262
263 This feature can be modified afterwards using unitary function
264 @ref LL_TIM_SetRepetitionCounter().*/
265 } LL_TIM_InitTypeDef;
266
267 /**
268 * @brief TIM Output Compare configuration structure definition.
269 */
270 typedef struct
271 {
272 uint32_t OCMode; /*!< Specifies the output mode.
273 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
274
275 This feature can be modified afterwards using unitary function
276 @ref LL_TIM_OC_SetMode().*/
277
278 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
279 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
280
281 This feature can be modified afterwards using unitary functions
282 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
283
284 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
285 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
286
287 This feature can be modified afterwards using unitary functions
288 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
289
290 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
291 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
292
293 This feature can be modified afterwards using unitary function
294 LL_TIM_OC_SetCompareCHx (x=1..6).*/
295
296 uint32_t OCPolarity; /*!< Specifies the output polarity.
297 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetPolarity().*/
301
302 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
303 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
304
305 This feature can be modified afterwards using unitary function
306 @ref LL_TIM_OC_SetPolarity().*/
307
308
309 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
310 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
311
312 This feature can be modified afterwards using unitary function
313 @ref LL_TIM_OC_SetIdleState().*/
314
315 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
316 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
317
318 This feature can be modified afterwards using unitary function
319 @ref LL_TIM_OC_SetIdleState().*/
320 } LL_TIM_OC_InitTypeDef;
321
322 /**
323 * @brief TIM Input Capture configuration structure definition.
324 */
325
326 typedef struct
327 {
328
329 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
330 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
331
332 This feature can be modified afterwards using unitary function
333 @ref LL_TIM_IC_SetPolarity().*/
334
335 uint32_t ICActiveInput; /*!< Specifies the input.
336 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
337
338 This feature can be modified afterwards using unitary function
339 @ref LL_TIM_IC_SetActiveInput().*/
340
341 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
342 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
343
344 This feature can be modified afterwards using unitary function
345 @ref LL_TIM_IC_SetPrescaler().*/
346
347 uint32_t ICFilter; /*!< Specifies the input capture filter.
348 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_IC_SetFilter().*/
352 } LL_TIM_IC_InitTypeDef;
353
354
355 /**
356 * @brief TIM Encoder interface configuration structure definition.
357 */
358 typedef struct
359 {
360 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
361 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
362
363 This feature can be modified afterwards using unitary function
364 @ref LL_TIM_SetEncoderMode().*/
365
366 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
367 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
368
369 This feature can be modified afterwards using unitary function
370 @ref LL_TIM_IC_SetPolarity().*/
371
372 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
373 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
374
375 This feature can be modified afterwards using unitary function
376 @ref LL_TIM_IC_SetActiveInput().*/
377
378 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
379 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
380
381 This feature can be modified afterwards using unitary function
382 @ref LL_TIM_IC_SetPrescaler().*/
383
384 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
385 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
386
387 This feature can be modified afterwards using unitary function
388 @ref LL_TIM_IC_SetFilter().*/
389
390 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
391 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetPolarity().*/
395
396 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
397 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetActiveInput().*/
401
402 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
403 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
404
405 This feature can be modified afterwards using unitary function
406 @ref LL_TIM_IC_SetPrescaler().*/
407
408 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
409 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
410
411 This feature can be modified afterwards using unitary function
412 @ref LL_TIM_IC_SetFilter().*/
413
414 } LL_TIM_ENCODER_InitTypeDef;
415
416 /**
417 * @brief TIM Hall sensor interface configuration structure definition.
418 */
419 typedef struct
420 {
421
422 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
423 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
424
425 This feature can be modified afterwards using unitary function
426 @ref LL_TIM_IC_SetPolarity().*/
427
428 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
429 Prescaler must be set to get a maximum counter period longer than the
430 time interval between 2 consecutive changes on the Hall inputs.
431 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
432
433 This feature can be modified afterwards using unitary function
434 @ref LL_TIM_IC_SetPrescaler().*/
435
436 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
437 This parameter can be a value of
438 @ref TIM_LL_EC_IC_FILTER.
439
440 This feature can be modified afterwards using unitary function
441 @ref LL_TIM_IC_SetFilter().*/
442
443 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
444 A positive pulse (TRGO event) is generated with a programmable delay every time
445 a change occurs on the Hall inputs.
446 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
447
448 This feature can be modified afterwards using unitary function
449 @ref LL_TIM_OC_SetCompareCH2().*/
450 } LL_TIM_HALLSENSOR_InitTypeDef;
451
452 /**
453 * @brief BDTR (Break and Dead Time) structure definition
454 */
455 typedef struct
456 {
457 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
458 This parameter can be a value of @ref TIM_LL_EC_OSSR
459
460 This feature can be modified afterwards using unitary function
461 @ref LL_TIM_SetOffStates()
462
463 @note This bit-field cannot be modified as long as LOCK level 2 has been
464 programmed. */
465
466 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
467 This parameter can be a value of @ref TIM_LL_EC_OSSI
468
469 This feature can be modified afterwards using unitary function
470 @ref LL_TIM_SetOffStates()
471
472 @note This bit-field cannot be modified as long as LOCK level 2 has been
473 programmed. */
474
475 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
476 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
477
478 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
479 register has been written, their content is frozen until the next reset.*/
480
481 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
482 switching-on of the outputs.
483 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
484
485 This feature can be modified afterwards using unitary function
486 @ref LL_TIM_OC_SetDeadTime()
487
488 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
489 programmed. */
490
491 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
492 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
493
494 This feature can be modified afterwards using unitary functions
495 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
496
497 @note This bit-field can not be modified as long as LOCK level 1 has been
498 programmed. */
499
500 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
501 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
502
503 This feature can be modified afterwards using unitary function
504 @ref LL_TIM_ConfigBRK()
505
506 @note This bit-field can not be modified as long as LOCK level 1 has been
507 programmed. */
508
509 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
510 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
511
512 This feature can be modified afterwards using unitary function
513 @ref LL_TIM_ConfigBRK()
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_ConfigBRK()
523
524 @note Bidirectional break input is only supported by advanced timers instances.
525
526 @note This bit-field can not be modified as long as LOCK level 1 has been
527 programmed. */
528
529 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
530 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
531
532 This feature can be modified afterwards using unitary functions
533 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
534
535 @note This bit-field can not be modified as long as LOCK level 1 has been
536 programmed. */
537
538 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
539 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
540
541 This feature can be modified afterwards using unitary function
542 @ref LL_TIM_ConfigBRK2()
543
544 @note This bit-field can not be modified as long as LOCK level 1 has been
545 programmed. */
546
547 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
548 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
549
550 This feature can be modified afterwards using unitary function
551 @ref LL_TIM_ConfigBRK2()
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
557 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_ConfigBRK2()
561
562 @note Bidirectional break input is only supported by advanced timers instances.
563
564 @note This bit-field can not be modified as long as LOCK level 1 has been
565 programmed. */
566
567 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
568 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
569
570 This feature can be modified afterwards using unitary functions
571 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
572
573 @note This bit-field can not be modified as long as LOCK level 1 has been
574 programmed. */
575 } LL_TIM_BDTR_InitTypeDef;
576
577 /**
578 * @}
579 */
580 #endif /* USE_FULL_LL_DRIVER */
581
582 /* Exported constants --------------------------------------------------------*/
583 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
584 * @{
585 */
586
587 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
588 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
589 * @{
590 */
591 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
592 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
593 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
594 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
595 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
596 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
597 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
598 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
599 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
600 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
601 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
602 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
603 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
604 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
605 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
606 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
607 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
608 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
609 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
610 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
611 /**
612 * @}
613 */
614
615 #if defined(USE_FULL_LL_DRIVER)
616 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
617 * @{
618 */
619 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
620 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
621 /**
622 * @}
623 */
624
625 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
626 * @{
627 */
628 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
629 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
635 * @{
636 */
637 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
638 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
639 /**
640 * @}
641 */
642 #endif /* USE_FULL_LL_DRIVER */
643
644 /** @defgroup TIM_LL_EC_IT IT Defines
645 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
646 * @{
647 */
648 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
649 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
650 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
651 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
652 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
653 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
654 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
655 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
656 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
657 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
658 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
659 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
665 * @{
666 */
667 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
668 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
669 /**
670 * @}
671 */
672
673 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
674 * @{
675 */
676 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
677 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
683 * @{
684 */
685 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
686 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
687 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
688 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
689 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
690 /**
691 * @}
692 */
693
694 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
695 * @{
696 */
697 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
698 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
699 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
705 * @{
706 */
707 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
708 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
714 * @{
715 */
716 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
717 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
718 /**
719 * @}
720 */
721
722 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
723 * @{
724 */
725 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
726 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
732 * @{
733 */
734 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
735 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
736 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
737 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
738 /**
739 * @}
740 */
741
742 /** @defgroup TIM_LL_EC_CHANNEL Channel
743 * @{
744 */
745 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
746 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
747 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
748 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
749 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
750 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
751 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
752 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
753 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
754 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
755 /**
756 * @}
757 */
758
759 #if defined(USE_FULL_LL_DRIVER)
760 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
761 * @{
762 */
763 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
764 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
765 /**
766 * @}
767 */
768 #endif /* USE_FULL_LL_DRIVER */
769
770 /** Legacy definitions for compatibility purpose
771 @cond 0
772 */
773 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
774 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
775 /**
776 @endcond
777 */
778
779 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
780 * @{
781 */
782 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
783 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
784 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
785 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
786 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
787 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
788 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
789 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
790 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
791 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
792 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
793 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
794 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
795 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
796 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
797 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
803 * @{
804 */
805 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
806 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
812 * @{
813 */
814 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
815 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
821 * @{
822 */
823 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
824 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
825 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
826 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
827 /**
828 * @}
829 */
830
831 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
832 * @{
833 */
834 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
835 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
836 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
837 /**
838 * @}
839 */
840
841 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
842 * @{
843 */
844 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
845 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
846 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
847 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
848 /**
849 * @}
850 */
851
852 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
853 * @{
854 */
855 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
856 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
857 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
858 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
859 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
860 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
861 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
862 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
863 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
864 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
865 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
866 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
867 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
868 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
869 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
870 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
876 * @{
877 */
878 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
879 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
880 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
881 /**
882 * @}
883 */
884
885 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
886 * @{
887 */
888 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
889 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
890 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
891 /**
892 * @}
893 */
894
895 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
896 * @{
897 */
898 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
899 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
900 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
901 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
902 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
903 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
904 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
905 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
906 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
907 /**
908 * @}
909 */
910
911 /** @defgroup TIM_LL_EC_TRGO Trigger Output
912 * @{
913 */
914 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
915 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
916 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
917 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
918 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
919 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
920 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
921 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
922 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
923 /**
924 * @}
925 */
926
927 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
928 * @{
929 */
930 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
931 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
932 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
933 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
934 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
935 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
936 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
937 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
938 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
939 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
940 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
941 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
942 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
943 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
944 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
945 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
946 /**
947 * @}
948 */
949
950 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
951 * @{
952 */
953 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
954 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
955 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
956 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
957 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
958 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
959 the counter are controlled. */
960 /**
961 * @}
962 */
963
964 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
965 * @{
966 */
967 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
968 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
969 /**
970 * @}
971 */
972
973 /** @defgroup TIM_LL_EC_TS Trigger Selection
974 * @{
975 */
976 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
977 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
978 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
979 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
980 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
981 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
982 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
983 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
984 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
985 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
986 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
987 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
988 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
989 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
990 /**
991 * @}
992 */
993
994 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
995 * @{
996 */
997 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
998 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
999 /**
1000 * @}
1001 */
1002
1003 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
1004 * @{
1005 */
1006 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
1007 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
1008 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1009 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1010 /**
1011 * @}
1012 */
1013
1014 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1015 * @{
1016 */
1017 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1018 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1019 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1020 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1021 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1022 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1023 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1024 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1025 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1026 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1027 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1028 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1029 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1030 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1031 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1032 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1033 /**
1034 * @}
1035 */
1036
1037 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1038 * @{
1039 */
1040 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1041 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1042 #if defined(COMP2)
1043 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1044 #endif /* COMP2 */
1045 #define LL_TIM_TIM1_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
1046 #define LL_TIM_TIM1_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1047 #define LL_TIM_TIM1_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
1048 #if defined(ADC2)
1049 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 2 */
1050 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
1051 #endif /* ADC2 */
1052 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
1053 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
1054 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
1055 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1056 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1057 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1058 #if defined(ADC2)
1059 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 1 */
1060 #endif /* ADC2 */
1061 /**
1062 * @}
1063 */
1064
1065 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1066 * @{
1067 */
1068 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1069 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1070 #if defined(COMP2)
1071 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1072 #endif /* COMP2 */
1073 #define LL_TIM_TIM2_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
1074 #define LL_TIM_TIM2_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1075 #define LL_TIM_TIM2_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
1076 #if defined(DCMI) && defined(LTDC)
1077 #define LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
1078 #define LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
1079 #endif /* DCMI && LTDC */
1080 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1081 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1082 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
1083 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1084 #if defined(DSI)
1085 #define LL_TIM_TIM2_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to DSI_TE */
1086 #endif /* DSI */
1087 #if defined(DCMI) && defined(LTDC)
1088 #define LL_TIM_TIM2_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
1089 #define LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
1090 #endif /* DCMI && LTDC */
1091 /**
1092 * @}
1093 */
1094
1095 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1096 * @{
1097 */
1098 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1099 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1100 #if defined(COMP2)
1101 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1102 #endif /* COMP2 */
1103 #define LL_TIM_TIM3_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
1104 #define LL_TIM_TIM3_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1105 #define LL_TIM_TIM3_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
1106 #if defined(DCMI) && defined(LTDC)
1107 #define LL_TIM_TIM3_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
1108 #define LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
1109 #endif /* DCMI && LTDC */
1110 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1111 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1112 #if defined(DSI)
1113 #define LL_TIM_TIM3_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DSI_TE */
1114 #endif /* DSI */
1115 #define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
1116 #define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC1 analog watchdog 2 */
1117 #define LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
1118 #if defined(DCMI) && defined(LTDC)
1119 #define LL_TIM_TIM3_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
1120 #define LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
1121 #endif /* DCMI && LTDC */
1122 /**
1123 * @}
1124 */
1125
1126 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1127 * @{
1128 */
1129 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1130 #define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1131 #if defined(COMP2)
1132 #define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1133 #endif /* COMP2 */
1134 #define LL_TIM_TIM4_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
1135 #define LL_TIM_TIM4_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1136 #define LL_TIM_TIM4_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
1137 #if defined(DCMI) && defined(LTDC)
1138 #define LL_TIM_TIM4_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
1139 #define LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
1140 #endif /* DCMI && LTDC */
1141 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1142 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1143 #if defined(DSI)
1144 #define LL_TIM_TIM4_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DSI_TE */
1145 #endif /* DSI */
1146 #if defined(ADC2)
1147 #define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD1 */
1148 #define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ETR input is connected to ADC2 AWD2 */
1149 #define LL_TIM_TIM4_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD3 */
1150 #endif /* ADC2 */
1151 #if defined(DCMI) && defined(LTDC)
1152 #define LL_TIM_TIM4_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
1153 #define LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
1154 #endif /* DCMI && LTDC */
1155 /**
1156 * @}
1157 */
1158
1159 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1160 * @{
1161 */
1162 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1163 #define LL_TIM_TIM5_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1164 #if defined(COMP2)
1165 #define LL_TIM_TIM5_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1166 #endif /* COMP2 */
1167 #define LL_TIM_TIM5_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
1168 #define LL_TIM_TIM5_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1169 #define LL_TIM_TIM5_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
1170 #if defined(DCMI) && defined(LTDC)
1171 #define LL_TIM_TIM5_ETRSOURCE_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI VSYNC */
1172 #define LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC_VSYNC */
1173 #endif /* DCMI && LTDC */
1174 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1175 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1176 #if defined(DSI)
1177 #define LL_TIM_TIM5_ETRSOURCE_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DSI_TE */
1178 #endif /* DSI */
1179 #if defined(DCMI) && defined(LTDC)
1180 #define LL_TIM_TIM5_ETRSOURCE_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to DCMI HSYNC */
1181 #define LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LTDC HSYNC */
1182 #endif /* DCMI && LTDC */
1183 /**
1184 * @}
1185 */
1186
1187 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1188 * @{
1189 */
1190 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1191 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1192 #if defined(COMP2)
1193 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1194 #endif /* COMP2 */
1195 #define LL_TIM_TIM8_ETRSOURCE_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIK */
1196 #define LL_TIM_TIM8_ETRSOURCE_HSI TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to HSI */
1197 #define LL_TIM_TIM8_ETRSOURCE_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to MSIS */
1198 #if defined (ADC2)
1199 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 AWD2 */
1200 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to ADC2 AWD3 */
1201 #endif /* ADC2 */
1202 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
1203 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
1204 #define LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
1205 #define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1206 #define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1207 #define LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1208 #if defined (ADC2)
1209 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ADC2 AWD1 */
1210 #endif /* ADC2 */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1216 * @{
1217 */
1218 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1219 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1225 * @{
1226 */
1227 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1228 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1229 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1230 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1231 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1232 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1233 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1234 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1235 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1236 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1237 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1238 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1239 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1240 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1241 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1242 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1243 /**
1244 * @}
1245 */
1246
1247 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1248 * @{
1249 */
1250 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1251 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1257 * @{
1258 */
1259 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1260 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1261 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1262 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1263 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1264 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1265 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1266 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1267 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1268 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1269 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1270 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1271 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1272 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1273 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1274 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup TIM_LL_EC_OSSI OSSI
1280 * @{
1281 */
1282 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1283 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1284 /**
1285 * @}
1286 */
1287
1288 /** @defgroup TIM_LL_EC_OSSR OSSR
1289 * @{
1290 */
1291 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1292 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1293 /**
1294 * @}
1295 */
1296
1297 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1298 * @{
1299 */
1300 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1301 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1302 /**
1303 * @}
1304 */
1305
1306 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1307 * @{
1308 */
1309 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1310 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1311 #if defined(COMP2)
1312 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1313 #endif /* COMP2 */
1314 #define LL_TIM_BKIN_SOURCE_MDF1 TIM1_AF1_BKDF1BK0E /*!< internal signal: Digital filter break output */
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1320 * @{
1321 */
1322 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1323 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1329 * @{
1330 */
1331 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1332 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1333 /**
1334 * @}
1335 */
1336
1337 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1338 * @{
1339 */
1340 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1341 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1342 /**
1343 * @}
1344 */
1345
1346 /** Legacy definitions for compatibility purpose
1347 @cond 0
1348 */
1349 #define LL_TIM_ReArmBRK(_PARAM_)
1350 #define LL_TIM_ReArmBRK2(_PARAM_)
1351 /**
1352 @endcond
1353 */
1354
1355 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1356 * @{
1357 */
1358 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1359 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1360 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1361 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1362 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1363 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1364 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1365 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1366 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1367 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1368 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1369 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1370 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1371 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1372 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1373 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1374 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1375 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1376 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1377 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1378 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1379 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1380 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1381 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1382 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1383 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1384 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR1 register is the DMA base address for DMA burst */
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1390 * @{
1391 */
1392 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1393 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1394 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1395 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1396 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1397 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1398 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1399 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1400 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1401 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1402 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1403 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1404 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1405 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1406 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1407 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1408 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1409 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1410 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1411 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1412 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1413 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1414 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1415 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1416 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1417 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1418 /**
1419 * @}
1420 */
1421
1422 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1423 * @{
1424 */
1425 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1426 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1427 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1428 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1429 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1430 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1431 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1432 /**
1433 * @}
1434 */
1435 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1436 * @{
1437 */
1438 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL /*!< TIM1 TI1 is connected to GPIO */
1439 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 TI1 is connected to COMP1 output */
1440 #if defined(COMP2)
1441 #define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 TI1 is connected to COMP2 output */
1442 #endif /* COMP2 */
1443 /**
1444 * @}
1445 */
1446
1447 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1448 * @{
1449 */
1450 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2 TI1 is connected to GPIO */
1451 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 TI1 is connected to COMP1 output */
1452 #if defined(COMP2)
1453 #define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 TI1 is connected to COMP2 output */
1454 #endif /* COMP2 */
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM16 External Input Ch2 Remap
1460 * @{
1461 */
1462 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2 TI2 is connected to GPIO */
1463 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 TI2 is connected to COMP1 output */
1464 #if defined(COMP2)
1465 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 TI2 is connected to COMP2 output */
1466 #endif /* COMP2 */
1467 /**
1468 * @}
1469 */
1470
1471 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1472 * @{
1473 */
1474 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2 TI4 is connected to COMP1 output */
1475 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 TI4 is connected to COMP1 output */
1476 #if defined(COMP2)
1477 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 TI4 is connected to COMP2 output */
1478 #endif /* COMP2 */
1479 /**
1480 * @}
1481 */
1482
1483 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1484 * @{
1485 */
1486 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3 TI1 is connected to GPIO */
1487 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 TI1 is connected to COMP1 output */
1488 #if defined(COMP2)
1489 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 TI1 is connected to COMP2 output */
1490 #endif /* COMP2 */
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
1496 * @{
1497 */
1498 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3 TI2 is connected to GPIO */
1499 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 TI2 is connected to COMP1 output */
1500 #if defined(COMP2)
1501 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 TI2 is connected to COMP2 output */
1502 #endif /* COMP2 */
1503 /**
1504 * @}
1505 */
1506
1507 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 External Input Ch1 Remap
1508 * @{
1509 */
1510 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000UL /*!< TIM4 TI1 is connected to GPIO */
1511 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 TI1 is connected to COMP1 output */
1512 #if defined(COMP2)
1513 #define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 TI1 is connected to COMP2 output */
1514 #endif /* COMP2 */
1515 /**
1516 * @}
1517 */
1518
1519 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 External Input Ch2 Remap
1520 * @{
1521 */
1522 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000UL /*!< TIM4 TI2 is connected to GPIO */
1523 #define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 TI2 is connected to COMP1 output */
1524 #if defined(COMP2)
1525 #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 TI2 is connected to COMP2 output */
1526 #endif /* COMP2 */
1527 /**
1528 * @}
1529 */
1530
1531 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 External Input Ch1 Remap
1532 * @{
1533 */
1534 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000UL /*!< TIM5 TI1 is connected to GPIO */
1535 #define LL_TIM_TIM5_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 TI1 is connected to LSI */
1536 #define LL_TIM_TIM5_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 TI1 is connected to LSE */
1537 #define LL_TIM_TIM5_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 TI1 is connected to RTC Wakeup */
1538 #define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 TI1 is connected to COMP1 output */
1539 #if defined(COMP2)
1540 #define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 TI1 is connected to COMP2 output */
1541 #endif /* COMP2 */
1542 /**
1543 * @}
1544 */
1545
1546 /** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 External Input Ch2 Remap
1547 * @{
1548 */
1549 #define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000UL /*!< TIM5 TI2 is connected to GPIO */
1550 #define LL_TIM_TIM5_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 TI2 is connected to COMP1 output */
1551 #if defined(COMP2)
1552 #define LL_TIM_TIM5_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 TI2 is connected to COMP2 output */
1553 #endif /* COMP2 */
1554 /**
1555 * @}
1556 */
1557
1558 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
1559 * @{
1560 */
1561 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000UL /*!< TIM8 TI1 is connected to GPIO */
1562 #define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 TI1 is connected to COMP1 output */
1563 #if defined(COMP2)
1564 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 TI1 is connected to COMP2 output */
1565 #endif /* COMP2 */
1566 /**
1567 * @}
1568 */
1569
1570 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1571 * @{
1572 */
1573 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15 TI1 is connected to GPIO */
1574 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 TI1 is connected to LSE */
1575 #define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 TI1 is connected to COMP1 output */
1576 #if defined(COMP2)
1577 #define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 TI1 is connected to COMP2 output */
1578 #endif /* COMP2 */
1579 /**
1580 * @}
1581 */
1582
1583 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
1584 * @{
1585 */
1586 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15 TI2 is connected to GPIO */
1587 #if defined(COMP2)
1588 #define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM15 TI2 is connected to COMP2 output */
1589 #endif /* COMP2 */
1590 /**
1591 * @}
1592 */
1593
1594 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1595 * @{
1596 */
1597 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16 TI1 is connected to GPIO */
1598 #define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to MCO */
1599 #define LL_TIM_TIM16_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSE DIV32 */
1600 #define LL_TIM_TIM16_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM16 TI1 is connected to RTC */
1601 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to LSE */
1602 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to LSI */
1603 #define LL_TIM_TIM16_TI1_RMP_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to MSIS/1024 */
1604 #define LL_TIM_TIM16_TI1_RMP_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM16 TI1 is connected to MSIS/4 */
1605 #define LL_TIM_TIM16_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16 TI1 is connected to HSI/256 */
1606 /**
1607 * @}
1608 */
1609
1610 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1611 * @{
1612 */
1613 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17 TI1 is connected to GPIO */
1614 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to MCO */
1615 #define LL_TIM_TIM17_TI1_RMP_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSE DIV32 */
1616 #define LL_TIM_TIM17_TI1_RMP_RTC TIM_TISEL_TI1SEL_2 /*!< TIM17 TI1 is connected to RTC */
1617 #define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to LSE */
1618 #define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to LSI */
1619 #define LL_TIM_TIM17_TI1_RMP_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to MSIS/1024 */
1620 #define LL_TIM_TIM17_TI1_RMP_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM17 TI1 is connected to MSIS/4 */
1621 #define LL_TIM_TIM17_TI1_RMP_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17 TI1 is connected to HSI/256 */
1622 /**
1623 * @}
1624 */
1625
1626 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1627 * @{
1628 */
1629 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_MSK /*!< OCREF_CLR_INT is connected to ETRF */
1630 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1631 #if defined(COMP2)
1632 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1633 #endif /* COMP2 */
1634 /**
1635 * @}
1636 */
1637
1638 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1639 * @{
1640 */
1641 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1642 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1643 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1644 /**
1645 * @}
1646 */
1647
1648 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1649 * @{
1650 */
1651 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1652 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1653 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1654 /**
1655 * @}
1656 */
1657
1658 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1659 * @{
1660 */
1661 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1662 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1663 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1664 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1665 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1666 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1667 /**
1668 * @}
1669 */
1670
1671 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1672 * @{
1673 */
1674 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1675 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1676 /**
1677 * @}
1678 */
1679 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1680 * @{
1681 */
1682 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1683 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1684 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1685 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1686 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1687 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1688 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1689 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1690 /**
1691 * @}
1692 */
1693
1694 /** Legacy definitions for compatibility purpose
1695 @cond 0
1696 */
1697 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1698 /**
1699 @endcond
1700 */
1701
1702 /**
1703 * @}
1704 */
1705
1706 /* Exported macro ------------------------------------------------------------*/
1707 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1708 * @{
1709 */
1710
1711 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1712 * @{
1713 */
1714 /**
1715 * @brief Write a value in TIM register.
1716 * @param __INSTANCE__ TIM Instance
1717 * @param __REG__ Register to be written
1718 * @param __VALUE__ Value to be written in the register
1719 * @retval None
1720 */
1721 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1722
1723 /**
1724 * @brief Read a value in TIM register.
1725 * @param __INSTANCE__ TIM Instance
1726 * @param __REG__ Register to be read
1727 * @retval Register value
1728 */
1729 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1730 /**
1731 * @}
1732 */
1733
1734 /**
1735 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1736 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1737 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1738 * to TIMx_CNT register bit 31)
1739 * @param __CNT__ Counter value
1740 * @retval UIF status bit
1741 */
1742 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1743 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1744
1745 /**
1746 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1747 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1748 * @param __TIMCLK__ timer input clock frequency (in Hz)
1749 * @param __CKD__ This parameter can be one of the following values:
1750 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1751 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1752 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1753 * @param __DT__ deadtime duration (in ns)
1754 * @retval DTG[0:7]
1755 */
1756 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1757 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1758 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1759 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1760 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1761 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1762 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1763 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1764 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1765 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1766 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1767 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1768 0U)
1769
1770 /**
1771 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1772 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1773 * @param __TIMCLK__ timer input clock frequency (in Hz)
1774 * @param __CNTCLK__ counter clock frequency (in Hz)
1775 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1776 */
1777 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1778 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1779
1780 /**
1781 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1782 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1783 * @param __TIMCLK__ timer input clock frequency (in Hz)
1784 * @param __PSC__ prescaler
1785 * @param __FREQ__ output signal frequency (in Hz)
1786 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1787 */
1788 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1789 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1790
1791 /**
1792 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1793 * output signal frequency.
1794 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1795 * @param __TIMCLK__ timer input clock frequency (in Hz)
1796 * @param __PSC__ prescaler
1797 * @param __FREQ__ output signal frequency (in Hz)
1798 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1799 */
1800 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1801 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1802 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1803
1804 /**
1805 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1806 * active/inactive delay.
1807 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1808 * @param __TIMCLK__ timer input clock frequency (in Hz)
1809 * @param __PSC__ prescaler
1810 * @param __DELAY__ timer output compare active/inactive delay (in us)
1811 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1812 */
1813 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1814 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1815 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1816
1817 /**
1818 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1819 * output compare active/inactive delay.
1820 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1821 * @param __TIMCLK__ timer input clock frequency (in Hz)
1822 * @param __PSC__ prescaler
1823 * @param __DELAY__ timer output compare active/inactive delay (in us)
1824 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1825 */
1826 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1827 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1828 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1829
1830 /**
1831 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1832 * (when the timer operates in one pulse mode).
1833 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1834 * @param __TIMCLK__ timer input clock frequency (in Hz)
1835 * @param __PSC__ prescaler
1836 * @param __DELAY__ timer output compare active/inactive delay (in us)
1837 * @param __PULSE__ pulse duration (in us)
1838 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1839 */
1840 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1841 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1842 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1843
1844 /**
1845 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1846 * pulse duration (when the timer operates in one pulse mode).
1847 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1848 * @param __TIMCLK__ timer input clock frequency (in Hz)
1849 * @param __PSC__ prescaler
1850 * @param __DELAY__ timer output compare active/inactive delay (in us)
1851 * @param __PULSE__ pulse duration (in us)
1852 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1853 */
1854 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1855 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1856 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1857
1858 /**
1859 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1860 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1861 * @param __ICPSC__ This parameter can be one of the following values:
1862 * @arg @ref LL_TIM_ICPSC_DIV1
1863 * @arg @ref LL_TIM_ICPSC_DIV2
1864 * @arg @ref LL_TIM_ICPSC_DIV4
1865 * @arg @ref LL_TIM_ICPSC_DIV8
1866 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1867 */
1868 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1869 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1870
1871
1872 /**
1873 * @}
1874 */
1875
1876 /* Exported functions --------------------------------------------------------*/
1877 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1878 * @{
1879 */
1880
1881 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1882 * @{
1883 */
1884 /**
1885 * @brief Enable timer counter.
1886 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1887 * @param TIMx Timer instance
1888 * @retval None
1889 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1890 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1891 {
1892 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1893 }
1894
1895 /**
1896 * @brief Disable timer counter.
1897 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1898 * @param TIMx Timer instance
1899 * @retval None
1900 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1901 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1902 {
1903 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1904 }
1905
1906 /**
1907 * @brief Indicates whether the timer counter is enabled.
1908 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1909 * @param TIMx Timer instance
1910 * @retval State of bit (1 or 0).
1911 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1912 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1913 {
1914 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1915 }
1916
1917 /**
1918 * @brief Enable update event generation.
1919 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1920 * @param TIMx Timer instance
1921 * @retval None
1922 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1923 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1924 {
1925 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1926 }
1927
1928 /**
1929 * @brief Disable update event generation.
1930 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1931 * @param TIMx Timer instance
1932 * @retval None
1933 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1934 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1935 {
1936 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1937 }
1938
1939 /**
1940 * @brief Indicates whether update event generation is enabled.
1941 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1942 * @param TIMx Timer instance
1943 * @retval Inverted state of bit (0 or 1).
1944 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1945 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1946 {
1947 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1948 }
1949
1950 /**
1951 * @brief Set update event source
1952 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1953 * generate an update interrupt or DMA request if enabled:
1954 * - Counter overflow/underflow
1955 * - Setting the UG bit
1956 * - Update generation through the slave mode controller
1957 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1958 * overflow/underflow generates an update interrupt or DMA request if enabled.
1959 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1960 * @param TIMx Timer instance
1961 * @param UpdateSource This parameter can be one of the following values:
1962 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1963 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1964 * @retval None
1965 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1966 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1967 {
1968 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1969 }
1970
1971 /**
1972 * @brief Get actual event update source
1973 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1974 * @param TIMx Timer instance
1975 * @retval Returned value can be one of the following values:
1976 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1977 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1978 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1979 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1980 {
1981 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1982 }
1983
1984 /**
1985 * @brief Set one pulse mode (one shot v.s. repetitive).
1986 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1987 * @param TIMx Timer instance
1988 * @param OnePulseMode This parameter can be one of the following values:
1989 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1990 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1991 * @retval None
1992 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1993 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1994 {
1995 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1996 }
1997
1998 /**
1999 * @brief Get actual one pulse mode.
2000 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
2001 * @param TIMx Timer instance
2002 * @retval Returned value can be one of the following values:
2003 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2004 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2005 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)2006 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
2007 {
2008 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
2009 }
2010
2011 /**
2012 * @brief Set the timer counter counting mode.
2013 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2014 * check whether or not the counter mode selection feature is supported
2015 * by a timer instance.
2016 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2017 * requires a timer reset to avoid unexpected direction
2018 * due to DIR bit readonly in center aligned mode.
2019 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
2020 * CR1 CMS LL_TIM_SetCounterMode
2021 * @param TIMx Timer instance
2022 * @param CounterMode This parameter can be one of the following values:
2023 * @arg @ref LL_TIM_COUNTERMODE_UP
2024 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2025 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2026 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2027 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2028 * @retval None
2029 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)2030 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
2031 {
2032 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
2033 }
2034
2035 /**
2036 * @brief Get actual counter mode.
2037 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2038 * check whether or not the counter mode selection feature is supported
2039 * by a timer instance.
2040 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
2041 * CR1 CMS LL_TIM_GetCounterMode
2042 * @param TIMx Timer instance
2043 * @retval Returned value can be one of the following values:
2044 * @arg @ref LL_TIM_COUNTERMODE_UP
2045 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2046 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2047 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2048 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2049 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)2050 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
2051 {
2052 uint32_t counter_mode;
2053
2054 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
2055
2056 if (counter_mode == 0U)
2057 {
2058 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2059 }
2060
2061 return counter_mode;
2062 }
2063
2064 /**
2065 * @brief Enable auto-reload (ARR) preload.
2066 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
2067 * @param TIMx Timer instance
2068 * @retval None
2069 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)2070 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
2071 {
2072 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
2073 }
2074
2075 /**
2076 * @brief Disable auto-reload (ARR) preload.
2077 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
2078 * @param TIMx Timer instance
2079 * @retval None
2080 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)2081 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
2082 {
2083 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
2084 }
2085
2086 /**
2087 * @brief Indicates whether auto-reload (ARR) preload is enabled.
2088 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
2089 * @param TIMx Timer instance
2090 * @retval State of bit (1 or 0).
2091 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)2092 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
2093 {
2094 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
2095 }
2096
2097 /**
2098 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
2099 * (when supported) and the digital filters.
2100 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2101 * whether or not the clock division feature is supported by the timer
2102 * instance.
2103 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
2104 * @param TIMx Timer instance
2105 * @param ClockDivision This parameter can be one of the following values:
2106 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2107 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2108 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2109 * @retval None
2110 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)2111 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
2112 {
2113 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
2114 }
2115
2116 /**
2117 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
2118 * generators (when supported) and the digital filters.
2119 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2120 * whether or not the clock division feature is supported by the timer
2121 * instance.
2122 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
2123 * @param TIMx Timer instance
2124 * @retval Returned value can be one of the following values:
2125 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2126 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2127 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2128 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)2129 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
2130 {
2131 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
2132 }
2133
2134 /**
2135 * @brief Set the counter value.
2136 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2137 * whether or not a timer instance supports a 32 bits counter.
2138 * @note If dithering is activated, pay attention to the Counter value interpretation
2139 * @rmtoll CNT CNT LL_TIM_SetCounter
2140 * @param TIMx Timer instance
2141 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2142 * @retval None
2143 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2144 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2145 {
2146 WRITE_REG(TIMx->CNT, Counter);
2147 }
2148
2149 /**
2150 * @brief Get the counter value.
2151 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2152 * whether or not a timer instance supports a 32 bits counter.
2153 * @note If dithering is activated, pay attention to the Counter value interpretation
2154 * @rmtoll CNT CNT LL_TIM_GetCounter
2155 * @param TIMx Timer instance
2156 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2157 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)2158 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
2159 {
2160 return (uint32_t)(READ_REG(TIMx->CNT));
2161 }
2162
2163 /**
2164 * @brief Get the current direction of the counter
2165 * @rmtoll CR1 DIR LL_TIM_GetDirection
2166 * @param TIMx Timer instance
2167 * @retval Returned value can be one of the following values:
2168 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2169 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2170 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)2171 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
2172 {
2173 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2174 }
2175
2176 /**
2177 * @brief Set the prescaler value.
2178 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2179 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2180 * prescaler ratio is taken into account at the next update event.
2181 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2182 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2183 * @param TIMx Timer instance
2184 * @param Prescaler between Min_Data=0 and Max_Data=65535
2185 * @retval None
2186 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2187 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2188 {
2189 WRITE_REG(TIMx->PSC, Prescaler);
2190 }
2191
2192 /**
2193 * @brief Get the prescaler value.
2194 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2195 * @param TIMx Timer instance
2196 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2197 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)2198 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
2199 {
2200 return (uint32_t)(READ_REG(TIMx->PSC));
2201 }
2202
2203 /**
2204 * @brief Set the auto-reload value.
2205 * @note The counter is blocked while the auto-reload value is null.
2206 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2207 * whether or not a timer instance supports a 32 bits counter.
2208 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2209 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2210 * parameter.
2211 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2212 * @param TIMx Timer instance
2213 * @param AutoReload between Min_Data=0 and Max_Data=65535
2214 * @retval None
2215 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2216 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2217 {
2218 WRITE_REG(TIMx->ARR, AutoReload);
2219 }
2220
2221 /**
2222 * @brief Get the auto-reload value.
2223 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2224 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2225 * whether or not a timer instance supports a 32 bits counter.
2226 * @note If dithering is activated, pay attention to the returned value interpretation
2227 * @param TIMx Timer instance
2228 * @retval Auto-reload value
2229 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2230 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2231 {
2232 return (uint32_t)(READ_REG(TIMx->ARR));
2233 }
2234
2235 /**
2236 * @brief Set the repetition counter value.
2237 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2238 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2239 * whether or not a timer instance supports a repetition counter.
2240 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2241 * @param TIMx Timer instance
2242 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2243 * @retval None
2244 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2245 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2246 {
2247 WRITE_REG(TIMx->RCR, RepetitionCounter);
2248 }
2249
2250 /**
2251 * @brief Get the repetition counter value.
2252 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2253 * whether or not a timer instance supports a repetition counter.
2254 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2255 * @param TIMx Timer instance
2256 * @retval Repetition counter value
2257 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2258 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2259 {
2260 return (uint32_t)(READ_REG(TIMx->RCR));
2261 }
2262
2263 /**
2264 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2265 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2266 * in an atomic way.
2267 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2268 * @param TIMx Timer instance
2269 * @retval None
2270 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2271 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2272 {
2273 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2274 }
2275
2276 /**
2277 * @brief Disable update interrupt flag (UIF) remapping.
2278 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2279 * @param TIMx Timer instance
2280 * @retval None
2281 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2282 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2283 {
2284 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2285 }
2286
2287 /**
2288 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2289 * @param Counter Counter value
2290 * @retval State of bit (1 or 0).
2291 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2292 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2293 {
2294 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2295 }
2296
2297 /**
2298 * @brief Enable dithering.
2299 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2300 * a timer instance provides dithering.
2301 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2302 * @param TIMx Timer instance
2303 * @retval None
2304 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2305 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2306 {
2307 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2308 }
2309
2310 /**
2311 * @brief Disable dithering.
2312 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2313 * a timer instance provides dithering.
2314 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2315 * @param TIMx Timer instance
2316 * @retval None
2317 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2318 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2319 {
2320 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2321 }
2322
2323 /**
2324 * @brief Indicates whether dithering is activated.
2325 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2326 * a timer instance provides dithering.
2327 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2328 * @param TIMx Timer instance
2329 * @retval State of bit (1 or 0).
2330 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2331 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2332 {
2333 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2334 }
2335
2336 /**
2337 * @}
2338 */
2339
2340 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2341 * @{
2342 */
2343 /**
2344 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2345 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2346 * they are updated only when a commutation event (COM) occurs.
2347 * @note Only on channels that have a complementary output.
2348 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2349 * whether or not a timer instance is able to generate a commutation event.
2350 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2351 * @param TIMx Timer instance
2352 * @retval None
2353 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2354 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2355 {
2356 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2357 }
2358
2359 /**
2360 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2361 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2362 * whether or not a timer instance is able to generate a commutation event.
2363 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2364 * @param TIMx Timer instance
2365 * @retval None
2366 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2367 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2368 {
2369 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2370 }
2371
2372 /**
2373 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2374 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2375 * @param TIMx Timer instance
2376 * @retval State of bit (1 or 0).
2377 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2378 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2379 {
2380 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2381 }
2382
2383 /**
2384 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2385 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2386 * whether or not a timer instance is able to generate a commutation event.
2387 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2388 * @param TIMx Timer instance
2389 * @param CCUpdateSource This parameter can be one of the following values:
2390 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2391 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2392 * @retval None
2393 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2394 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2395 {
2396 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2397 }
2398
2399 /**
2400 * @brief Set the trigger of the capture/compare DMA request.
2401 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2402 * @param TIMx Timer instance
2403 * @param DMAReqTrigger This parameter can be one of the following values:
2404 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2405 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2406 * @retval None
2407 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2408 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2409 {
2410 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2411 }
2412
2413 /**
2414 * @brief Get actual trigger of the capture/compare DMA request.
2415 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2416 * @param TIMx Timer instance
2417 * @retval Returned value can be one of the following values:
2418 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2419 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2420 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2421 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2422 {
2423 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2424 }
2425
2426 /**
2427 * @brief Set the lock level to freeze the
2428 * configuration of several capture/compare parameters.
2429 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2430 * the lock mechanism is supported by a timer instance.
2431 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2432 * @param TIMx Timer instance
2433 * @param LockLevel This parameter can be one of the following values:
2434 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2435 * @arg @ref LL_TIM_LOCKLEVEL_1
2436 * @arg @ref LL_TIM_LOCKLEVEL_2
2437 * @arg @ref LL_TIM_LOCKLEVEL_3
2438 * @retval None
2439 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2440 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2441 {
2442 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2443 }
2444
2445 /**
2446 * @brief Enable capture/compare channels.
2447 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2448 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2449 * CCER CC2E LL_TIM_CC_EnableChannel\n
2450 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2451 * CCER CC3E LL_TIM_CC_EnableChannel\n
2452 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2453 * CCER CC4E LL_TIM_CC_EnableChannel\n
2454 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2455 * CCER CC5E LL_TIM_CC_EnableChannel\n
2456 * CCER CC6E LL_TIM_CC_EnableChannel
2457 * @param TIMx Timer instance
2458 * @param Channels This parameter can be a combination of the following values:
2459 * @arg @ref LL_TIM_CHANNEL_CH1
2460 * @arg @ref LL_TIM_CHANNEL_CH1N
2461 * @arg @ref LL_TIM_CHANNEL_CH2
2462 * @arg @ref LL_TIM_CHANNEL_CH2N
2463 * @arg @ref LL_TIM_CHANNEL_CH3
2464 * @arg @ref LL_TIM_CHANNEL_CH3N
2465 * @arg @ref LL_TIM_CHANNEL_CH4
2466 * @arg @ref LL_TIM_CHANNEL_CH4N
2467 * @arg @ref LL_TIM_CHANNEL_CH5
2468 * @arg @ref LL_TIM_CHANNEL_CH6
2469 * @retval None
2470 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2471 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2472 {
2473 SET_BIT(TIMx->CCER, Channels);
2474 }
2475
2476 /**
2477 * @brief Disable capture/compare channels.
2478 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2479 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2480 * CCER CC2E LL_TIM_CC_DisableChannel\n
2481 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2482 * CCER CC3E LL_TIM_CC_DisableChannel\n
2483 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2484 * CCER CC4E LL_TIM_CC_DisableChannel\n
2485 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2486 * CCER CC5E LL_TIM_CC_DisableChannel\n
2487 * CCER CC6E LL_TIM_CC_DisableChannel
2488 * @param TIMx Timer instance
2489 * @param Channels This parameter can be a combination of the following values:
2490 * @arg @ref LL_TIM_CHANNEL_CH1
2491 * @arg @ref LL_TIM_CHANNEL_CH1N
2492 * @arg @ref LL_TIM_CHANNEL_CH2
2493 * @arg @ref LL_TIM_CHANNEL_CH2N
2494 * @arg @ref LL_TIM_CHANNEL_CH3
2495 * @arg @ref LL_TIM_CHANNEL_CH3N
2496 * @arg @ref LL_TIM_CHANNEL_CH4
2497 * @arg @ref LL_TIM_CHANNEL_CH4N
2498 * @arg @ref LL_TIM_CHANNEL_CH5
2499 * @arg @ref LL_TIM_CHANNEL_CH6
2500 * @retval None
2501 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2502 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2503 {
2504 CLEAR_BIT(TIMx->CCER, Channels);
2505 }
2506
2507 /**
2508 * @brief Indicate whether channel(s) is(are) enabled.
2509 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2510 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2511 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2512 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2513 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2514 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2515 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2516 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2517 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2518 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2519 * @param TIMx Timer instance
2520 * @param Channels This parameter can be a combination of the following values:
2521 * @arg @ref LL_TIM_CHANNEL_CH1
2522 * @arg @ref LL_TIM_CHANNEL_CH1N
2523 * @arg @ref LL_TIM_CHANNEL_CH2
2524 * @arg @ref LL_TIM_CHANNEL_CH2N
2525 * @arg @ref LL_TIM_CHANNEL_CH3
2526 * @arg @ref LL_TIM_CHANNEL_CH3N
2527 * @arg @ref LL_TIM_CHANNEL_CH4
2528 * @arg @ref LL_TIM_CHANNEL_CH4N
2529 * @arg @ref LL_TIM_CHANNEL_CH5
2530 * @arg @ref LL_TIM_CHANNEL_CH6
2531 * @retval State of bit (1 or 0).
2532 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2533 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2534 {
2535 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2536 }
2537
2538 /**
2539 * @}
2540 */
2541
2542 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2543 * @{
2544 */
2545 /**
2546 * @brief Configure an output channel.
2547 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2548 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2549 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2550 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2551 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2552 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2553 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2554 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2555 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2556 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2557 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2558 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2559 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2560 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2561 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2562 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2563 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2564 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2565 * @param TIMx Timer instance
2566 * @param Channel This parameter can be one of the following values:
2567 * @arg @ref LL_TIM_CHANNEL_CH1
2568 * @arg @ref LL_TIM_CHANNEL_CH2
2569 * @arg @ref LL_TIM_CHANNEL_CH3
2570 * @arg @ref LL_TIM_CHANNEL_CH4
2571 * @arg @ref LL_TIM_CHANNEL_CH5
2572 * @arg @ref LL_TIM_CHANNEL_CH6
2573 * @param Configuration This parameter must be a combination of all the following values:
2574 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2575 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2576 * @retval None
2577 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2578 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2579 {
2580 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2581 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2582 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2583 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2584 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2585 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2586 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2587 }
2588
2589 /**
2590 * @brief Define the behavior of the output reference signal OCxREF from which
2591 * OCx and OCxN (when relevant) are derived.
2592 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2593 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2594 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2595 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2596 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2597 * CCMR3 OC6M LL_TIM_OC_SetMode
2598 * @param TIMx Timer instance
2599 * @param Channel This parameter can be one of the following values:
2600 * @arg @ref LL_TIM_CHANNEL_CH1
2601 * @arg @ref LL_TIM_CHANNEL_CH2
2602 * @arg @ref LL_TIM_CHANNEL_CH3
2603 * @arg @ref LL_TIM_CHANNEL_CH4
2604 * @arg @ref LL_TIM_CHANNEL_CH5
2605 * @arg @ref LL_TIM_CHANNEL_CH6
2606 * @param Mode This parameter can be one of the following values:
2607 * @arg @ref LL_TIM_OCMODE_FROZEN
2608 * @arg @ref LL_TIM_OCMODE_ACTIVE
2609 * @arg @ref LL_TIM_OCMODE_INACTIVE
2610 * @arg @ref LL_TIM_OCMODE_TOGGLE
2611 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2612 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2613 * @arg @ref LL_TIM_OCMODE_PWM1
2614 * @arg @ref LL_TIM_OCMODE_PWM2
2615 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2616 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2617 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2618 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2619 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2620 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2621 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2622 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2623 * @retval None
2624 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2625 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2626 {
2627 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2628 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2629 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2630 }
2631
2632 /**
2633 * @brief Get the output compare mode of an output channel.
2634 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2635 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2636 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2637 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2638 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2639 * CCMR3 OC6M LL_TIM_OC_GetMode
2640 * @param TIMx Timer instance
2641 * @param Channel This parameter can be one of the following values:
2642 * @arg @ref LL_TIM_CHANNEL_CH1
2643 * @arg @ref LL_TIM_CHANNEL_CH2
2644 * @arg @ref LL_TIM_CHANNEL_CH3
2645 * @arg @ref LL_TIM_CHANNEL_CH4
2646 * @arg @ref LL_TIM_CHANNEL_CH5
2647 * @arg @ref LL_TIM_CHANNEL_CH6
2648 * @retval Returned value can be one of the following values:
2649 * @arg @ref LL_TIM_OCMODE_FROZEN
2650 * @arg @ref LL_TIM_OCMODE_ACTIVE
2651 * @arg @ref LL_TIM_OCMODE_INACTIVE
2652 * @arg @ref LL_TIM_OCMODE_TOGGLE
2653 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2654 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2655 * @arg @ref LL_TIM_OCMODE_PWM1
2656 * @arg @ref LL_TIM_OCMODE_PWM2
2657 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2658 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2659 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2660 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2661 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2662 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2663 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2664 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2665 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2666 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2667 {
2668 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2669 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2670 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2671 }
2672
2673 /**
2674 * @brief Set the polarity of an output channel.
2675 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2676 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2677 * CCER CC2P LL_TIM_OC_SetPolarity\n
2678 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2679 * CCER CC3P LL_TIM_OC_SetPolarity\n
2680 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2681 * CCER CC4P LL_TIM_OC_SetPolarity\n
2682 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2683 * CCER CC5P LL_TIM_OC_SetPolarity\n
2684 * CCER CC6P LL_TIM_OC_SetPolarity
2685 * @param TIMx Timer instance
2686 * @param Channel This parameter can be one of the following values:
2687 * @arg @ref LL_TIM_CHANNEL_CH1
2688 * @arg @ref LL_TIM_CHANNEL_CH1N
2689 * @arg @ref LL_TIM_CHANNEL_CH2
2690 * @arg @ref LL_TIM_CHANNEL_CH2N
2691 * @arg @ref LL_TIM_CHANNEL_CH3
2692 * @arg @ref LL_TIM_CHANNEL_CH3N
2693 * @arg @ref LL_TIM_CHANNEL_CH4
2694 * @arg @ref LL_TIM_CHANNEL_CH4N
2695 * @arg @ref LL_TIM_CHANNEL_CH5
2696 * @arg @ref LL_TIM_CHANNEL_CH6
2697 * @param Polarity This parameter can be one of the following values:
2698 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2699 * @arg @ref LL_TIM_OCPOLARITY_LOW
2700 * @retval None
2701 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2702 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2703 {
2704 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2705 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2706 }
2707
2708 /**
2709 * @brief Get the polarity of an output channel.
2710 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2711 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2712 * CCER CC2P LL_TIM_OC_GetPolarity\n
2713 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2714 * CCER CC3P LL_TIM_OC_GetPolarity\n
2715 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2716 * CCER CC4P LL_TIM_OC_GetPolarity\n
2717 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2718 * CCER CC5P LL_TIM_OC_GetPolarity\n
2719 * CCER CC6P LL_TIM_OC_GetPolarity
2720 * @param TIMx Timer instance
2721 * @param Channel This parameter can be one of the following values:
2722 * @arg @ref LL_TIM_CHANNEL_CH1
2723 * @arg @ref LL_TIM_CHANNEL_CH1N
2724 * @arg @ref LL_TIM_CHANNEL_CH2
2725 * @arg @ref LL_TIM_CHANNEL_CH2N
2726 * @arg @ref LL_TIM_CHANNEL_CH3
2727 * @arg @ref LL_TIM_CHANNEL_CH3N
2728 * @arg @ref LL_TIM_CHANNEL_CH4
2729 * @arg @ref LL_TIM_CHANNEL_CH4N
2730 * @arg @ref LL_TIM_CHANNEL_CH5
2731 * @arg @ref LL_TIM_CHANNEL_CH6
2732 * @retval Returned value can be one of the following values:
2733 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2734 * @arg @ref LL_TIM_OCPOLARITY_LOW
2735 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2736 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2737 {
2738 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2739 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2740 }
2741
2742 /**
2743 * @brief Set the IDLE state of an output channel
2744 * @note This function is significant only for the timer instances
2745 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2746 * can be used to check whether or not a timer instance provides
2747 * a break input.
2748 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2749 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2750 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2751 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2752 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2753 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2754 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2755 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2756 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2757 * CR2 OIS6 LL_TIM_OC_SetIdleState
2758 * @param TIMx Timer instance
2759 * @param Channel This parameter can be one of the following values:
2760 * @arg @ref LL_TIM_CHANNEL_CH1
2761 * @arg @ref LL_TIM_CHANNEL_CH1N
2762 * @arg @ref LL_TIM_CHANNEL_CH2
2763 * @arg @ref LL_TIM_CHANNEL_CH2N
2764 * @arg @ref LL_TIM_CHANNEL_CH3
2765 * @arg @ref LL_TIM_CHANNEL_CH3N
2766 * @arg @ref LL_TIM_CHANNEL_CH4
2767 * @arg @ref LL_TIM_CHANNEL_CH4N
2768 * @arg @ref LL_TIM_CHANNEL_CH5
2769 * @arg @ref LL_TIM_CHANNEL_CH6
2770 * @param IdleState This parameter can be one of the following values:
2771 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2772 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2773 * @retval None
2774 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2775 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2776 {
2777 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2778 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2779 }
2780
2781 /**
2782 * @brief Get the IDLE state of an output channel
2783 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2784 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2785 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2786 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2787 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2788 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2789 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2790 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2791 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2792 * CR2 OIS6 LL_TIM_OC_GetIdleState
2793 * @param TIMx Timer instance
2794 * @param Channel This parameter can be one of the following values:
2795 * @arg @ref LL_TIM_CHANNEL_CH1
2796 * @arg @ref LL_TIM_CHANNEL_CH1N
2797 * @arg @ref LL_TIM_CHANNEL_CH2
2798 * @arg @ref LL_TIM_CHANNEL_CH2N
2799 * @arg @ref LL_TIM_CHANNEL_CH3
2800 * @arg @ref LL_TIM_CHANNEL_CH3N
2801 * @arg @ref LL_TIM_CHANNEL_CH4
2802 * @arg @ref LL_TIM_CHANNEL_CH4N
2803 * @arg @ref LL_TIM_CHANNEL_CH5
2804 * @arg @ref LL_TIM_CHANNEL_CH6
2805 * @retval Returned value can be one of the following values:
2806 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2807 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2808 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2809 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2810 {
2811 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2812 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2813 }
2814
2815 /**
2816 * @brief Enable fast mode for the output channel.
2817 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2818 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2819 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2820 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2821 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2822 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2823 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2824 * @param TIMx Timer instance
2825 * @param Channel This parameter can be one of the following values:
2826 * @arg @ref LL_TIM_CHANNEL_CH1
2827 * @arg @ref LL_TIM_CHANNEL_CH2
2828 * @arg @ref LL_TIM_CHANNEL_CH3
2829 * @arg @ref LL_TIM_CHANNEL_CH4
2830 * @arg @ref LL_TIM_CHANNEL_CH5
2831 * @arg @ref LL_TIM_CHANNEL_CH6
2832 * @retval None
2833 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2834 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2835 {
2836 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2837 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2838 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2839
2840 }
2841
2842 /**
2843 * @brief Disable fast mode for the output channel.
2844 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2845 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2846 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2847 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2848 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2849 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2850 * @param TIMx Timer instance
2851 * @param Channel This parameter can be one of the following values:
2852 * @arg @ref LL_TIM_CHANNEL_CH1
2853 * @arg @ref LL_TIM_CHANNEL_CH2
2854 * @arg @ref LL_TIM_CHANNEL_CH3
2855 * @arg @ref LL_TIM_CHANNEL_CH4
2856 * @arg @ref LL_TIM_CHANNEL_CH5
2857 * @arg @ref LL_TIM_CHANNEL_CH6
2858 * @retval None
2859 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2860 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2861 {
2862 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2863 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2864 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2865
2866 }
2867
2868 /**
2869 * @brief Indicates whether fast mode is enabled for the output channel.
2870 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2871 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2872 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2873 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2874 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2875 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2876 * @param TIMx Timer instance
2877 * @param Channel This parameter can be one of the following values:
2878 * @arg @ref LL_TIM_CHANNEL_CH1
2879 * @arg @ref LL_TIM_CHANNEL_CH2
2880 * @arg @ref LL_TIM_CHANNEL_CH3
2881 * @arg @ref LL_TIM_CHANNEL_CH4
2882 * @arg @ref LL_TIM_CHANNEL_CH5
2883 * @arg @ref LL_TIM_CHANNEL_CH6
2884 * @retval State of bit (1 or 0).
2885 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2886 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2887 {
2888 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2889 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2890 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2891 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2892 }
2893
2894 /**
2895 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2896 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2897 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2898 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2899 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2900 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2901 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2902 * @param TIMx Timer instance
2903 * @param Channel This parameter can be one of the following values:
2904 * @arg @ref LL_TIM_CHANNEL_CH1
2905 * @arg @ref LL_TIM_CHANNEL_CH2
2906 * @arg @ref LL_TIM_CHANNEL_CH3
2907 * @arg @ref LL_TIM_CHANNEL_CH4
2908 * @arg @ref LL_TIM_CHANNEL_CH5
2909 * @arg @ref LL_TIM_CHANNEL_CH6
2910 * @retval None
2911 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2912 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2913 {
2914 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2915 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2916 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2917 }
2918
2919 /**
2920 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2921 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2922 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2923 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2924 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2925 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2926 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2927 * @param TIMx Timer instance
2928 * @param Channel This parameter can be one of the following values:
2929 * @arg @ref LL_TIM_CHANNEL_CH1
2930 * @arg @ref LL_TIM_CHANNEL_CH2
2931 * @arg @ref LL_TIM_CHANNEL_CH3
2932 * @arg @ref LL_TIM_CHANNEL_CH4
2933 * @arg @ref LL_TIM_CHANNEL_CH5
2934 * @arg @ref LL_TIM_CHANNEL_CH6
2935 * @retval None
2936 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2937 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2938 {
2939 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2941 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2942 }
2943
2944 /**
2945 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2946 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2947 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2948 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2949 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2950 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2951 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2952 * @param TIMx Timer instance
2953 * @param Channel This parameter can be one of the following values:
2954 * @arg @ref LL_TIM_CHANNEL_CH1
2955 * @arg @ref LL_TIM_CHANNEL_CH2
2956 * @arg @ref LL_TIM_CHANNEL_CH3
2957 * @arg @ref LL_TIM_CHANNEL_CH4
2958 * @arg @ref LL_TIM_CHANNEL_CH5
2959 * @arg @ref LL_TIM_CHANNEL_CH6
2960 * @retval State of bit (1 or 0).
2961 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2962 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2963 {
2964 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2965 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2966 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2967 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2968 }
2969
2970 /**
2971 * @brief Enable clearing the output channel on an external event.
2972 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2973 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2974 * or not a timer instance can clear the OCxREF signal on an external event.
2975 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2976 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2977 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2978 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2979 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2980 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2981 * @param TIMx Timer instance
2982 * @param Channel This parameter can be one of the following values:
2983 * @arg @ref LL_TIM_CHANNEL_CH1
2984 * @arg @ref LL_TIM_CHANNEL_CH2
2985 * @arg @ref LL_TIM_CHANNEL_CH3
2986 * @arg @ref LL_TIM_CHANNEL_CH4
2987 * @arg @ref LL_TIM_CHANNEL_CH5
2988 * @arg @ref LL_TIM_CHANNEL_CH6
2989 * @retval None
2990 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2991 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2992 {
2993 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2994 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2995 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2996 }
2997
2998 /**
2999 * @brief Disable clearing the output channel on an external event.
3000 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3001 * or not a timer instance can clear the OCxREF signal on an external event.
3002 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
3003 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
3004 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
3005 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
3006 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
3007 * CCMR3 OC6CE LL_TIM_OC_DisableClear
3008 * @param TIMx Timer instance
3009 * @param Channel This parameter can be one of the following values:
3010 * @arg @ref LL_TIM_CHANNEL_CH1
3011 * @arg @ref LL_TIM_CHANNEL_CH2
3012 * @arg @ref LL_TIM_CHANNEL_CH3
3013 * @arg @ref LL_TIM_CHANNEL_CH4
3014 * @arg @ref LL_TIM_CHANNEL_CH5
3015 * @arg @ref LL_TIM_CHANNEL_CH6
3016 * @retval None
3017 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)3018 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3019 {
3020 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3021 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3022 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3023 }
3024
3025 /**
3026 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
3027 * @note This function enables clearing the output channel on an external event.
3028 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3029 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3030 * or not a timer instance can clear the OCxREF signal on an external event.
3031 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
3032 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
3033 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
3034 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
3035 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
3036 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
3037 * @param TIMx Timer instance
3038 * @param Channel This parameter can be one of the following values:
3039 * @arg @ref LL_TIM_CHANNEL_CH1
3040 * @arg @ref LL_TIM_CHANNEL_CH2
3041 * @arg @ref LL_TIM_CHANNEL_CH3
3042 * @arg @ref LL_TIM_CHANNEL_CH4
3043 * @arg @ref LL_TIM_CHANNEL_CH5
3044 * @arg @ref LL_TIM_CHANNEL_CH6
3045 * @retval State of bit (1 or 0).
3046 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)3047 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
3048 {
3049 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3050 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3051 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
3052 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3053 }
3054
3055 /**
3056 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
3057 * the Ocx and OCxN signals).
3058 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3059 * dead-time insertion feature is supported by a timer instance.
3060 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
3061 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
3062 * @param TIMx Timer instance
3063 * @param DeadTime between Min_Data=0 and Max_Data=255
3064 * @retval None
3065 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)3066 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
3067 {
3068 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
3069 }
3070
3071 /**
3072 * @brief Set compare value for output channel 1 (TIMx_CCR1).
3073 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3074 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3075 * whether or not a timer instance supports a 32 bits counter.
3076 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3077 * output channel 1 is supported by a timer instance.
3078 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3079 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
3080 * @param TIMx Timer instance
3081 * @param CompareValue between Min_Data=0 and Max_Data=65535
3082 * @retval None
3083 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)3084 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
3085 {
3086 WRITE_REG(TIMx->CCR1, CompareValue);
3087 }
3088
3089 /**
3090 * @brief Set compare value for output channel 2 (TIMx_CCR2).
3091 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3092 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3093 * whether or not a timer instance supports a 32 bits counter.
3094 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3095 * output channel 2 is supported by a timer instance.
3096 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3097 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
3098 * @param TIMx Timer instance
3099 * @param CompareValue between Min_Data=0 and Max_Data=65535
3100 * @retval None
3101 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)3102 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
3103 {
3104 WRITE_REG(TIMx->CCR2, CompareValue);
3105 }
3106
3107 /**
3108 * @brief Set compare value for output channel 3 (TIMx_CCR3).
3109 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3110 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3111 * whether or not a timer instance supports a 32 bits counter.
3112 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3113 * output channel is supported by a timer instance.
3114 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3115 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
3116 * @param TIMx Timer instance
3117 * @param CompareValue between Min_Data=0 and Max_Data=65535
3118 * @retval None
3119 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)3120 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
3121 {
3122 WRITE_REG(TIMx->CCR3, CompareValue);
3123 }
3124
3125 /**
3126 * @brief Set compare value for output channel 4 (TIMx_CCR4).
3127 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3128 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3129 * whether or not a timer instance supports a 32 bits counter.
3130 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3131 * output channel 4 is supported by a timer instance.
3132 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3133 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
3134 * @param TIMx Timer instance
3135 * @param CompareValue between Min_Data=0 and Max_Data=65535
3136 * @retval None
3137 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)3138 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
3139 {
3140 WRITE_REG(TIMx->CCR4, CompareValue);
3141 }
3142
3143 /**
3144 * @brief Set compare value for output channel 5 (TIMx_CCR5).
3145 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3146 * output channel 5 is supported by a timer instance.
3147 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3148 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3149 * @param TIMx Timer instance
3150 * @param CompareValue between Min_Data=0 and Max_Data=65535
3151 * @retval None
3152 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3153 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3154 {
3155 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3156 }
3157
3158 /**
3159 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3160 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3161 * output channel 6 is supported by a timer instance.
3162 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3163 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3164 * @param TIMx Timer instance
3165 * @param CompareValue between Min_Data=0 and Max_Data=65535
3166 * @retval None
3167 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3168 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3169 {
3170 WRITE_REG(TIMx->CCR6, CompareValue);
3171 }
3172
3173 /**
3174 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3175 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3176 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3177 * whether or not a timer instance supports a 32 bits counter.
3178 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3179 * output channel 1 is supported by a timer instance.
3180 * @note If dithering is activated, pay attention to the returned value interpretation.
3181 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3182 * @param TIMx Timer instance
3183 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3184 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)3185 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
3186 {
3187 return (uint32_t)(READ_REG(TIMx->CCR1));
3188 }
3189
3190 /**
3191 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3192 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3193 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3194 * whether or not a timer instance supports a 32 bits counter.
3195 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3196 * output channel 2 is supported by a timer instance.
3197 * @note If dithering is activated, pay attention to the returned value interpretation.
3198 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3199 * @param TIMx Timer instance
3200 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3201 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)3202 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
3203 {
3204 return (uint32_t)(READ_REG(TIMx->CCR2));
3205 }
3206
3207 /**
3208 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3209 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3210 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3211 * whether or not a timer instance supports a 32 bits counter.
3212 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3213 * output channel 3 is supported by a timer instance.
3214 * @note If dithering is activated, pay attention to the returned value interpretation.
3215 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3216 * @param TIMx Timer instance
3217 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3218 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)3219 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
3220 {
3221 return (uint32_t)(READ_REG(TIMx->CCR3));
3222 }
3223
3224 /**
3225 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3226 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3227 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3228 * whether or not a timer instance supports a 32 bits counter.
3229 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3230 * output channel 4 is supported by a timer instance.
3231 * @note If dithering is activated, pay attention to the returned value interpretation.
3232 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3233 * @param TIMx Timer instance
3234 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3235 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3236 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3237 {
3238 return (uint32_t)(READ_REG(TIMx->CCR4));
3239 }
3240
3241 /**
3242 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3243 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3244 * output channel 5 is supported by a timer instance.
3245 * @note If dithering is activated, pay attention to the returned value interpretation.
3246 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3247 * @param TIMx Timer instance
3248 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3249 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3250 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3251 {
3252 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3253 }
3254
3255 /**
3256 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3257 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3258 * output channel 6 is supported by a timer instance.
3259 * @note If dithering is activated, pay attention to the returned value interpretation.
3260 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3261 * @param TIMx Timer instance
3262 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3263 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3264 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3265 {
3266 return (uint32_t)(READ_REG(TIMx->CCR6));
3267 }
3268
3269 /**
3270 * @brief Select on which reference signal the OC5REF is combined to.
3271 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3272 * whether or not a timer instance supports the combined 3-phase PWM mode.
3273 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3274 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3275 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3276 * @param TIMx Timer instance
3277 * @param GroupCH5 This parameter can be a combination of the following values:
3278 * @arg @ref LL_TIM_GROUPCH5_NONE
3279 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3280 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3281 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3282 * @retval None
3283 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3284 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3285 {
3286 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3287 }
3288
3289 /**
3290 * @brief Set the pulse on compare pulse width prescaler.
3291 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3292 * whether or not the pulse on compare feature is supported by the timer
3293 * instance.
3294 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3295 * @param TIMx Timer instance
3296 * @param PulseWidthPrescaler This parameter can be one of the following values:
3297 * @arg @ref LL_TIM_PWPRSC_X1
3298 * @arg @ref LL_TIM_PWPRSC_X2
3299 * @arg @ref LL_TIM_PWPRSC_X4
3300 * @arg @ref LL_TIM_PWPRSC_X8
3301 * @arg @ref LL_TIM_PWPRSC_X16
3302 * @arg @ref LL_TIM_PWPRSC_X32
3303 * @arg @ref LL_TIM_PWPRSC_X64
3304 * @arg @ref LL_TIM_PWPRSC_X128
3305 * @retval None
3306 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3307 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3308 {
3309 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3310 }
3311
3312 /**
3313 * @brief Get the pulse on compare pulse width prescaler.
3314 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3315 * whether or not the pulse on compare feature is supported by the timer
3316 * instance.
3317 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3318 * @param TIMx Timer instance
3319 * @retval Returned value can be one of the following values:
3320 * @arg @ref LL_TIM_PWPRSC_X1
3321 * @arg @ref LL_TIM_PWPRSC_X2
3322 * @arg @ref LL_TIM_PWPRSC_X4
3323 * @arg @ref LL_TIM_PWPRSC_X8
3324 * @arg @ref LL_TIM_PWPRSC_X16
3325 * @arg @ref LL_TIM_PWPRSC_X32
3326 * @arg @ref LL_TIM_PWPRSC_X64
3327 * @arg @ref LL_TIM_PWPRSC_X128
3328 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3329 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3330 {
3331 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3332 }
3333
3334 /**
3335 * @brief Set the pulse on compare pulse width duration.
3336 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3337 * whether or not the pulse on compare feature is supported by the timer
3338 * instance.
3339 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3340 * @param TIMx Timer instance
3341 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3342 * @retval None
3343 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3344 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3345 {
3346 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3347 }
3348
3349 /**
3350 * @brief Get the pulse on compare pulse width duration.
3351 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3352 * whether or not the pulse on compare feature is supported by the timer
3353 * instance.
3354 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3355 * @param TIMx Timer instance
3356 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3357 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3358 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3359 {
3360 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3361 }
3362
3363 /**
3364 * @}
3365 */
3366
3367 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3368 * @{
3369 */
3370 /**
3371 * @brief Configure input channel.
3372 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3373 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3374 * CCMR1 IC1F LL_TIM_IC_Config\n
3375 * CCMR1 CC2S LL_TIM_IC_Config\n
3376 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3377 * CCMR1 IC2F LL_TIM_IC_Config\n
3378 * CCMR2 CC3S LL_TIM_IC_Config\n
3379 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3380 * CCMR2 IC3F LL_TIM_IC_Config\n
3381 * CCMR2 CC4S LL_TIM_IC_Config\n
3382 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3383 * CCMR2 IC4F LL_TIM_IC_Config\n
3384 * CCER CC1P LL_TIM_IC_Config\n
3385 * CCER CC1NP LL_TIM_IC_Config\n
3386 * CCER CC2P LL_TIM_IC_Config\n
3387 * CCER CC2NP LL_TIM_IC_Config\n
3388 * CCER CC3P LL_TIM_IC_Config\n
3389 * CCER CC3NP LL_TIM_IC_Config\n
3390 * CCER CC4P LL_TIM_IC_Config\n
3391 * CCER CC4NP LL_TIM_IC_Config
3392 * @param TIMx Timer instance
3393 * @param Channel This parameter can be one of the following values:
3394 * @arg @ref LL_TIM_CHANNEL_CH1
3395 * @arg @ref LL_TIM_CHANNEL_CH2
3396 * @arg @ref LL_TIM_CHANNEL_CH3
3397 * @arg @ref LL_TIM_CHANNEL_CH4
3398 * @param Configuration This parameter must be a combination of all the following values:
3399 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3400 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3401 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3402 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3403 * @retval None
3404 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3405 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3406 {
3407 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3408 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3409 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3410 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3411 << SHIFT_TAB_ICxx[iChannel]);
3412 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3413 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3414 }
3415
3416 /**
3417 * @brief Set the active input.
3418 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3419 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3420 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3421 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3422 * @param TIMx Timer instance
3423 * @param Channel This parameter can be one of the following values:
3424 * @arg @ref LL_TIM_CHANNEL_CH1
3425 * @arg @ref LL_TIM_CHANNEL_CH2
3426 * @arg @ref LL_TIM_CHANNEL_CH3
3427 * @arg @ref LL_TIM_CHANNEL_CH4
3428 * @param ICActiveInput This parameter can be one of the following values:
3429 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3430 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3431 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3432 * @retval None
3433 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3434 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3435 {
3436 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3437 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3438 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3439 }
3440
3441 /**
3442 * @brief Get the current active input.
3443 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3444 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3445 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3446 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3447 * @param TIMx Timer instance
3448 * @param Channel This parameter can be one of the following values:
3449 * @arg @ref LL_TIM_CHANNEL_CH1
3450 * @arg @ref LL_TIM_CHANNEL_CH2
3451 * @arg @ref LL_TIM_CHANNEL_CH3
3452 * @arg @ref LL_TIM_CHANNEL_CH4
3453 * @retval Returned value can be one of the following values:
3454 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3455 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3456 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3457 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3458 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3459 {
3460 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3461 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3462 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3463 }
3464
3465 /**
3466 * @brief Set the prescaler of input channel.
3467 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3468 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3469 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3470 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3471 * @param TIMx Timer instance
3472 * @param Channel This parameter can be one of the following values:
3473 * @arg @ref LL_TIM_CHANNEL_CH1
3474 * @arg @ref LL_TIM_CHANNEL_CH2
3475 * @arg @ref LL_TIM_CHANNEL_CH3
3476 * @arg @ref LL_TIM_CHANNEL_CH4
3477 * @param ICPrescaler This parameter can be one of the following values:
3478 * @arg @ref LL_TIM_ICPSC_DIV1
3479 * @arg @ref LL_TIM_ICPSC_DIV2
3480 * @arg @ref LL_TIM_ICPSC_DIV4
3481 * @arg @ref LL_TIM_ICPSC_DIV8
3482 * @retval None
3483 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3484 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3485 {
3486 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3487 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3488 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3489 }
3490
3491 /**
3492 * @brief Get the current prescaler value acting on an input channel.
3493 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3494 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3495 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3496 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3497 * @param TIMx Timer instance
3498 * @param Channel This parameter can be one of the following values:
3499 * @arg @ref LL_TIM_CHANNEL_CH1
3500 * @arg @ref LL_TIM_CHANNEL_CH2
3501 * @arg @ref LL_TIM_CHANNEL_CH3
3502 * @arg @ref LL_TIM_CHANNEL_CH4
3503 * @retval Returned value can be one of the following values:
3504 * @arg @ref LL_TIM_ICPSC_DIV1
3505 * @arg @ref LL_TIM_ICPSC_DIV2
3506 * @arg @ref LL_TIM_ICPSC_DIV4
3507 * @arg @ref LL_TIM_ICPSC_DIV8
3508 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3509 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3510 {
3511 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3512 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3513 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3514 }
3515
3516 /**
3517 * @brief Set the input filter duration.
3518 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3519 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3520 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3521 * CCMR2 IC4F LL_TIM_IC_SetFilter
3522 * @param TIMx Timer instance
3523 * @param Channel This parameter can be one of the following values:
3524 * @arg @ref LL_TIM_CHANNEL_CH1
3525 * @arg @ref LL_TIM_CHANNEL_CH2
3526 * @arg @ref LL_TIM_CHANNEL_CH3
3527 * @arg @ref LL_TIM_CHANNEL_CH4
3528 * @param ICFilter This parameter can be one of the following values:
3529 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3530 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3531 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3532 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3533 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3534 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3535 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3536 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3537 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3538 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3539 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3540 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3541 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3542 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3543 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3544 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3545 * @retval None
3546 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3547 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3548 {
3549 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3550 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3551 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3552 }
3553
3554 /**
3555 * @brief Get the input filter duration.
3556 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3557 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3558 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3559 * CCMR2 IC4F LL_TIM_IC_GetFilter
3560 * @param TIMx Timer instance
3561 * @param Channel This parameter can be one of the following values:
3562 * @arg @ref LL_TIM_CHANNEL_CH1
3563 * @arg @ref LL_TIM_CHANNEL_CH2
3564 * @arg @ref LL_TIM_CHANNEL_CH3
3565 * @arg @ref LL_TIM_CHANNEL_CH4
3566 * @retval Returned value can be one of the following values:
3567 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3568 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3569 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3570 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3571 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3572 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3573 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3574 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3575 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3576 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3577 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3578 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3579 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3580 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3581 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3582 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3583 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3584 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3585 {
3586 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3587 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3588 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3589 }
3590
3591 /**
3592 * @brief Set the input channel polarity.
3593 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3594 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3595 * CCER CC2P LL_TIM_IC_SetPolarity\n
3596 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3597 * CCER CC3P LL_TIM_IC_SetPolarity\n
3598 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3599 * CCER CC4P LL_TIM_IC_SetPolarity\n
3600 * CCER CC4NP LL_TIM_IC_SetPolarity
3601 * @param TIMx Timer instance
3602 * @param Channel This parameter can be one of the following values:
3603 * @arg @ref LL_TIM_CHANNEL_CH1
3604 * @arg @ref LL_TIM_CHANNEL_CH2
3605 * @arg @ref LL_TIM_CHANNEL_CH3
3606 * @arg @ref LL_TIM_CHANNEL_CH4
3607 * @param ICPolarity This parameter can be one of the following values:
3608 * @arg @ref LL_TIM_IC_POLARITY_RISING
3609 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3610 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3611 * @retval None
3612 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3613 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3614 {
3615 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3616 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3617 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3618 }
3619
3620 /**
3621 * @brief Get the current input channel polarity.
3622 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3623 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3624 * CCER CC2P LL_TIM_IC_GetPolarity\n
3625 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3626 * CCER CC3P LL_TIM_IC_GetPolarity\n
3627 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3628 * CCER CC4P LL_TIM_IC_GetPolarity\n
3629 * CCER CC4NP LL_TIM_IC_GetPolarity
3630 * @param TIMx Timer instance
3631 * @param Channel This parameter can be one of the following values:
3632 * @arg @ref LL_TIM_CHANNEL_CH1
3633 * @arg @ref LL_TIM_CHANNEL_CH2
3634 * @arg @ref LL_TIM_CHANNEL_CH3
3635 * @arg @ref LL_TIM_CHANNEL_CH4
3636 * @retval Returned value can be one of the following values:
3637 * @arg @ref LL_TIM_IC_POLARITY_RISING
3638 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3639 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3640 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3641 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3642 {
3643 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3644 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3645 SHIFT_TAB_CCxP[iChannel]);
3646 }
3647
3648 /**
3649 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3650 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3651 * a timer instance provides an XOR input.
3652 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3653 * @param TIMx Timer instance
3654 * @retval None
3655 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3656 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3657 {
3658 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3659 }
3660
3661 /**
3662 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3663 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3664 * a timer instance provides an XOR input.
3665 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3666 * @param TIMx Timer instance
3667 * @retval None
3668 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3669 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3670 {
3671 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3672 }
3673
3674 /**
3675 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3676 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3677 * a timer instance provides an XOR input.
3678 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3679 * @param TIMx Timer instance
3680 * @retval State of bit (1 or 0).
3681 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3682 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3683 {
3684 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3685 }
3686
3687 /**
3688 * @brief Get captured value for input channel 1.
3689 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3690 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3691 * whether or not a timer instance supports a 32 bits counter.
3692 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3693 * input channel 1 is supported by a timer instance.
3694 * @note If dithering is activated, pay attention to the returned value interpretation.
3695 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3696 * @param TIMx Timer instance
3697 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3698 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3699 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3700 {
3701 return (uint32_t)(READ_REG(TIMx->CCR1));
3702 }
3703
3704 /**
3705 * @brief Get captured value for input channel 2.
3706 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3707 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3708 * whether or not a timer instance supports a 32 bits counter.
3709 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3710 * input channel 2 is supported by a timer instance.
3711 * @note If dithering is activated, pay attention to the returned value interpretation.
3712 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3713 * @param TIMx Timer instance
3714 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3715 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3716 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3717 {
3718 return (uint32_t)(READ_REG(TIMx->CCR2));
3719 }
3720
3721 /**
3722 * @brief Get captured value for input channel 3.
3723 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3724 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3725 * whether or not a timer instance supports a 32 bits counter.
3726 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3727 * input channel 3 is supported by a timer instance.
3728 * @note If dithering is activated, pay attention to the returned value interpretation.
3729 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3730 * @param TIMx Timer instance
3731 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3732 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3733 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3734 {
3735 return (uint32_t)(READ_REG(TIMx->CCR3));
3736 }
3737
3738 /**
3739 * @brief Get captured value for input channel 4.
3740 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3741 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3742 * whether or not a timer instance supports a 32 bits counter.
3743 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3744 * input channel 4 is supported by a timer instance.
3745 * @note If dithering is activated, pay attention to the returned value interpretation.
3746 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3747 * @param TIMx Timer instance
3748 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3749 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3750 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3751 {
3752 return (uint32_t)(READ_REG(TIMx->CCR4));
3753 }
3754
3755 /**
3756 * @}
3757 */
3758
3759 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3760 * @{
3761 */
3762 /**
3763 * @brief Enable external clock mode 2.
3764 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3765 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3766 * whether or not a timer instance supports external clock mode2.
3767 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3768 * @param TIMx Timer instance
3769 * @retval None
3770 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3771 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3772 {
3773 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3774 }
3775
3776 /**
3777 * @brief Disable external clock mode 2.
3778 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3779 * whether or not a timer instance supports external clock mode2.
3780 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3781 * @param TIMx Timer instance
3782 * @retval None
3783 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3784 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3785 {
3786 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3787 }
3788
3789 /**
3790 * @brief Indicate whether external clock mode 2 is enabled.
3791 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3792 * whether or not a timer instance supports external clock mode2.
3793 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3794 * @param TIMx Timer instance
3795 * @retval State of bit (1 or 0).
3796 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3797 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3798 {
3799 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3800 }
3801
3802 /**
3803 * @brief Set the clock source of the counter clock.
3804 * @note when selected clock source is external clock mode 1, the timer input
3805 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3806 * function. This timer input must be configured by calling
3807 * the @ref LL_TIM_IC_Config() function.
3808 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3809 * whether or not a timer instance supports external clock mode1.
3810 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3811 * whether or not a timer instance supports external clock mode2.
3812 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3813 * SMCR ECE LL_TIM_SetClockSource
3814 * @param TIMx Timer instance
3815 * @param ClockSource This parameter can be one of the following values:
3816 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3817 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3818 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3819 * @retval None
3820 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3821 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3822 {
3823 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3824 }
3825
3826 /**
3827 * @brief Set the encoder interface mode.
3828 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3829 * whether or not a timer instance supports the encoder mode.
3830 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3831 * @param TIMx Timer instance
3832 * @param EncoderMode This parameter can be one of the following values:
3833 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3834 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3835 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3836 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3837 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3838 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3839 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3840 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3841 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3842 * @retval None
3843 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3844 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3845 {
3846 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3847 }
3848
3849 /**
3850 * @}
3851 */
3852
3853 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3854 * @{
3855 */
3856 /**
3857 * @brief Set the trigger output (TRGO) used for timer synchronization .
3858 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3859 * whether or not a timer instance can operate as a master timer.
3860 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3861 * @param TIMx Timer instance
3862 * @param TimerSynchronization This parameter can be one of the following values:
3863 * @arg @ref LL_TIM_TRGO_RESET
3864 * @arg @ref LL_TIM_TRGO_ENABLE
3865 * @arg @ref LL_TIM_TRGO_UPDATE
3866 * @arg @ref LL_TIM_TRGO_CC1IF
3867 * @arg @ref LL_TIM_TRGO_OC1REF
3868 * @arg @ref LL_TIM_TRGO_OC2REF
3869 * @arg @ref LL_TIM_TRGO_OC3REF
3870 * @arg @ref LL_TIM_TRGO_OC4REF
3871 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3872 * @retval None
3873 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3874 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3875 {
3876 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3877 }
3878
3879 /**
3880 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3881 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3882 * whether or not a timer instance can be used for ADC synchronization.
3883 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3884 * @param TIMx Timer Instance
3885 * @param ADCSynchronization This parameter can be one of the following values:
3886 * @arg @ref LL_TIM_TRGO2_RESET
3887 * @arg @ref LL_TIM_TRGO2_ENABLE
3888 * @arg @ref LL_TIM_TRGO2_UPDATE
3889 * @arg @ref LL_TIM_TRGO2_CC1F
3890 * @arg @ref LL_TIM_TRGO2_OC1
3891 * @arg @ref LL_TIM_TRGO2_OC2
3892 * @arg @ref LL_TIM_TRGO2_OC3
3893 * @arg @ref LL_TIM_TRGO2_OC4
3894 * @arg @ref LL_TIM_TRGO2_OC5
3895 * @arg @ref LL_TIM_TRGO2_OC6
3896 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3897 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3898 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3899 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3900 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3901 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3902 * @retval None
3903 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3904 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3905 {
3906 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3907 }
3908
3909 /**
3910 * @brief Set the synchronization mode of a slave timer.
3911 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3912 * a timer instance can operate as a slave timer.
3913 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3914 * @param TIMx Timer instance
3915 * @param SlaveMode This parameter can be one of the following values:
3916 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3917 * @arg @ref LL_TIM_SLAVEMODE_RESET
3918 * @arg @ref LL_TIM_SLAVEMODE_GATED
3919 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3920 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3921 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3922 * @retval None
3923 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3924 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3925 {
3926 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3927 }
3928
3929 /**
3930 * @brief Set the selects the trigger input to be used to synchronize the counter.
3931 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3932 * a timer instance can operate as a slave timer.
3933 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3934 * @param TIMx Timer instance
3935 * @param TriggerInput This parameter can be one of the following values:
3936 * @arg @ref LL_TIM_TS_ITR0
3937 * @arg @ref LL_TIM_TS_ITR1
3938 * @arg @ref LL_TIM_TS_ITR2
3939 * @arg @ref LL_TIM_TS_ITR3
3940 * @arg @ref LL_TIM_TS_ITR4
3941 * @arg @ref LL_TIM_TS_ITR5
3942 * @arg @ref LL_TIM_TS_ITR6
3943 * @arg @ref LL_TIM_TS_ITR7
3944 * @arg @ref LL_TIM_TS_ITR8
3945 * @arg @ref LL_TIM_TS_ITR11
3946 * @arg @ref LL_TIM_TS_TI1F_ED
3947 * @arg @ref LL_TIM_TS_TI1FP1
3948 * @arg @ref LL_TIM_TS_TI2FP2
3949 * @arg @ref LL_TIM_TS_ETRF
3950 * @retval None
3951 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3952 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3953 {
3954 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3955 }
3956
3957 /**
3958 * @brief Enable the Master/Slave mode.
3959 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3960 * a timer instance can operate as a slave timer.
3961 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3962 * @param TIMx Timer instance
3963 * @retval None
3964 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3965 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3966 {
3967 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3968 }
3969
3970 /**
3971 * @brief Disable the Master/Slave mode.
3972 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3973 * a timer instance can operate as a slave timer.
3974 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3975 * @param TIMx Timer instance
3976 * @retval None
3977 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3978 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3979 {
3980 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3981 }
3982
3983 /**
3984 * @brief Indicates whether the Master/Slave mode is enabled.
3985 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3986 * a timer instance can operate as a slave timer.
3987 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3988 * @param TIMx Timer instance
3989 * @retval State of bit (1 or 0).
3990 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3991 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3992 {
3993 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3994 }
3995
3996 /**
3997 * @brief Configure the external trigger (ETR) input.
3998 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3999 * a timer instance provides an external trigger input.
4000 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
4001 * SMCR ETPS LL_TIM_ConfigETR\n
4002 * SMCR ETF LL_TIM_ConfigETR
4003 * @param TIMx Timer instance
4004 * @param ETRPolarity This parameter can be one of the following values:
4005 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
4006 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
4007 * @param ETRPrescaler This parameter can be one of the following values:
4008 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
4009 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
4010 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
4011 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
4012 * @param ETRFilter This parameter can be one of the following values:
4013 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
4014 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
4015 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
4016 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
4017 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
4018 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
4019 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
4020 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
4021 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
4022 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
4023 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
4024 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
4025 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
4026 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
4027 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
4028 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
4029 * @retval None
4030 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)4031 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
4032 uint32_t ETRFilter)
4033 {
4034 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
4035 }
4036
4037 /**
4038 * @brief Select the external trigger (ETR) input source.
4039 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
4040 * not a timer instance supports ETR source selection.
4041 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
4042 * @param TIMx Timer instance
4043 * @param ETRSource This parameter can be one of the following values:
4044 *
4045 * TIM1: any combination of ETR_RMP where
4046 *
4047 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
4048 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
4049 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*)
4050 * @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIK
4051 * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI
4052 * @arg @ref LL_TIM_TIM1_ETRSOURCE_MSIS
4053 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (*)
4054 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 (*)
4055 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
4056 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
4057 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
4058 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1
4059 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2
4060 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3
4061 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (*)
4062 *
4063 * TIM2: any combination of ETR_RMP where
4064 *
4065 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
4066 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
4067 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*)
4068 * @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIK
4069 * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI
4070 * @arg @ref LL_TIM_TIM2_ETRSOURCE_MSIS
4071 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMI_VSYNC (*)
4072 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_VSYNC (*)
4073 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
4074 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
4075 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
4076 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
4077 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DSI_TE (*)
4078 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMI_HSYNC (*)
4079 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LTDC_HSYNC (*)
4080 *
4081 * TIM3: any combination of ETR_RMP where
4082 *
4083 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
4084 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
4085 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*)
4086 * @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIK
4087 * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI
4088 * @arg @ref LL_TIM_TIM3_ETRSOURCE_MSIS
4089 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMI_VSYNC (*)
4090 * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_VSYNC (*)
4091 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
4092 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
4093 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DSI_TE (*)
4094 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD1
4095 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD2
4096 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC1_AWD3
4097 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMI_HSYNC (*)
4098 * @arg @ref LL_TIM_TIM3_ETRSOURCE_LTDC_HSYNC (*)
4099 *
4100 * TIM4: any combination of ETR_RMP where
4101 *
4102 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
4103 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
4104 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2 (*)
4105 * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIK
4106 * @arg @ref LL_TIM_TIM4_ETRSOURCE_HSI
4107 * @arg @ref LL_TIM_TIM4_ETRSOURCE_MSIS
4108 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMI_VSYNC (*)
4109 * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_VSYNC (*)
4110 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
4111 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
4112 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DSI_TE (*)
4113 * @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD1 (*)
4114 * @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD2 (*)
4115 * @arg @ref LL_TIM_TIM4_ETRSOURCE_ADC2_AWD3 (*)
4116 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMI_HSYNC (*)
4117 * @arg @ref LL_TIM_TIM4_ETRSOURCE_LTDC_HSYNC (*)
4118 *
4119 * TIM5: any combination of ETR_RMP where
4120 *
4121 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
4122 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1
4123 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
4124 * @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIK
4125 * @arg @ref LL_TIM_TIM5_ETRSOURCE_HSI
4126 * @arg @ref LL_TIM_TIM5_ETRSOURCE_MSIS
4127 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMI_VSYNC (*)
4128 * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_VSYNC (*)
4129 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
4130 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
4131 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DSI_TE (*)
4132 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMI_HSYNC (*)
4133 * @arg @ref LL_TIM_TIM5_ETRSOURCE_LTDC_HSYNC (*)
4134 *
4135 * TIM8: any combination of ETR_RMP where
4136 *
4137 * . . ETR_RMP can be one of the following values
4138 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
4139 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
4140 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2 (*)
4141 * @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIK
4142 * @arg @ref LL_TIM_TIM8_ETRSOURCE_HSI
4143 * @arg @ref LL_TIM_TIM8_ETRSOURCE_MSIS
4144 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (*)
4145 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (*)
4146 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD1
4147 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD2
4148 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC1_AWD3
4149 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD1
4150 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD2
4151 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC4_AWD3
4152 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (*)
4153 *
4154 * (*) Value not defined in all devices. \n
4155 * @retval None
4156 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)4157 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
4158 {
4159 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
4160 }
4161
4162 /**
4163 * @brief Enable SMS preload.
4164 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4165 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4166 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
4167 * @param TIMx Timer instance
4168 * @retval None
4169 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)4170 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
4171 {
4172 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4173 }
4174
4175 /**
4176 * @brief Disable SMS preload.
4177 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4178 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4179 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
4180 * @param TIMx Timer instance
4181 * @retval None
4182 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)4183 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
4184 {
4185 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4186 }
4187
4188 /**
4189 * @brief Indicate whether SMS preload is enabled.
4190 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4191 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4192 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
4193 * @param TIMx Timer instance
4194 * @retval State of bit (1 or 0).
4195 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)4196 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
4197 {
4198 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4199 }
4200
4201 /**
4202 * @brief Set the preload source of SMS.
4203 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4204 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4205 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4206 * @param TIMx Timer instance
4207 * @param PreloadSource This parameter can be one of the following values:
4208 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4209 * @arg @ref LL_TIM_SMSPS_INDEX
4210 * @retval None
4211 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4212 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4213 {
4214 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4215 }
4216
4217 /**
4218 * @brief Get the preload source of SMS.
4219 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4220 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4221 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4222 * @param TIMx Timer instance
4223 * @retval Returned value can be one of the following values:
4224 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4225 * @arg @ref LL_TIM_SMSPS_INDEX
4226 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)4227 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
4228 {
4229 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4230 }
4231
4232 /**
4233 * @}
4234 */
4235
4236 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4237 * @{
4238 */
4239 /**
4240 * @brief Enable the break function.
4241 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4242 * a timer instance provides a break input.
4243 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4244 * @param TIMx Timer instance
4245 * @retval None
4246 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4247 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4248 {
4249 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4250 }
4251
4252 /**
4253 * @brief Disable the break function.
4254 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4255 * @param TIMx Timer instance
4256 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4257 * a timer instance provides a break input.
4258 * @retval None
4259 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4260 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4261 {
4262 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4263 }
4264
4265 /**
4266 * @brief Configure the break input.
4267 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4268 * a timer instance provides a break input.
4269 * @note Bidirectional mode is only supported by advanced timer instances.
4270 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4271 * a timer instance is an advanced-control timer.
4272 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4273 * in input mode and in open drain output mode. Any active Break event will
4274 * assert a low logic level on the Break input to indicate an internal break
4275 * event to external devices.
4276 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4277 * LL_TIM_BREAK_AFMODE_INPUT.
4278 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4279 * BDTR BKF LL_TIM_ConfigBRK\n
4280 * BDTR BKBID LL_TIM_ConfigBRK
4281 * @param TIMx Timer instance
4282 * @param BreakPolarity This parameter can be one of the following values:
4283 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4284 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4285 * @param BreakFilter This parameter can be one of the following values:
4286 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4287 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4288 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4289 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4290 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4291 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4292 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4293 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4294 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4295 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4296 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4297 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4298 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4299 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4300 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4301 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4302 * @param BreakAFMode This parameter can be one of the following values:
4303 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4304 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4305 * @retval None
4306 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4307 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4308 uint32_t BreakAFMode)
4309 {
4310 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4311 }
4312
4313 /**
4314 * @brief Disarm the break input (when it operates in bidirectional mode).
4315 * @note The break input can be disarmed only when it is configured in
4316 * bidirectional mode and when when MOE is reset.
4317 * @note Purpose is to be able to have the input voltage back to high-state,
4318 * whatever the time constant on the output .
4319 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4320 * @param TIMx Timer instance
4321 * @retval None
4322 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4323 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4324 {
4325 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4326 }
4327
4328 /**
4329 * @brief Enable the break 2 function.
4330 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4331 * a timer instance provides a second break input.
4332 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4333 * @param TIMx Timer instance
4334 * @retval None
4335 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4336 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4337 {
4338 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4339 }
4340
4341 /**
4342 * @brief Disable the break 2 function.
4343 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4344 * a timer instance provides a second break input.
4345 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4346 * @param TIMx Timer instance
4347 * @retval None
4348 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4349 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4350 {
4351 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4352 }
4353
4354 /**
4355 * @brief Configure the break 2 input.
4356 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4357 * a timer instance provides a second break input.
4358 * @note Bidirectional mode is only supported by advanced timer instances.
4359 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4360 * a timer instance is an advanced-control timer.
4361 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4362 * in input mode and in open drain output mode. Any active Break event will
4363 * assert a low logic level on the Break 2 input to indicate an internal break
4364 * event to external devices.
4365 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4366 * LL_TIM_BREAK2_AFMODE_INPUT.
4367 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4368 * BDTR BK2F LL_TIM_ConfigBRK2\n
4369 * BDTR BK2BID LL_TIM_ConfigBRK2
4370 * @param TIMx Timer instance
4371 * @param Break2Polarity This parameter can be one of the following values:
4372 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4373 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4374 * @param Break2Filter This parameter can be one of the following values:
4375 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4376 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4377 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4378 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4379 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4380 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4381 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4382 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4383 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4384 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4385 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4386 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4387 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4388 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4389 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4390 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4391 * @param Break2AFMode This parameter can be one of the following values:
4392 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4393 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4394 * @retval None
4395 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4396 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4397 uint32_t Break2AFMode)
4398 {
4399 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4400 }
4401
4402 /**
4403 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4404 * @note The break 2 input can be disarmed only when it is configured in
4405 * bidirectional mode and when when MOE is reset.
4406 * @note Purpose is to be able to have the input voltage back to high-state,
4407 * whatever the time constant on the output.
4408 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4409 * @param TIMx Timer instance
4410 * @retval None
4411 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4412 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4413 {
4414 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4415 }
4416
4417 /**
4418 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4419 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4420 * a timer instance provides a break input.
4421 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4422 * BDTR OSSR LL_TIM_SetOffStates
4423 * @param TIMx Timer instance
4424 * @param OffStateIdle This parameter can be one of the following values:
4425 * @arg @ref LL_TIM_OSSI_DISABLE
4426 * @arg @ref LL_TIM_OSSI_ENABLE
4427 * @param OffStateRun This parameter can be one of the following values:
4428 * @arg @ref LL_TIM_OSSR_DISABLE
4429 * @arg @ref LL_TIM_OSSR_ENABLE
4430 * @retval None
4431 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4432 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4433 {
4434 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4435 }
4436
4437 /**
4438 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4439 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4440 * a timer instance provides a break input.
4441 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4442 * @param TIMx Timer instance
4443 * @retval None
4444 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4445 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4446 {
4447 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4448 }
4449
4450 /**
4451 * @brief Disable automatic output (MOE can be set only by software).
4452 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4453 * a timer instance provides a break input.
4454 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4455 * @param TIMx Timer instance
4456 * @retval None
4457 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4458 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4459 {
4460 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4461 }
4462
4463 /**
4464 * @brief Indicate whether automatic output is enabled.
4465 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4466 * a timer instance provides a break input.
4467 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4468 * @param TIMx Timer instance
4469 * @retval State of bit (1 or 0).
4470 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4471 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4472 {
4473 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4474 }
4475
4476 /**
4477 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4478 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4479 * software and is reset in case of break or break2 event
4480 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4481 * a timer instance provides a break input.
4482 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4483 * @param TIMx Timer instance
4484 * @retval None
4485 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4486 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4487 {
4488 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4489 }
4490
4491 /**
4492 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4493 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4494 * software and is reset in case of break or break2 event.
4495 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4496 * a timer instance provides a break input.
4497 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4498 * @param TIMx Timer instance
4499 * @retval None
4500 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4501 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4502 {
4503 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4504 }
4505
4506 /**
4507 * @brief Indicates whether outputs are enabled.
4508 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4509 * a timer instance provides a break input.
4510 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4511 * @param TIMx Timer instance
4512 * @retval State of bit (1 or 0).
4513 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4514 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4515 {
4516 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4517 }
4518
4519 /**
4520 * @brief Enable the signals connected to the designated timer break input.
4521 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4522 * or not a timer instance allows for break input selection.
4523 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4524 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4525 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4526 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
4527 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4528 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4529 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4530 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource
4531 * @param TIMx Timer instance
4532 * @param BreakInput This parameter can be one of the following values:
4533 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4534 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4535 * @param Source This parameter can be one of the following values:
4536 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4537 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4538 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
4539 * @arg @ref LL_TIM_BKIN_SOURCE_MDF1
4540 *
4541 * (*) Value not defined in all devices.
4542 * @retval None
4543 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4544 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4545 {
4546 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4547 SET_BIT(*pReg, Source);
4548 }
4549
4550 /**
4551 * @brief Disable the signals connected to the designated timer break input.
4552 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4553 * or not a timer instance allows for break input selection.
4554 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4555 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4556 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4557 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
4558 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4559 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4560 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
4561 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource
4562 * @param TIMx Timer instance
4563 * @param BreakInput This parameter can be one of the following values:
4564 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4565 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4566 * @param Source This parameter can be one of the following values:
4567 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4568 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4569 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
4570 * @arg @ref LL_TIM_BKIN_SOURCE_MDF1
4571 *
4572 * (*) Value not defined in all devices.
4573 * @retval None
4574 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4575 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4576 {
4577 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4578 CLEAR_BIT(*pReg, Source);
4579 }
4580
4581 /**
4582 * @brief Set the polarity of the break signal for the timer break input.
4583 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4584 * or not a timer instance allows for break input selection.
4585 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4586 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4587 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4588 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4589 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4590 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
4591 * @param TIMx Timer instance
4592 * @param BreakInput This parameter can be one of the following values:
4593 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4594 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4595 * @param Source This parameter can be one of the following values:
4596 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4597 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4598 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 (*)
4599 * @param Polarity This parameter can be one of the following values:
4600 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4601 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4602 *
4603 * (*) Value not defined in all devices.
4604 * @retval None
4605 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4606 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4607 uint32_t Polarity)
4608 {
4609 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4610 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4611 }
4612 /**
4613 * @brief Enable asymmetrical deadtime.
4614 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4615 * a timer instance provides asymmetrical deadtime.
4616 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4617 * @param TIMx Timer instance
4618 * @retval None
4619 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4620 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4621 {
4622 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4623 }
4624
4625 /**
4626 * @brief Disable asymmetrical dead-time.
4627 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4628 * a timer instance provides asymmetrical deadtime.
4629 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4630 * @param TIMx Timer instance
4631 * @retval None
4632 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4633 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4634 {
4635 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4636 }
4637
4638 /**
4639 * @brief Indicates whether asymmetrical deadtime is activated.
4640 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4641 * a timer instance provides asymmetrical deadtime.
4642 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4643 * @param TIMx Timer instance
4644 * @retval State of bit (1 or 0).
4645 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4646 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4647 {
4648 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4649 }
4650
4651 /**
4652 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4653 * rising edge of OCxN signals).
4654 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4655 * asymmetrical dead-time insertion feature is supported by a timer instance.
4656 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4657 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4658 * (LOCK bits in TIMx_BDTR register).
4659 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4660 * @param TIMx Timer instance
4661 * @param DeadTime between Min_Data=0 and Max_Data=255
4662 * @retval None
4663 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4664 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4665 {
4666 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4667 }
4668
4669 /**
4670 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4671 * the rising edge of OCxN signals).
4672 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4673 * asymmetrical dead-time insertion feature is supported by a timer instance.
4674 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4675 * (LOCK bits in TIMx_BDTR register).
4676 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4677 * @param TIMx Timer instance
4678 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4679 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4680 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4681 {
4682 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4683 }
4684
4685 /**
4686 * @brief Enable deadtime preload.
4687 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4688 * a timer instance provides deadtime preload.
4689 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4690 * @param TIMx Timer instance
4691 * @retval None
4692 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4693 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4694 {
4695 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4696 }
4697
4698 /**
4699 * @brief Disable dead-time preload.
4700 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4701 * a timer instance provides deadtime preload.
4702 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4703 * @param TIMx Timer instance
4704 * @retval None
4705 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4706 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4707 {
4708 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4709 }
4710
4711 /**
4712 * @brief Indicates whether deadtime preload is activated.
4713 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4714 * a timer instance provides deadtime preload.
4715 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4716 * @param TIMx Timer instance
4717 * @retval State of bit (1 or 0).
4718 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4719 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4720 {
4721 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4722 }
4723
4724 /**
4725 * @}
4726 */
4727
4728 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4729 * @{
4730 */
4731 /**
4732 * @brief Configures the timer DMA burst feature.
4733 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4734 * not a timer instance supports the DMA burst mode.
4735 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4736 * DCR DBA LL_TIM_ConfigDMABurst
4737 * @param TIMx Timer instance
4738 * @param DMABurstBaseAddress This parameter can be one of the following values:
4739 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4740 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4741 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4742 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4743 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4744 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4745 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4746 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4747 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4748 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4749 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4750 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4751 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4752 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4753 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4754 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4755 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4756 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4757 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4758 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4759 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4760 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4761 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4762 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4763 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4764 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4765 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
4766 * @param DMABurstLength This parameter can be one of the following values:
4767 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4768 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4769 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4770 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4771 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4772 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4773 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4774 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4775 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4776 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4777 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4778 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4779 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4780 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4781 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4782 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4783 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4784 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4785 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4786 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4787 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4788 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4789 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4790 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4791 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4792 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4793 * @param DMABurstSource This parameter can be one of the following values:
4794 * @arg @ref LL_TIM_DMA_UPDATE
4795 * @arg @ref LL_TIM_DMA_CC1
4796 * @arg @ref LL_TIM_DMA_CC2
4797 * @arg @ref LL_TIM_DMA_CC3
4798 * @arg @ref LL_TIM_DMA_CC4
4799 * @arg @ref LL_TIM_DMA_COM
4800 * @arg @ref LL_TIM_DMA_TRIGGER
4801 * @retval None
4802 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4803 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4804 uint32_t DMABurstSource)
4805 {
4806 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4807 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4808 }
4809
4810 /**
4811 * @}
4812 */
4813
4814 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4815 * @{
4816 */
4817
4818 /**
4819 * @brief Enable encoder index.
4820 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4821 * a timer instance provides an index input.
4822 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4823 * @param TIMx Timer instance
4824 * @retval None
4825 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4826 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4827 {
4828 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4829 }
4830
4831 /**
4832 * @brief Disable encoder index.
4833 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4834 * a timer instance provides an index input.
4835 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4836 * @param TIMx Timer instance
4837 * @retval None
4838 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4839 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4840 {
4841 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4842 }
4843
4844 /**
4845 * @brief Indicate whether encoder index is enabled.
4846 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4847 * a timer instance provides an index input.
4848 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4849 * @param TIMx Timer instance
4850 * @retval State of bit (1 or 0).
4851 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4852 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4853 {
4854 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4855 }
4856
4857 /**
4858 * @brief Set index direction
4859 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4860 * a timer instance provides an index input.
4861 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4862 * @param TIMx Timer instance
4863 * @param IndexDirection This parameter can be one of the following values:
4864 * @arg @ref LL_TIM_INDEX_UP_DOWN
4865 * @arg @ref LL_TIM_INDEX_UP
4866 * @arg @ref LL_TIM_INDEX_DOWN
4867 * @retval None
4868 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4869 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4870 {
4871 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4872 }
4873
4874 /**
4875 * @brief Get actual index direction
4876 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4877 * a timer instance provides an index input.
4878 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4879 * @param TIMx Timer instance
4880 * @retval Returned value can be one of the following values:
4881 * @arg @ref LL_TIM_INDEX_UP_DOWN
4882 * @arg @ref LL_TIM_INDEX_UP
4883 * @arg @ref LL_TIM_INDEX_DOWN
4884 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4885 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4886 {
4887 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4888 }
4889
4890 /**
4891 * @brief Set index blanking
4892 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4893 * a timer instance provides an index input.
4894 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4895 * @param TIMx Timer instance
4896 * @param Indexblanking This parameter can be one of the following values:
4897 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4898 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4899 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4900 * @retval None
4901 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4902 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4903 {
4904 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4905 }
4906
4907 /**
4908 * @brief Get actual index blanking
4909 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4910 * a timer instance provides an index input.
4911 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4912 * @param TIMx Timer instance
4913 * @retval Returned value can be one of the following values:
4914 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4915 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4916 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4917 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4918 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4919 {
4920 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4921 }
4922
4923
4924 /**
4925 * @brief Enable first index.
4926 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4927 * a timer instance provides an index input.
4928 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4929 * @param TIMx Timer instance
4930 * @retval None
4931 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4932 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4933 {
4934 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4935 }
4936
4937 /**
4938 * @brief Disable first index.
4939 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4940 * a timer instance provides an index input.
4941 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4942 * @param TIMx Timer instance
4943 * @retval None
4944 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4945 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4946 {
4947 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4948 }
4949
4950 /**
4951 * @brief Indicates whether first index is enabled.
4952 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4953 * a timer instance provides an index input.
4954 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4955 * @param TIMx Timer instance
4956 * @retval State of bit (1 or 0).
4957 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4958 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4959 {
4960 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4961 }
4962
4963 /**
4964 * @brief Set index positioning
4965 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4966 * a timer instance provides an index input.
4967 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4968 * @param TIMx Timer instance
4969 * @param IndexPositionning This parameter can be one of the following values:
4970 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4971 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4972 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4973 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4974 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4975 * @arg @ref LL_TIM_INDEX_POSITION_UP
4976 * @retval None
4977 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4978 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4979 {
4980 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4981 }
4982
4983 /**
4984 * @brief Get actual index positioning
4985 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4986 * a timer instance provides an index input.
4987 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4988 * @param TIMx Timer instance
4989 * @retval Returned value can be one of the following values:
4990 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4991 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4992 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4993 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4994 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4995 * @arg @ref LL_TIM_INDEX_POSITION_UP
4996 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4997 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4998 {
4999 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
5000 }
5001
5002 /**
5003 * @brief Configure encoder index.
5004 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5005 * a timer instance provides an index input.
5006 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
5007 * ECR IBLK LL_TIM_ConfigIDX\n
5008 * ECR FIDX LL_TIM_ConfigIDX\n
5009 * ECR IPOS LL_TIM_ConfigIDX
5010 * @param TIMx Timer instance
5011 * @param Configuration This parameter must be a combination of all the following values:
5012 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
5013 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
5014 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
5015 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
5016 * @retval None
5017 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)5018 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
5019 {
5020 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
5021 }
5022
5023 /**
5024 * @}
5025 */
5026
5027 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
5028 * @{
5029 */
5030 /**
5031 * @brief Remap TIM inputs (input channel, internal/external triggers).
5032 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
5033 * a some timer inputs can be remapped.
5034 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
5035 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
5036 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
5037 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
5038 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
5039 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
5040 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
5041 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
5042 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
5043 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
5044 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
5045 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
5046 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
5047 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
5048 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
5049 *
5050 * @param TIMx Timer instance
5051 * @param Remap Remap param depends on the TIMx. Description available only
5052 * in CHM version of the User Manual (not in .pdf).
5053 * Otherwise see Reference Manual description of TISEL registers.
5054 *
5055 * Below description summarizes "Timer Instance" and "Remap" param combinations:
5056 *
5057 * TIM1: one of the following values:
5058 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
5059 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output
5060 * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*)
5061 *
5062 * TIM2: one of the following values:
5063 * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
5064 * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output
5065 * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output (*)
5066 * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
5067 * @arg LL_TIM_TIM2_TI2_RMP_COMP1: TIM2 TI2 is connected to COMP1 output
5068 * @arg LL_TIM_TIM2_TI2_RMP_COMP2: TIM2 TI2 is connected to COMP2 output (*)
5069 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
5070 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output
5071 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output (*)
5072 *
5073 * TIM3: one of the following values:
5074 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
5075 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output
5076 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*)
5077 * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
5078 * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output
5079 * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*)
5080 *
5081 * TIM4: one of the following values:
5082 * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO
5083 * @arg LL_TIM_TIM4_TI1_RMP_COMP1: TIM4 TI1 is connected to COMP1 output
5084 * @arg LL_TIM_TIM4_TI1_RMP_COMP2: TIM4 TI1 is connected to COMP2 output (*)
5085 * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO
5086 * @arg LL_TIM_TIM4_TI2_RMP_COMP1: TIM4 TI2 is connected to COMP1 output
5087 * @arg LL_TIM_TIM4_TI2_RMP_COMP2: TIM4 TI2 is connected to COMP2 output (*)
5088 *
5089 * TIM5: one of the following values:
5090 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
5091 * @arg LL_TIM_TIM5_TI1_RMP_LSI: TIM5 TI1 is connected to LSI
5092 * @arg LL_TIM_TIM5_TI1_RMP_LSE: TIM5 TI1 is connected to LSE
5093 * @arg LL_TIM_TIM5_TI1_RMP_RTC: TIM5 TI1 is connected to RTC Wakeup
5094 * @arg LL_TIM_TIM5_TI1_RMP_COMP1: TIM5 TI1 is connected to COMP1 output
5095 * @arg LL_TIM_TIM5_TI1_RMP_COMP2: TIM5 TI1 is connected to COMP2 output (*)
5096 * @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO
5097 * @arg LL_TIM_TIM5_TI2_RMP_COMP1: TIM5 TI2 is connected to COMP1 output
5098 * @arg LL_TIM_TIM5_TI2_RMP_COMP2: TIM5 TI2 is connected to COMP2 output (*)
5099 *
5100 * TIM8: one of the following values:
5101 * @arg TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
5102 * @arg TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output (*)
5103 *
5104 * TIM15: one of the following values:
5105 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
5106 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
5107 * @arg LL_TIM_TIM15_TI1_RMP_COMP1: TIM15 TI1 is connected to COMP1 output
5108 * @arg LL_TIM_TIM15_TI1_RMP_COMP2: TIM15 TI1 is connected to COMP2 output (*)
5109 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO
5110 * @arg LL_TIM_TIM15_TI2_RMP_COMP2: TIM15 TI2 is connected to COMP2 output (*)
5111 *
5112 * TIM16: one of the following values:
5113 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
5114 * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO
5115 * @arg LL_TIM_TIM16_TI1_RMP_HSE_DIV32: TIM16 TI1 is connected to HSE DIV32
5116 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC
5117 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
5118 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
5119 * @arg LL_TIM_TIM16_TI1_RMP_MSIS_1024: TIM16 TI1 is connected to MSIS/1024
5120 * @arg LL_TIM_TIM16_TI1_RMP_MSIS_4: TIM16 TI1 is connected to MSIS/4
5121 * @arg LL_TIM_TIM16_TI1_RMP_HSI_256: TIM16 TI1 is connected to HSI/256
5122 *
5123 * TIM17: one of the following values:
5124 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
5125 * @arg LL_TIM_TIM17_TI1_RMP_MCO: TIM17 TI1 is connected to MCO
5126 * @arg LL_TIM_TIM17_TI1_RMP_HSE_DIV32: TIM17 TI1 is connected to HSE DIV32
5127 * @arg LL_TIM_TIM17_TI1_RMP_RTC: TIM17 TI1 is connected to RTC
5128 * @arg LL_TIM_TIM17_TI1_RMP_LSE: TIM17 TI1 is connected to LSE
5129 * @arg LL_TIM_TIM17_TI1_RMP_LSI: TIM17 TI1 is connected to LSI
5130 * @arg LL_TIM_TIM17_TI1_RMP_MSIS_1024: TIM17 TI1 is connected to MSIS/1024
5131 * @arg LL_TIM_TIM17_TI1_RMP_MSIS_4: TIM17 TI1 is connected to MSIS/4
5132 * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256
5133 *
5134 * (*) Value not defined in all devices. \n
5135 * @retval None
5136 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)5137 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
5138 {
5139 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
5140 }
5141
5142 /**
5143 * @brief Enable request for HSE/32 clock used for TISEL remap.
5144 * @note Only TIM16 and TIM17 support HSE/32 remap
5145 * @note The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16
5146 * @note Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register
5147 * @rmtoll OR1 HSE32EN LL_TIM_EnableHSE32
5148 * @param TIMx Timer instance
5149 * @retval None
5150 */
LL_TIM_EnableHSE32(TIM_TypeDef * TIMx)5151 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
5152 {
5153 SET_BIT(TIMx->OR1, TIM_OR1_HSE32EN);
5154 }
5155
5156 /**
5157 * @brief Disable request for HSE/32 clock used for TISEL remap.
5158 * @note Only TIM16 and TIM17 support HSE/32 remap
5159 * @rmtoll OR1 HSE32EN LL_TIM_DisableHSE32
5160 * @param TIMx Timer instance
5161 * @retval None
5162 */
LL_TIM_DisableHSE32(TIM_TypeDef * TIMx)5163 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
5164 {
5165 CLEAR_BIT(TIMx->OR1, TIM_OR1_HSE32EN);
5166 }
5167
5168 /**
5169 * @brief Indicate whether request for HSE/32 clock is enabled.
5170 * @note Only TIM16 and TIM17 support HSE/32 remap
5171 * @rmtoll OR1 HSE32EN LL_TIM_IsEnabledHSE32
5172 * @param TIMx Timer instance
5173 * @retval State of bit (1 or 0).
5174 */
LL_TIM_IsEnabledHSE32(const TIM_TypeDef * TIMx)5175 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx)
5176 {
5177 return ((READ_BIT(TIMx->OR1, TIM_OR1_HSE32EN) == (TIM_OR1_HSE32EN)) ? 1UL : 0UL);
5178 }
5179
5180 /**
5181 * @}
5182 */
5183
5184 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
5185 * @{
5186 */
5187 /**
5188 * @brief Set the OCREF clear input source
5189 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
5190 * @note This function can only be used in Output compare and PWM modes.
5191 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
5192 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
5193 * @param TIMx Timer instance
5194 * @param OCRefClearInputSource This parameter can be one of the following values:
5195 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
5196 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
5197 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
5198 *
5199 * (*) Value not defined in all devices. \n
5200 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
5201 * @retval None
5202 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)5203 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
5204 {
5205 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
5206 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
5207 MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
5208 }
5209 /**
5210 * @}
5211 */
5212
5213 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
5214 * @{
5215 */
5216 /**
5217 * @brief Clear the update interrupt flag (UIF).
5218 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5219 * @param TIMx Timer instance
5220 * @retval None
5221 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5222 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5223 {
5224 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5225 }
5226
5227 /**
5228 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5229 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5230 * @param TIMx Timer instance
5231 * @retval State of bit (1 or 0).
5232 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)5233 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
5234 {
5235 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5236 }
5237
5238 /**
5239 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5240 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5241 * @param TIMx Timer instance
5242 * @retval None
5243 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5244 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5245 {
5246 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5247 }
5248
5249 /**
5250 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5251 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5252 * @param TIMx Timer instance
5253 * @retval State of bit (1 or 0).
5254 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)5255 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
5256 {
5257 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5258 }
5259
5260 /**
5261 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5262 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5263 * @param TIMx Timer instance
5264 * @retval None
5265 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5266 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5267 {
5268 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5269 }
5270
5271 /**
5272 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5273 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5274 * @param TIMx Timer instance
5275 * @retval State of bit (1 or 0).
5276 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)5277 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
5278 {
5279 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5280 }
5281
5282 /**
5283 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5284 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5285 * @param TIMx Timer instance
5286 * @retval None
5287 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5288 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5289 {
5290 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5291 }
5292
5293 /**
5294 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5295 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5296 * @param TIMx Timer instance
5297 * @retval State of bit (1 or 0).
5298 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)5299 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
5300 {
5301 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5302 }
5303
5304 /**
5305 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5306 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5307 * @param TIMx Timer instance
5308 * @retval None
5309 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5310 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5311 {
5312 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5313 }
5314
5315 /**
5316 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5317 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5318 * @param TIMx Timer instance
5319 * @retval State of bit (1 or 0).
5320 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)5321 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
5322 {
5323 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5324 }
5325
5326 /**
5327 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5328 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5329 * @param TIMx Timer instance
5330 * @retval None
5331 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5332 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5333 {
5334 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5335 }
5336
5337 /**
5338 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5339 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5340 * @param TIMx Timer instance
5341 * @retval State of bit (1 or 0).
5342 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)5343 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
5344 {
5345 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5346 }
5347
5348 /**
5349 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5350 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5351 * @param TIMx Timer instance
5352 * @retval None
5353 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5354 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5355 {
5356 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5357 }
5358
5359 /**
5360 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5361 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5362 * @param TIMx Timer instance
5363 * @retval State of bit (1 or 0).
5364 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)5365 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
5366 {
5367 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5368 }
5369
5370 /**
5371 * @brief Clear the commutation interrupt flag (COMIF).
5372 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5373 * @param TIMx Timer instance
5374 * @retval None
5375 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5376 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5377 {
5378 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5379 }
5380
5381 /**
5382 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5383 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5384 * @param TIMx Timer instance
5385 * @retval State of bit (1 or 0).
5386 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5387 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5388 {
5389 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5390 }
5391
5392 /**
5393 * @brief Clear the trigger interrupt flag (TIF).
5394 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5395 * @param TIMx Timer instance
5396 * @retval None
5397 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5398 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5399 {
5400 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5401 }
5402
5403 /**
5404 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5405 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5406 * @param TIMx Timer instance
5407 * @retval State of bit (1 or 0).
5408 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5409 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5410 {
5411 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5412 }
5413
5414 /**
5415 * @brief Clear the break interrupt flag (BIF).
5416 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5417 * @param TIMx Timer instance
5418 * @retval None
5419 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5420 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5421 {
5422 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5423 }
5424
5425 /**
5426 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5427 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5428 * @param TIMx Timer instance
5429 * @retval State of bit (1 or 0).
5430 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5431 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5432 {
5433 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5434 }
5435
5436 /**
5437 * @brief Clear the break 2 interrupt flag (B2IF).
5438 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5439 * @param TIMx Timer instance
5440 * @retval None
5441 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5442 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5443 {
5444 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5445 }
5446
5447 /**
5448 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5449 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5450 * @param TIMx Timer instance
5451 * @retval State of bit (1 or 0).
5452 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5453 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5454 {
5455 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5456 }
5457
5458 /**
5459 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5460 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5461 * @param TIMx Timer instance
5462 * @retval None
5463 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5464 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5465 {
5466 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5467 }
5468
5469 /**
5470 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5471 * (Capture/Compare 1 interrupt is pending).
5472 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5473 * @param TIMx Timer instance
5474 * @retval State of bit (1 or 0).
5475 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5476 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5477 {
5478 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5479 }
5480
5481 /**
5482 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5483 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5484 * @param TIMx Timer instance
5485 * @retval None
5486 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5487 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5488 {
5489 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5490 }
5491
5492 /**
5493 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5494 * (Capture/Compare 2 over-capture interrupt is pending).
5495 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5496 * @param TIMx Timer instance
5497 * @retval State of bit (1 or 0).
5498 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5499 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5500 {
5501 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5502 }
5503
5504 /**
5505 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5506 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5507 * @param TIMx Timer instance
5508 * @retval None
5509 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5510 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5511 {
5512 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5513 }
5514
5515 /**
5516 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5517 * (Capture/Compare 3 over-capture interrupt is pending).
5518 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5519 * @param TIMx Timer instance
5520 * @retval State of bit (1 or 0).
5521 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5522 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5523 {
5524 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5525 }
5526
5527 /**
5528 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5529 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5530 * @param TIMx Timer instance
5531 * @retval None
5532 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5533 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5534 {
5535 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5536 }
5537
5538 /**
5539 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5540 * (Capture/Compare 4 over-capture interrupt is pending).
5541 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5542 * @param TIMx Timer instance
5543 * @retval State of bit (1 or 0).
5544 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5545 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5546 {
5547 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5548 }
5549
5550 /**
5551 * @brief Clear the system break interrupt flag (SBIF).
5552 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5553 * @param TIMx Timer instance
5554 * @retval None
5555 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5556 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5557 {
5558 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5559 }
5560
5561 /**
5562 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5563 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5564 * @param TIMx Timer instance
5565 * @retval State of bit (1 or 0).
5566 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5567 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5568 {
5569 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5570 }
5571
5572 /**
5573 * @brief Clear the transition error interrupt flag (TERRF).
5574 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5575 * a timer instance provides encoder error management.
5576 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5577 * @param TIMx Timer instance
5578 * @retval None
5579 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5580 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5581 {
5582 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5583 }
5584
5585 /**
5586 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5587 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5588 * a timer instance provides encoder error management.
5589 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5590 * @param TIMx Timer instance
5591 * @retval State of bit (1 or 0).
5592 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5593 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5594 {
5595 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5596 }
5597
5598 /**
5599 * @brief Clear the index error interrupt flag (IERRF).
5600 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5601 * a timer instance provides encoder error management.
5602 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5603 * @param TIMx Timer instance
5604 * @retval None
5605 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5606 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5607 {
5608 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5609 }
5610
5611 /**
5612 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5613 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5614 * a timer instance provides encoder error management.
5615 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5616 * @param TIMx Timer instance
5617 * @retval State of bit (1 or 0).
5618 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5619 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5620 {
5621 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5622 }
5623
5624 /**
5625 * @brief Clear the direction change interrupt flag (DIRF).
5626 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5627 * a timer instance provides encoder interrupt management.
5628 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5629 * @param TIMx Timer instance
5630 * @retval None
5631 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5632 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5633 {
5634 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5635 }
5636
5637 /**
5638 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5639 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5640 * a timer instance provides encoder interrupt management.
5641 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5642 * @param TIMx Timer instance
5643 * @retval State of bit (1 or 0).
5644 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5645 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5646 {
5647 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5648 }
5649
5650 /**
5651 * @brief Clear the index interrupt flag (IDXF).
5652 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5653 * a timer instance provides encoder interrupt management.
5654 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5655 * @param TIMx Timer instance
5656 * @retval None
5657 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5658 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5659 {
5660 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5661 }
5662
5663 /**
5664 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5665 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5666 * a timer instance provides encoder interrupt management.
5667 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5668 * @param TIMx Timer instance
5669 * @retval State of bit (1 or 0).
5670 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5671 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5672 {
5673 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5674 }
5675 /**
5676 * @}
5677 */
5678
5679 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5680 * @{
5681 */
5682 /**
5683 * @brief Enable update interrupt (UIE).
5684 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5685 * @param TIMx Timer instance
5686 * @retval None
5687 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5688 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5689 {
5690 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5691 }
5692
5693 /**
5694 * @brief Disable update interrupt (UIE).
5695 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5696 * @param TIMx Timer instance
5697 * @retval None
5698 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5699 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5700 {
5701 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5702 }
5703
5704 /**
5705 * @brief Indicates whether the update interrupt (UIE) is enabled.
5706 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5707 * @param TIMx Timer instance
5708 * @retval State of bit (1 or 0).
5709 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5710 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5711 {
5712 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5713 }
5714
5715 /**
5716 * @brief Enable capture/compare 1 interrupt (CC1IE).
5717 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5718 * @param TIMx Timer instance
5719 * @retval None
5720 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5721 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5722 {
5723 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5724 }
5725
5726 /**
5727 * @brief Disable capture/compare 1 interrupt (CC1IE).
5728 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5729 * @param TIMx Timer instance
5730 * @retval None
5731 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5732 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5733 {
5734 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5735 }
5736
5737 /**
5738 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5739 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5740 * @param TIMx Timer instance
5741 * @retval State of bit (1 or 0).
5742 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5743 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5744 {
5745 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5746 }
5747
5748 /**
5749 * @brief Enable capture/compare 2 interrupt (CC2IE).
5750 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5751 * @param TIMx Timer instance
5752 * @retval None
5753 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5754 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5755 {
5756 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5757 }
5758
5759 /**
5760 * @brief Disable capture/compare 2 interrupt (CC2IE).
5761 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5762 * @param TIMx Timer instance
5763 * @retval None
5764 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5765 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5766 {
5767 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5768 }
5769
5770 /**
5771 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5772 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5773 * @param TIMx Timer instance
5774 * @retval State of bit (1 or 0).
5775 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5776 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5777 {
5778 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5779 }
5780
5781 /**
5782 * @brief Enable capture/compare 3 interrupt (CC3IE).
5783 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5784 * @param TIMx Timer instance
5785 * @retval None
5786 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5787 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5788 {
5789 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5790 }
5791
5792 /**
5793 * @brief Disable capture/compare 3 interrupt (CC3IE).
5794 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5795 * @param TIMx Timer instance
5796 * @retval None
5797 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5798 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5799 {
5800 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5801 }
5802
5803 /**
5804 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5805 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5806 * @param TIMx Timer instance
5807 * @retval State of bit (1 or 0).
5808 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5809 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5810 {
5811 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5812 }
5813
5814 /**
5815 * @brief Enable capture/compare 4 interrupt (CC4IE).
5816 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5817 * @param TIMx Timer instance
5818 * @retval None
5819 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5820 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5821 {
5822 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5823 }
5824
5825 /**
5826 * @brief Disable capture/compare 4 interrupt (CC4IE).
5827 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5828 * @param TIMx Timer instance
5829 * @retval None
5830 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5831 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5832 {
5833 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5834 }
5835
5836 /**
5837 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5838 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5839 * @param TIMx Timer instance
5840 * @retval State of bit (1 or 0).
5841 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5842 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5843 {
5844 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5845 }
5846
5847 /**
5848 * @brief Enable commutation interrupt (COMIE).
5849 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5850 * @param TIMx Timer instance
5851 * @retval None
5852 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5853 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5854 {
5855 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5856 }
5857
5858 /**
5859 * @brief Disable commutation interrupt (COMIE).
5860 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5861 * @param TIMx Timer instance
5862 * @retval None
5863 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5864 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5865 {
5866 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5867 }
5868
5869 /**
5870 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5871 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5872 * @param TIMx Timer instance
5873 * @retval State of bit (1 or 0).
5874 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5875 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5876 {
5877 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5878 }
5879
5880 /**
5881 * @brief Enable trigger interrupt (TIE).
5882 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5883 * @param TIMx Timer instance
5884 * @retval None
5885 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5886 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5887 {
5888 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5889 }
5890
5891 /**
5892 * @brief Disable trigger interrupt (TIE).
5893 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5894 * @param TIMx Timer instance
5895 * @retval None
5896 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5897 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5898 {
5899 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5900 }
5901
5902 /**
5903 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5904 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5905 * @param TIMx Timer instance
5906 * @retval State of bit (1 or 0).
5907 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5908 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5909 {
5910 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5911 }
5912
5913 /**
5914 * @brief Enable break interrupt (BIE).
5915 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5916 * @param TIMx Timer instance
5917 * @retval None
5918 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5919 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5920 {
5921 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5922 }
5923
5924 /**
5925 * @brief Disable break interrupt (BIE).
5926 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5927 * @param TIMx Timer instance
5928 * @retval None
5929 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5930 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5931 {
5932 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5933 }
5934
5935 /**
5936 * @brief Indicates whether the break interrupt (BIE) is enabled.
5937 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5938 * @param TIMx Timer instance
5939 * @retval State of bit (1 or 0).
5940 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5941 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5942 {
5943 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5944 }
5945
5946 /**
5947 * @brief Enable transition error interrupt (TERRIE).
5948 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5949 * a timer instance provides encoder error management.
5950 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5951 * @param TIMx Timer instance
5952 * @retval None
5953 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5954 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5955 {
5956 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5957 }
5958
5959 /**
5960 * @brief Disable transition error interrupt (TERRIE).
5961 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5962 * a timer instance provides encoder error management.
5963 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5964 * @param TIMx Timer instance
5965 * @retval None
5966 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5967 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5968 {
5969 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5970 }
5971
5972 /**
5973 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5974 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5975 * a timer instance provides encoder error management.
5976 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5977 * @param TIMx Timer instance
5978 * @retval State of bit (1 or 0).
5979 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5980 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5981 {
5982 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5983 }
5984
5985 /**
5986 * @brief Enable index error interrupt (IERRIE).
5987 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5988 * a timer instance provides encoder error management.
5989 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5990 * @param TIMx Timer instance
5991 * @retval None
5992 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5993 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5994 {
5995 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5996 }
5997
5998 /**
5999 * @brief Disable index error interrupt (IERRIE).
6000 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6001 * a timer instance provides encoder error management.
6002 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
6003 * @param TIMx Timer instance
6004 * @retval None
6005 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)6006 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
6007 {
6008 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6009 }
6010
6011 /**
6012 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
6013 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6014 * a timer instance provides encoder error management.
6015 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
6016 * @param TIMx Timer instance
6017 * @retval State of bit (1 or 0).
6018 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)6019 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
6020 {
6021 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
6022 }
6023
6024 /**
6025 * @brief Enable direction change interrupt (DIRIE).
6026 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6027 * a timer instance provides encoder interrupt management.
6028 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
6029 * @param TIMx Timer instance
6030 * @retval None
6031 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)6032 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
6033 {
6034 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6035 }
6036
6037 /**
6038 * @brief Disable direction change interrupt (DIRIE).
6039 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6040 * a timer instance provides encoder interrupt management.
6041 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
6042 * @param TIMx Timer instance
6043 * @retval None
6044 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)6045 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
6046 {
6047 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6048 }
6049
6050 /**
6051 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
6052 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6053 * a timer instance provides encoder interrupt management.
6054 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
6055 * @param TIMx Timer instance
6056 * @retval State of bit (1 or 0).
6057 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)6058 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
6059 {
6060 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
6061 }
6062
6063 /**
6064 * @brief Enable index interrupt (IDXIE).
6065 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6066 * a timer instance provides encoder interrupt management.
6067 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
6068 * @param TIMx Timer instance
6069 * @retval None
6070 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)6071 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
6072 {
6073 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6074 }
6075
6076 /**
6077 * @brief Disable index interrupt (IDXIE).
6078 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6079 * a timer instance provides encoder interrupt management.
6080 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
6081 * @param TIMx Timer instance
6082 * @retval None
6083 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)6084 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
6085 {
6086 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6087 }
6088
6089 /**
6090 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
6091 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6092 * a timer instance provides encoder interrupt management.
6093 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
6094 * @param TIMx Timer instance
6095 * @retval State of bit (1 or 0).
6096 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)6097 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
6098 {
6099 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
6100 }
6101
6102 /**
6103 * @}
6104 */
6105
6106 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
6107 * @{
6108 */
6109 /**
6110 * @brief Enable update DMA request (UDE).
6111 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
6112 * @param TIMx Timer instance
6113 * @retval None
6114 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)6115 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6116 {
6117 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
6118 }
6119
6120 /**
6121 * @brief Disable update DMA request (UDE).
6122 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
6123 * @param TIMx Timer instance
6124 * @retval None
6125 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)6126 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6127 {
6128 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
6129 }
6130
6131 /**
6132 * @brief Indicates whether the update DMA request (UDE) is enabled.
6133 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
6134 * @param TIMx Timer instance
6135 * @retval State of bit (1 or 0).
6136 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)6137 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
6138 {
6139 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
6140 }
6141
6142 /**
6143 * @brief Enable capture/compare 1 DMA request (CC1DE).
6144 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
6145 * @param TIMx Timer instance
6146 * @retval None
6147 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)6148 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
6149 {
6150 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6151 }
6152
6153 /**
6154 * @brief Disable capture/compare 1 DMA request (CC1DE).
6155 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
6156 * @param TIMx Timer instance
6157 * @retval None
6158 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)6159 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
6160 {
6161 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6162 }
6163
6164 /**
6165 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
6166 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
6167 * @param TIMx Timer instance
6168 * @retval State of bit (1 or 0).
6169 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)6170 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
6171 {
6172 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
6173 }
6174
6175 /**
6176 * @brief Enable capture/compare 2 DMA request (CC2DE).
6177 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
6178 * @param TIMx Timer instance
6179 * @retval None
6180 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)6181 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
6182 {
6183 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6184 }
6185
6186 /**
6187 * @brief Disable capture/compare 2 DMA request (CC2DE).
6188 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
6189 * @param TIMx Timer instance
6190 * @retval None
6191 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)6192 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
6193 {
6194 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6195 }
6196
6197 /**
6198 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
6199 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
6200 * @param TIMx Timer instance
6201 * @retval State of bit (1 or 0).
6202 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)6203 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
6204 {
6205 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
6206 }
6207
6208 /**
6209 * @brief Enable capture/compare 3 DMA request (CC3DE).
6210 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
6211 * @param TIMx Timer instance
6212 * @retval None
6213 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)6214 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
6215 {
6216 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6217 }
6218
6219 /**
6220 * @brief Disable capture/compare 3 DMA request (CC3DE).
6221 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6222 * @param TIMx Timer instance
6223 * @retval None
6224 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6225 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6226 {
6227 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6228 }
6229
6230 /**
6231 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6232 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6233 * @param TIMx Timer instance
6234 * @retval State of bit (1 or 0).
6235 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)6236 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
6237 {
6238 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6239 }
6240
6241 /**
6242 * @brief Enable capture/compare 4 DMA request (CC4DE).
6243 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6244 * @param TIMx Timer instance
6245 * @retval None
6246 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6247 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6248 {
6249 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6250 }
6251
6252 /**
6253 * @brief Disable capture/compare 4 DMA request (CC4DE).
6254 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6255 * @param TIMx Timer instance
6256 * @retval None
6257 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6258 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6259 {
6260 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6261 }
6262
6263 /**
6264 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6265 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6266 * @param TIMx Timer instance
6267 * @retval State of bit (1 or 0).
6268 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)6269 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
6270 {
6271 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6272 }
6273
6274 /**
6275 * @brief Enable commutation DMA request (COMDE).
6276 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6277 * @param TIMx Timer instance
6278 * @retval None
6279 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6280 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6281 {
6282 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6283 }
6284
6285 /**
6286 * @brief Disable commutation DMA request (COMDE).
6287 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6288 * @param TIMx Timer instance
6289 * @retval None
6290 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6291 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6292 {
6293 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6294 }
6295
6296 /**
6297 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6298 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6299 * @param TIMx Timer instance
6300 * @retval State of bit (1 or 0).
6301 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)6302 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
6303 {
6304 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6305 }
6306
6307 /**
6308 * @brief Enable trigger interrupt (TDE).
6309 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6310 * @param TIMx Timer instance
6311 * @retval None
6312 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6313 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6314 {
6315 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6316 }
6317
6318 /**
6319 * @brief Disable trigger interrupt (TDE).
6320 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6321 * @param TIMx Timer instance
6322 * @retval None
6323 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6324 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6325 {
6326 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6327 }
6328
6329 /**
6330 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6331 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6332 * @param TIMx Timer instance
6333 * @retval State of bit (1 or 0).
6334 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)6335 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
6336 {
6337 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6338 }
6339
6340 /**
6341 * @}
6342 */
6343
6344 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6345 * @{
6346 */
6347 /**
6348 * @brief Generate an update event.
6349 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6350 * @param TIMx Timer instance
6351 * @retval None
6352 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6353 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6354 {
6355 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6356 }
6357
6358 /**
6359 * @brief Generate Capture/Compare 1 event.
6360 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6361 * @param TIMx Timer instance
6362 * @retval None
6363 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6364 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6365 {
6366 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6367 }
6368
6369 /**
6370 * @brief Generate Capture/Compare 2 event.
6371 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6372 * @param TIMx Timer instance
6373 * @retval None
6374 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6375 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6376 {
6377 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6378 }
6379
6380 /**
6381 * @brief Generate Capture/Compare 3 event.
6382 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6383 * @param TIMx Timer instance
6384 * @retval None
6385 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6386 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6387 {
6388 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6389 }
6390
6391 /**
6392 * @brief Generate Capture/Compare 4 event.
6393 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6394 * @param TIMx Timer instance
6395 * @retval None
6396 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6397 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6398 {
6399 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6400 }
6401
6402 /**
6403 * @brief Generate commutation event.
6404 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6405 * @param TIMx Timer instance
6406 * @retval None
6407 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6408 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6409 {
6410 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6411 }
6412
6413 /**
6414 * @brief Generate trigger event.
6415 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6416 * @param TIMx Timer instance
6417 * @retval None
6418 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6419 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6420 {
6421 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6422 }
6423
6424 /**
6425 * @brief Generate break event.
6426 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6427 * @param TIMx Timer instance
6428 * @retval None
6429 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6430 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6431 {
6432 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6433 }
6434
6435 /**
6436 * @brief Generate break 2 event.
6437 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6438 * @param TIMx Timer instance
6439 * @retval None
6440 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6441 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6442 {
6443 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6444 }
6445
6446 /**
6447 * @}
6448 */
6449
6450 #if defined(USE_FULL_LL_DRIVER)
6451 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6452 * @{
6453 */
6454
6455 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6456 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6457 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6458 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6459 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6460 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6461 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6462 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6463 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6464 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6465 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6466 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6467 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6468 /**
6469 * @}
6470 */
6471 #endif /* USE_FULL_LL_DRIVER */
6472
6473 /**
6474 * @}
6475 */
6476
6477 /**
6478 * @}
6479 */
6480
6481 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
6482
6483 /**
6484 * @}
6485 */
6486
6487 #ifdef __cplusplus
6488 }
6489 #endif
6490
6491 #endif /* __STM32U5xx_LL_TIM_H */
6492
