1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32G4xx_LL_TIM_H
21 #define __STM32G4xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
35
36 /** @defgroup TIM_LL TIM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
43 * @{
44 */
45 static const uint8_t OFFSET_TAB_CCMRx[] =
46 {
47 0x00U, /* 0: TIMx_CH1 */
48 0x00U, /* 1: TIMx_CH1N */
49 0x00U, /* 2: TIMx_CH2 */
50 0x00U, /* 3: TIMx_CH2N */
51 0x04U, /* 4: TIMx_CH3 */
52 0x04U, /* 5: TIMx_CH3N */
53 0x04U, /* 6: TIMx_CH4 */
54 0x04U, /* 7: TIMx_CH4N */
55 0x38U, /* 8: TIMx_CH5 */
56 0x38U /* 9: TIMx_CH6 */
57
58 };
59
60 static const uint8_t SHIFT_TAB_OCxx[] =
61 {
62 0U, /* 0: OC1M, OC1FE, OC1PE */
63 0U, /* 1: - NA */
64 8U, /* 2: OC2M, OC2FE, OC2PE */
65 0U, /* 3: - NA */
66 0U, /* 4: OC3M, OC3FE, OC3PE */
67 0U, /* 5: - NA */
68 8U, /* 6: OC4M, OC4FE, OC4PE */
69 0U, /* 7: - NA */
70 0U, /* 8: OC5M, OC5FE, OC5PE */
71 8U /* 9: OC6M, OC6FE, OC6PE */
72 };
73
74 static const uint8_t SHIFT_TAB_ICxx[] =
75 {
76 0U, /* 0: CC1S, IC1PSC, IC1F */
77 0U, /* 1: - NA */
78 8U, /* 2: CC2S, IC2PSC, IC2F */
79 0U, /* 3: - NA */
80 0U, /* 4: CC3S, IC3PSC, IC3F */
81 0U, /* 5: - NA */
82 8U, /* 6: CC4S, IC4PSC, IC4F */
83 0U, /* 7: - NA */
84 0U, /* 8: - NA */
85 0U /* 9: - NA */
86 };
87
88 static const uint8_t SHIFT_TAB_CCxP[] =
89 {
90 0U, /* 0: CC1P */
91 2U, /* 1: CC1NP */
92 4U, /* 2: CC2P */
93 6U, /* 3: CC2NP */
94 8U, /* 4: CC3P */
95 10U, /* 5: CC3NP */
96 12U, /* 6: CC4P */
97 14U, /* 7: CC4NP */
98 16U, /* 8: CC5P */
99 20U /* 9: CC6P */
100 };
101
102 static const uint8_t SHIFT_TAB_OISx[] =
103 {
104 0U, /* 0: OIS1 */
105 1U, /* 1: OIS1N */
106 2U, /* 2: OIS2 */
107 3U, /* 3: OIS2N */
108 4U, /* 4: OIS3 */
109 5U, /* 5: OIS3N */
110 6U, /* 6: OIS4 */
111 7U, /* 7: OIS4N */
112 8U, /* 8: OIS5 */
113 10U /* 9: OIS6 */
114 };
115 /**
116 * @}
117 */
118
119 /* Private constants ---------------------------------------------------------*/
120 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
121 * @{
122 */
123
124 /* Defines used for the bit position in the register and perform offsets */
125 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
126
127 /* Generic bit definitions for TIMx_AF1 register */
128 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
129 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
130
131
132 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
133 #define DT_DELAY_1 ((uint8_t)0x7F)
134 #define DT_DELAY_2 ((uint8_t)0x3F)
135 #define DT_DELAY_3 ((uint8_t)0x1F)
136 #define DT_DELAY_4 ((uint8_t)0x1F)
137
138 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
139 #define DT_RANGE_1 ((uint8_t)0x00)
140 #define DT_RANGE_2 ((uint8_t)0x80)
141 #define DT_RANGE_3 ((uint8_t)0xC0)
142 #define DT_RANGE_4 ((uint8_t)0xE0)
143
144 /** Legacy definitions for compatibility purpose
145 @cond 0
146 */
147 /**
148 @endcond
149 */
150
151 #define OCREF_CLEAR_SELECT_Pos (28U)
152 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */
153 /**
154 * @}
155 */
156
157 /* Private macros ------------------------------------------------------------*/
158 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
159 * @{
160 */
161 /** @brief Convert channel id into channel index.
162 * @param __CHANNEL__ This parameter can be one of the following values:
163 * @arg @ref LL_TIM_CHANNEL_CH1
164 * @arg @ref LL_TIM_CHANNEL_CH1N
165 * @arg @ref LL_TIM_CHANNEL_CH2
166 * @arg @ref LL_TIM_CHANNEL_CH2N
167 * @arg @ref LL_TIM_CHANNEL_CH3
168 * @arg @ref LL_TIM_CHANNEL_CH3N
169 * @arg @ref LL_TIM_CHANNEL_CH4
170 * @arg @ref LL_TIM_CHANNEL_CH4N
171 * @arg @ref LL_TIM_CHANNEL_CH5
172 * @arg @ref LL_TIM_CHANNEL_CH6
173 * @retval none
174 */
175 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
176 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
177 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
178 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
179 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
180 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
181 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
182 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
183 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
184 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
185
186 /** @brief Calculate the deadtime sampling period(in ps).
187 * @param __TIMCLK__ timer input clock frequency (in Hz).
188 * @param __CKD__ This parameter can be one of the following values:
189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
190 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
191 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
192 * @retval none
193 */
194 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
195 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
196 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
197 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
198 /**
199 * @}
200 */
201
202
203 /* Exported types ------------------------------------------------------------*/
204 #if defined(USE_FULL_LL_DRIVER)
205 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
206 * @{
207 */
208
209 /**
210 * @brief TIM Time Base configuration structure definition.
211 */
212 typedef struct
213 {
214 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
215 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
216
217 This feature can be modified afterwards using unitary function
218 @ref LL_TIM_SetPrescaler().*/
219
220 uint32_t CounterMode; /*!< Specifies the counter mode.
221 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
222
223 This feature can be modified afterwards using unitary function
224 @ref LL_TIM_SetCounterMode().*/
225
226 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
227 Auto-Reload Register at the next update event.
228 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
229 Some timer instances may support 32 bits counters. In that case this parameter must
230 be a number between 0x0000 and 0xFFFFFFFF.
231
232 This feature can be modified afterwards using unitary function
233 @ref LL_TIM_SetAutoReload().*/
234
235 uint32_t ClockDivision; /*!< Specifies the clock division.
236 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetClockDivision().*/
240
241 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
242 reaches zero, an update event is generated and counting restarts
243 from the RCR value (N).
244 This means in PWM mode that (N+1) corresponds to:
245 - the number of PWM periods in edge-aligned mode
246 - the number of half PWM period in center-aligned mode
247 GP timers: this parameter must be a number between Min_Data = 0x00 and
248 Max_Data = 0xFF.
249 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
250 Max_Data = 0xFFFF.
251
252 This feature can be modified afterwards using unitary function
253 @ref LL_TIM_SetRepetitionCounter().*/
254 } LL_TIM_InitTypeDef;
255
256 /**
257 * @brief TIM Output Compare configuration structure definition.
258 */
259 typedef struct
260 {
261 uint32_t OCMode; /*!< Specifies the output mode.
262 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
263
264 This feature can be modified afterwards using unitary function
265 @ref LL_TIM_OC_SetMode().*/
266
267 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
268 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
269
270 This feature can be modified afterwards using unitary functions
271 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
272
273 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
274 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
275
276 This feature can be modified afterwards using unitary functions
277 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
278
279 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
280 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
281
282 This feature can be modified afterwards using unitary function
283 LL_TIM_OC_SetCompareCHx (x=1..6).*/
284
285 uint32_t OCPolarity; /*!< Specifies the output polarity.
286 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
287
288 This feature can be modified afterwards using unitary function
289 @ref LL_TIM_OC_SetPolarity().*/
290
291 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
292 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
293
294 This feature can be modified afterwards using unitary function
295 @ref LL_TIM_OC_SetPolarity().*/
296
297
298 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
299 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
300
301 This feature can be modified afterwards using unitary function
302 @ref LL_TIM_OC_SetIdleState().*/
303
304 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function
308 @ref LL_TIM_OC_SetIdleState().*/
309 } LL_TIM_OC_InitTypeDef;
310
311 /**
312 * @brief TIM Input Capture configuration structure definition.
313 */
314
315 typedef struct
316 {
317
318 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
319 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
320
321 This feature can be modified afterwards using unitary function
322 @ref LL_TIM_IC_SetPolarity().*/
323
324 uint32_t ICActiveInput; /*!< Specifies the input.
325 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
326
327 This feature can be modified afterwards using unitary function
328 @ref LL_TIM_IC_SetActiveInput().*/
329
330 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
331 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
332
333 This feature can be modified afterwards using unitary function
334 @ref LL_TIM_IC_SetPrescaler().*/
335
336 uint32_t ICFilter; /*!< Specifies the input capture filter.
337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
338
339 This feature can be modified afterwards using unitary function
340 @ref LL_TIM_IC_SetFilter().*/
341 } LL_TIM_IC_InitTypeDef;
342
343
344 /**
345 * @brief TIM Encoder interface configuration structure definition.
346 */
347 typedef struct
348 {
349 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
350 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
351
352 This feature can be modified afterwards using unitary function
353 @ref LL_TIM_SetEncoderMode().*/
354
355 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
356 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
357
358 This feature can be modified afterwards using unitary function
359 @ref LL_TIM_IC_SetPolarity().*/
360
361 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
362 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
363
364 This feature can be modified afterwards using unitary function
365 @ref LL_TIM_IC_SetActiveInput().*/
366
367 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
368 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
369
370 This feature can be modified afterwards using unitary function
371 @ref LL_TIM_IC_SetPrescaler().*/
372
373 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
374 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
375
376 This feature can be modified afterwards using unitary function
377 @ref LL_TIM_IC_SetFilter().*/
378
379 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
380 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
381
382 This feature can be modified afterwards using unitary function
383 @ref LL_TIM_IC_SetPolarity().*/
384
385 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
386 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
387
388 This feature can be modified afterwards using unitary function
389 @ref LL_TIM_IC_SetActiveInput().*/
390
391 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
392 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
393
394 This feature can be modified afterwards using unitary function
395 @ref LL_TIM_IC_SetPrescaler().*/
396
397 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
398 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
399
400 This feature can be modified afterwards using unitary function
401 @ref LL_TIM_IC_SetFilter().*/
402
403 } LL_TIM_ENCODER_InitTypeDef;
404
405 /**
406 * @brief TIM Hall sensor interface configuration structure definition.
407 */
408 typedef struct
409 {
410
411 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
412 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
413
414 This feature can be modified afterwards using unitary function
415 @ref LL_TIM_IC_SetPolarity().*/
416
417 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
418 Prescaler must be set to get a maximum counter period longer than the
419 time interval between 2 consecutive changes on the Hall inputs.
420 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
421
422 This feature can be modified afterwards using unitary function
423 @ref LL_TIM_IC_SetPrescaler().*/
424
425 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
426 This parameter can be a value of
427 @ref TIM_LL_EC_IC_FILTER.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_IC_SetFilter().*/
431
432 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
433 A positive pulse (TRGO event) is generated with a programmable delay every time
434 a change occurs on the Hall inputs.
435 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
436
437 This feature can be modified afterwards using unitary function
438 @ref LL_TIM_OC_SetCompareCH2().*/
439 } LL_TIM_HALLSENSOR_InitTypeDef;
440
441 /**
442 * @brief BDTR (Break and Dead Time) structure definition
443 */
444 typedef struct
445 {
446 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
447 This parameter can be a value of @ref TIM_LL_EC_OSSR
448
449 This feature can be modified afterwards using unitary function
450 @ref LL_TIM_SetOffStates()
451
452 @note This bit-field cannot be modified as long as LOCK level 2 has been
453 programmed. */
454
455 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
456 This parameter can be a value of @ref TIM_LL_EC_OSSI
457
458 This feature can be modified afterwards using unitary function
459 @ref LL_TIM_SetOffStates()
460
461 @note This bit-field cannot be modified as long as LOCK level 2 has been
462 programmed. */
463
464 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
465 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
466
467 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
468 register has been written, their content is frozen until the next reset.*/
469
470 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
471 switching-on of the outputs.
472 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
473
474 This feature can be modified afterwards using unitary function
475 @ref LL_TIM_OC_SetDeadTime()
476
477 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
478 programmed. */
479
480 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
481 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
482
483 This feature can be modified afterwards using unitary functions
484 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been
487 programmed. */
488
489 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
490 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
491
492 This feature can be modified afterwards using unitary function
493 @ref LL_TIM_ConfigBRK()
494
495 @note This bit-field can not be modified as long as LOCK level 1 has been
496 programmed. */
497
498 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
499 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
500
501 This feature can be modified afterwards using unitary function
502 @ref LL_TIM_ConfigBRK()
503
504 @note This bit-field can not be modified as long as LOCK level 1 has been
505 programmed. */
506
507 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
508 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
509
510 This feature can be modified afterwards using unitary functions
511 @ref LL_TIM_ConfigBRK()
512
513 @note Bidirectional break input is only supported by advanced timers instances.
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
523
524 @note This bit-field can not be modified as long as LOCK level 1 has been
525 programmed. */
526
527 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
528 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
529
530 This feature can be modified afterwards using unitary function
531 @ref LL_TIM_ConfigBRK2()
532
533 @note This bit-field can not be modified as long as LOCK level 1 has been
534 programmed. */
535
536 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
537 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
538
539 This feature can be modified afterwards using unitary function
540 @ref LL_TIM_ConfigBRK2()
541
542 @note This bit-field can not be modified as long as LOCK level 1 has been
543 programmed. */
544
545 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
546 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
547
548 This feature can be modified afterwards using unitary functions
549 @ref LL_TIM_ConfigBRK2()
550
551 @note Bidirectional break input is only supported by advanced timers instances.
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
557 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
561
562 @note This bit-field can not be modified as long as LOCK level 1 has been
563 programmed. */
564 } LL_TIM_BDTR_InitTypeDef;
565
566 /**
567 * @}
568 */
569 #endif /* USE_FULL_LL_DRIVER */
570
571 /* Exported constants --------------------------------------------------------*/
572 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
573 * @{
574 */
575
576 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
577 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
578 * @{
579 */
580 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
581 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
582 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
583 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
584 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
585 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
586 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
587 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
588 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
589 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
590 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
591 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
592 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
593 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
594 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
595 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
596 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
597 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
598 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
599 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
600 /**
601 * @}
602 */
603
604 #if defined(USE_FULL_LL_DRIVER)
605 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
606 * @{
607 */
608 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
609 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
610 /**
611 * @}
612 */
613
614 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
615 * @{
616 */
617 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
618 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
619 /**
620 * @}
621 */
622
623 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
624 * @{
625 */
626 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
627 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
628 /**
629 * @}
630 */
631 #endif /* USE_FULL_LL_DRIVER */
632
633 /** @defgroup TIM_LL_EC_IT IT Defines
634 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
635 * @{
636 */
637 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
638 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
639 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
640 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
641 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
642 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
643 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
644 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
645 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
646 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
647 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
648 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
649 /**
650 * @}
651 */
652
653 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
654 * @{
655 */
656 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
657 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
658 /**
659 * @}
660 */
661
662 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
663 * @{
664 */
665 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
666 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
667 /**
668 * @}
669 */
670
671 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
672 * @{
673 */
674 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
675 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
676 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
677 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
678 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
684 * @{
685 */
686 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
687 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
688 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
694 * @{
695 */
696 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
697 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
698 /**
699 * @}
700 */
701
702 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
703 * @{
704 */
705 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
706 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
707 /**
708 * @}
709 */
710
711 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
712 * @{
713 */
714 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
715 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
716 /**
717 * @}
718 */
719
720 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
721 * @{
722 */
723 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
724 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
725 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
726 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_CHANNEL Channel
732 * @{
733 */
734 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
735 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
736 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
737 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
738 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
739 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
740 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
741 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
742 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
743 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
744 /**
745 * @}
746 */
747
748 #if defined(USE_FULL_LL_DRIVER)
749 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
750 * @{
751 */
752 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
753 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
754 /**
755 * @}
756 */
757 #endif /* USE_FULL_LL_DRIVER */
758
759 /** Legacy definitions for compatibility purpose
760 @cond 0
761 */
762 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
763 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
764 /**
765 @endcond
766 */
767
768 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
769 * @{
770 */
771 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
772 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
773 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
774 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
775 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
776 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
777 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
778 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
779 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
780 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
781 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
782 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
783 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
784 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
785 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
786 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
787 /**
788 * @}
789 */
790
791 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
792 * @{
793 */
794 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
795 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
796 /**
797 * @}
798 */
799
800 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
801 * @{
802 */
803 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
804 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
805 /**
806 * @}
807 */
808
809 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
810 * @{
811 */
812 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
813 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
814 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
815 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
816 /**
817 * @}
818 */
819
820 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
821 * @{
822 */
823 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
824 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
825 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
826 /**
827 * @}
828 */
829
830 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
831 * @{
832 */
833 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
834 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
835 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
836 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
837 /**
838 * @}
839 */
840
841 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
842 * @{
843 */
844 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
845 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
846 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
847 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
848 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
849 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
850 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
851 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
852 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
853 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
854 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
855 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
856 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
857 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
858 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
859 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
860 /**
861 * @}
862 */
863
864 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
865 * @{
866 */
867 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
868 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
869 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
870 /**
871 * @}
872 */
873
874 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
875 * @{
876 */
877 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
878 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
879 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
880 /**
881 * @}
882 */
883
884 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
885 * @{
886 */
887 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
888 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
889 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
890 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
891 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
892 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
893 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
894 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
895 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
896 /**
897 * @}
898 */
899
900 /** @defgroup TIM_LL_EC_TRGO Trigger Output
901 * @{
902 */
903 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
904 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
905 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
906 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
907 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
908 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
909 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
910 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
911 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
912 /**
913 * @}
914 */
915
916 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
917 * @{
918 */
919 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
920 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
921 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
922 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
923 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
924 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
926 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
927 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
928 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
929 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
930 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
931 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
932 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
933 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
934 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
935 /**
936 * @}
937 */
938
939 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
940 * @{
941 */
942 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
943 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
944 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
945 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
946 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
947 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
948 the counter are controlled. */
949 /**
950 * @}
951 */
952
953 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
954 * @{
955 */
956 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
957 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
958 /**
959 * @}
960 */
961
962 /** @defgroup TIM_LL_EC_TS Trigger Selection
963 * @{
964 */
965 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
966 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
967 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
968 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
969 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
970 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
971 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
972 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
973 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
974 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
975 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
976 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
977 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
978 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
979 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
980 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
981 /**
982 * @}
983 */
984
985 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
986 * @{
987 */
988 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
989 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
990 /**
991 * @}
992 */
993
994 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
995 * @{
996 */
997 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
998 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
999 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1000 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1001 /**
1002 * @}
1003 */
1004
1005 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1006 * @{
1007 */
1008 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1009 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1010 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1011 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1012 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1013 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1014 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1015 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1016 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1017 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1018 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1019 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1020 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1021 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1022 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1023 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1029 * @{
1030 */
1031 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1032 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1033 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1034 #define LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1035 #define LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1036 #if defined(COMP5)
1037 #define LL_TIM_TIM1_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1038 #endif /* COMP5 */
1039 #if defined(COMP6)
1040 #define LL_TIM_TIM1_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1041 #endif /* COMP6 */
1042 #if defined(COMP7)
1043 #define LL_TIM_TIM1_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1044 #endif /* COMP7 */
1045 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
1046 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
1047 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
1048 #if defined(ADC4)
1049 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1050 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1051 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1052 #endif /* ADC4 */
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1058 * @{
1059 */
1060 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1061 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1062 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1063 #define LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1064 #define LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1065 #if defined(COMP5)
1066 #define LL_TIM_TIM2_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1067 #endif /* COMP5 */
1068 #if defined(COMP6)
1069 #define LL_TIM_TIM2_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1070 #endif /* COMP6 */
1071 #if defined(COMP7)
1072 #define LL_TIM_TIM2_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1073 #endif /* COMP7 */
1074 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1075 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1076 #if defined(TIM5)
1077 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
1078 #endif /* TIM5 */
1079 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1080 /**
1081 * @}
1082 */
1083
1084 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1085 * @{
1086 */
1087 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1088 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1089 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1090 #define LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1091 #define LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1092 #if defined(COMP5)
1093 #define LL_TIM_TIM3_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1094 #endif /* COMP5 */
1095 #if defined(COMP6)
1096 #define LL_TIM_TIM3_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1097 #endif /* COMP6 */
1098 #if defined(COMP7)
1099 #define LL_TIM_TIM3_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1100 #endif /* COMP7 */
1101 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1102 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1103 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
1104 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
1105 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
1106 /**
1107 * @}
1108 */
1109
1110 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1111 * @{
1112 */
1113 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1114 #define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1115 #define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1116 #define LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1117 #define LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1118 #if defined(COMP5)
1119 #define LL_TIM_TIM4_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1120 #endif /* COMP5 */
1121 #if defined(COMP6)
1122 #define LL_TIM_TIM4_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1123 #endif /* COMP6 */
1124 #if defined(COMP7)
1125 #define LL_TIM_TIM4_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1126 #endif /* COMP7 */
1127 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1128 #if defined(TIM5)
1129 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1130 #endif /* TIM5 */
1131 /**
1132 * @}
1133 */
1134
1135 #if defined(TIM5)
1136 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1137 * @{
1138 */
1139 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1140 #define LL_TIM_TIM5_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1141 #define LL_TIM_TIM5_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1142 #define LL_TIM_TIM5_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1143 #define LL_TIM_TIM5_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1144 #if defined(COMP5)
1145 #define LL_TIM_TIM5_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1146 #endif /* COMP5 */
1147 #if defined(COMP6)
1148 #define LL_TIM_TIM5_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1149 #endif /* COMP6 */
1150 #if defined(COMP7)
1151 #define LL_TIM_TIM5_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1152 #endif /* COMP7 */
1153 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1154 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1155 /**
1156 * @}
1157 */
1158 #endif /* TIM5 */
1159
1160 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1161 * @{
1162 */
1163 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1164 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1165 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1166 #define LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1167 #define LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1168 #if defined(COMP5)
1169 #define LL_TIM_TIM8_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1170 #endif /* COMP5 */
1171 #if defined(COMP6)
1172 #define LL_TIM_TIM8_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1173 #endif /* COMP6 */
1174 #if defined(COMP7)
1175 #define LL_TIM_TIM8_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1176 #endif /* COMP7 */
1177 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */
1178 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
1179 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
1180 #if defined(ADC3)
1181 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
1182 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
1183 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
1184 #endif /* ADC3 */
1185 /**
1186 * @}
1187 */
1188
1189 #if defined(TIM20)
1190 /** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
1191 * @{
1192 */
1193 #define LL_TIM_TIM20_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1194 #define LL_TIM_TIM20_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1195 #define LL_TIM_TIM20_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1196 #define LL_TIM_TIM20_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1197 #define LL_TIM_TIM20_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1198 #if defined(COMP5)
1199 #define LL_TIM_TIM20_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1200 #endif /* COMP5 */
1201 #if defined(COMP6)
1202 #define LL_TIM_TIM20_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1203 #endif /* COMP6 */
1204 #if defined(COMP7)
1205 #define LL_TIM_TIM20_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1206 #endif /* COMP7 */
1207 #if defined(ADC3)
1208 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */
1209 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
1210 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
1211 #endif /* ADC3 */
1212 #if defined(ADC5)
1213 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
1214 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
1215 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
1216 #endif /* ADC5 */
1217 /**
1218 * @}
1219 */
1220 #endif /* TIM20 */
1221
1222 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1223 * @{
1224 */
1225 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1226 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1232 * @{
1233 */
1234 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1235 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1236 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1237 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1238 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1239 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1240 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1241 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1242 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1243 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1244 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1245 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1246 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1247 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1248 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1249 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1250 /**
1251 * @}
1252 */
1253
1254 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1255 * @{
1256 */
1257 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1258 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1259 /**
1260 * @}
1261 */
1262
1263 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1264 * @{
1265 */
1266 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1267 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1268 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1269 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1270 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1271 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1272 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1273 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1274 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1275 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1276 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1277 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1278 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1279 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1280 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1281 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1282 /**
1283 * @}
1284 */
1285
1286 /** @defgroup TIM_LL_EC_OSSI OSSI
1287 * @{
1288 */
1289 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1290 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_LL_EC_OSSR OSSR
1296 * @{
1297 */
1298 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1299 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1305 * @{
1306 */
1307 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1308 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1309 /**
1310 * @}
1311 */
1312
1313 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1314 * @{
1315 */
1316 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1317 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1318 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1319 #define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
1320 #define LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E /*!< internal signal: COMP4 output */
1321 #if defined(COMP5)
1322 #define LL_TIM_BKIN_SOURCE_BKCOMP5 TIM1_AF1_BKCMP5E /*!< internal signal: COMP5 output */
1323 #endif /* COMP5 */
1324 #if defined(COMP6)
1325 #define LL_TIM_BKIN_SOURCE_BKCOMP6 TIM1_AF1_BKCMP6E /*!< internal signal: COMP6 output */
1326 #endif /* COMP6 */
1327 #if defined(COMP7)
1328 #define LL_TIM_BKIN_SOURCE_BKCOMP7 TIM1_AF1_BKCMP7E /*!< internal signal: COMP7 output */
1329 #endif /* COMP7 */
1330 /**
1331 * @}
1332 */
1333
1334 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1335 * @{
1336 */
1337 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1338 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1339 /**
1340 * @}
1341 */
1342
1343 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1344 * @{
1345 */
1346 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1347 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1348 /**
1349 * @}
1350 */
1351
1352 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1353 * @{
1354 */
1355 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1356 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1357 /**
1358 * @}
1359 */
1360
1361 /** Legacy definitions for compatibility purpose
1362 @cond 0
1363 */
1364 #define LL_TIM_ReArmBRK(_PARAM_)
1365 #define LL_TIM_ReArmBRK2(_PARAM_)
1366 /**
1367 @endcond
1368 */
1369
1370 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1371 * @{
1372 */
1373 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1374 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1375 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1376 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1377 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1378 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1379 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1380 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1381 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1382 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1383 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1384 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1385 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1386 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1387 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1388 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1389 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1390 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1391 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1392 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1393 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1394 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1395 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1396 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1397 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1398 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1399 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst */
1400 /**
1401 * @}
1402 */
1403
1404 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1405 * @{
1406 */
1407 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1408 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1409 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1410 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1411 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1412 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1413 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1414 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1415 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1416 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1417 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1418 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1419 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1420 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1421 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1422 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1423 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1424 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1425 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1426 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1427 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1428 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1429 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1430 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1431 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1432 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1433 /**
1434 * @}
1435 */
1436
1437 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1438 * @{
1439 */
1440 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1441 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
1442 #define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
1443 #define LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
1444 #define LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
1445 /**
1446 * @}
1447 */
1448
1449 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1450 * @{
1451 */
1452 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1453 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
1454 #define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
1455 #define LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
1456 #define LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
1457 #if defined(COMP5)
1458 #define LL_TIM_TIM2_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
1459 #endif /* COMP5 */
1460 /**
1461 * @}
1462 */
1463
1464 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1465 * @{
1466 */
1467 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1468 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
1469 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
1470 #define LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
1471 #define LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
1472 #if defined(COMP6)
1473 #define LL_TIM_TIM2_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
1474 #endif /* COMP6 */
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
1480 * @{
1481 */
1482 #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
1483 #define LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
1484 /**
1485 * @}
1486 */
1487
1488 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1489 * @{
1490 */
1491 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
1492 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
1493 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
1494 /**
1495 * @}
1496 */
1497
1498 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1499 * @{
1500 */
1501 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1502 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
1503 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
1504 #define LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
1505 #define LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
1506 #if defined(COMP5)
1507 #define LL_TIM_TIM3_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
1508 #endif /* COMP5 */
1509 #if defined(COMP6)
1510 #define LL_TIM_TIM3_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
1511 #endif /* COMP6 */
1512 #if defined(COMP7)
1513 #define LL_TIM_TIM3_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
1514 #endif /* COMP7 */
1515 /**
1516 * @}
1517 */
1518
1519 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1520 * @{
1521 */
1522 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1523 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
1524 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
1525 #define LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
1526 #define LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
1527 #if defined(COMP5)
1528 #define LL_TIM_TIM3_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
1529 #endif /* COMP5 */
1530 #if defined(COMP6)
1531 #define LL_TIM_TIM3_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
1532 #endif /* COMP6 */
1533 #if defined(COMP7)
1534 #define LL_TIM_TIM3_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
1535 #endif /* COMP7 */
1536 /**
1537 * @}
1538 */
1539
1540 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
1541 * @{
1542 */
1543 #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
1544 #define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
1545 /**
1546 * @}
1547 */
1548
1549 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
1550 * @{
1551 */
1552 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
1553 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
1554 #define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
1555 #define LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
1556 #define LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
1557 #if defined(COMP5)
1558 #define LL_TIM_TIM4_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
1559 #endif /* COMP5 */
1560 #if defined(COMP6)
1561 #define LL_TIM_TIM4_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
1562 #endif /* COMP6 */
1563 #if defined(COMP7)
1564 #define LL_TIM_TIM4_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
1565 #endif /* COMP7 */
1566 /**
1567 * @}
1568 */
1569
1570 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
1571 * @{
1572 */
1573 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
1574 #define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
1575 #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
1576 #define LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
1577 #define LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
1578 #if defined(COMP5)
1579 #define LL_TIM_TIM4_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
1580 #endif /* COMP5 */
1581 #if defined(COMP6)
1582 #define LL_TIM_TIM4_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
1583 #endif /* COMP6 */
1584 #if defined(COMP7)
1585 #define LL_TIM_TIM4_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
1586 #endif /* COMP7 */
1587 /**
1588 * @}
1589 */
1590
1591 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
1592 * @{
1593 */
1594 #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
1595 #if defined(COMP5)
1596 #define LL_TIM_TIM4_TI3_RMP_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
1597 #endif /* COMP5 */
1598 /**
1599 * @}
1600 */
1601
1602 /** @defgroup TIM_LL_EC_TIM4_TI4_RMP TIM4 Timer Input Ch4 Remap
1603 * @{
1604 */
1605 #define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
1606 #if defined(COMP6)
1607 #define LL_TIM_TIM4_TI4_RMP_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
1608 #endif /* COMP6 */
1609 /**
1610 * @}
1611 */
1612
1613 #if defined(TIM5)
1614 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1615 * @{
1616 */
1617 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
1618 #define LL_TIM_TIM5_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
1619 #define LL_TIM_TIM5_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
1620 #define LL_TIM_TIM5_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
1621 #define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
1622 #define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
1623 #define LL_TIM_TIM5_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
1624 #define LL_TIM_TIM5_TI1_RMP_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
1625 #if defined(COMP5)
1626 #define LL_TIM_TIM5_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
1627 #endif /* COMP5 */
1628 #if defined(COMP6)
1629 #define LL_TIM_TIM5_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
1630 #endif /* COMP6 */
1631 #if defined(COMP7)
1632 #define LL_TIM_TIM5_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
1633 #endif /* COMP7 */
1634 /**
1635 * @}
1636 */
1637
1638 /** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 Timer Input Ch2 Remap
1639 * @{
1640 */
1641 #define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
1642 #define LL_TIM_TIM5_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
1643 #define LL_TIM_TIM5_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
1644 #define LL_TIM_TIM5_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
1645 #define LL_TIM_TIM5_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
1646 #if defined(COMP5)
1647 #define LL_TIM_TIM5_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
1648 #endif /* COMP5 */
1649 #if defined(COMP6)
1650 #define LL_TIM_TIM5_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
1651 #endif /* COMP6 */
1652 #if defined(COMP7)
1653 #define LL_TIM_TIM5_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
1654 #endif /* COMP7 */
1655 /**
1656 * @}
1657 */
1658 #endif /* TIM5 */
1659
1660 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1661 * @{
1662 */
1663 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
1664 #define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
1665 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
1666 #define LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
1667 #define LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
1668 /**
1669 * @}
1670 */
1671
1672 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1673 * @{
1674 */
1675 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1676 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
1677 #define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
1678 #define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
1679 #if defined(COMP5)
1680 #define LL_TIM_TIM15_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
1681 #endif /* COMP5 */
1682 #if defined(COMP7)
1683 #define LL_TIM_TIM15_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
1684 #endif /* COMP7 */
1685 /**
1686 * @}
1687 */
1688
1689 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1690 * @{
1691 */
1692 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1693 #define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
1694 #define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
1695 #if defined(COMP6)
1696 #define LL_TIM_TIM15_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
1697 #endif /* COMP6 */
1698 #if defined(COMP7)
1699 #define LL_TIM_TIM15_TI2_RMP_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
1700 #endif /* COMP7 */
1701 /**
1702 * @}
1703 */
1704
1705 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1706 * @{
1707 */
1708 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1709 #if defined(COMP6)
1710 #define LL_TIM_TIM16_TI1_RMP_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
1711 #endif /* COMP6 */
1712 #define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
1713 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
1714 #define LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
1715 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
1716 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
1717 /**
1718 * @}
1719 */
1720
1721 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1722 * @{
1723 */
1724 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1725 #if defined(COMP5)
1726 #define LL_TIM_TIM17_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
1727 #endif /* COMP5 */
1728 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
1729 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
1730 #define LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
1731 #define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
1732 #define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
1733 /**
1734 * @}
1735 */
1736
1737 #if defined(TIM20)
1738 /** @defgroup TIM_LL_EC_TIM20_TI1_RMP TIM20 Timer Input Ch1 Remap
1739 * @{
1740 */
1741 #define LL_TIM_TIM20_TI1_RMP_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
1742 #define LL_TIM_TIM20_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
1743 #define LL_TIM_TIM20_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
1744 #define LL_TIM_TIM20_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
1745 #define LL_TIM_TIM20_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
1746 /**
1747 * @}
1748 */
1749 #endif /* TIM20 */
1750
1751 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1752 * @{
1753 */
1754 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
1755 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1756 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1757 #define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF clear input is connected to COMP3_OUT */
1758 #define LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP4_OUT */
1759 #if defined(COMP5)
1760 #define LL_TIM_OCREF_CLR_INT_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF clear input is connected to COMP5_OUT */
1761 #endif /* COMP5 */
1762 #if defined(COMP6)
1763 #define LL_TIM_OCREF_CLR_INT_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP6_OUT */
1764 #endif /* COMP6 */
1765 #if defined(COMP7)
1766 #define LL_TIM_OCREF_CLR_INT_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF clear input is connected to COMP7_OUT */
1767 #endif /* COMP7 */
1768 /**
1769 * @}
1770 */
1771
1772 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1773 * @{
1774 */
1775 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1776 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1777 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1778 /**
1779 * @}
1780 */
1781
1782 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1783 * @{
1784 */
1785 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1786 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1787 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1788 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1789 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1790 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1791 /**
1792 * @}
1793 */
1794
1795 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1796 * @{
1797 */
1798 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1799 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1800 /**
1801 * @}
1802 */
1803 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1804 * @{
1805 */
1806 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1807 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1808 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1809 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1810 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1811 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1812 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1813 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1814 /**
1815 * @}
1816 */
1817
1818 /** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
1819 * @{
1820 */
1821 #define LL_TIM_HSE_32_NOT_REQUEST 0x00000000U /*!< Clock HSE/32 not requested */
1822 #define LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
1823 /**
1824 * @}
1825 */
1826
1827 /** Legacy definitions for compatibility purpose
1828 @cond 0
1829 */
1830 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1831 /**
1832 @endcond
1833 */
1834
1835 /**
1836 * @}
1837 */
1838
1839 /* Exported macro ------------------------------------------------------------*/
1840 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1841 * @{
1842 */
1843
1844 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1845 * @{
1846 */
1847 /**
1848 * @brief Write a value in TIM register.
1849 * @param __INSTANCE__ TIM Instance
1850 * @param __REG__ Register to be written
1851 * @param __VALUE__ Value to be written in the register
1852 * @retval None
1853 */
1854 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1855
1856 /**
1857 * @brief Read a value in TIM register.
1858 * @param __INSTANCE__ TIM Instance
1859 * @param __REG__ Register to be read
1860 * @retval Register value
1861 */
1862 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1863 /**
1864 * @}
1865 */
1866
1867 /**
1868 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1869 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1870 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1871 * to TIMx_CNT register bit 31)
1872 * @param __CNT__ Counter value
1873 * @retval UIF status bit
1874 */
1875 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1876 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1877
1878 /**
1879 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1880 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1881 * @param __TIMCLK__ timer input clock frequency (in Hz)
1882 * @param __CKD__ This parameter can be one of the following values:
1883 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1884 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1885 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1886 * @param __DT__ deadtime duration (in ns)
1887 * @retval DTG[0:7]
1888 */
1889 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1890 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1891 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1892 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1893 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1894 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1895 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1896 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1897 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1898 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1899 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1900 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1901 0U)
1902
1903 /**
1904 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1905 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1906 * @param __TIMCLK__ timer input clock frequency (in Hz)
1907 * @param __CNTCLK__ counter clock frequency (in Hz)
1908 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1909 */
1910 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1911 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1912
1913 /**
1914 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1915 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1916 * @param __TIMCLK__ timer input clock frequency (in Hz)
1917 * @param __PSC__ prescaler
1918 * @param __FREQ__ output signal frequency (in Hz)
1919 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1920 */
1921 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1922 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1923
1924 /**
1925 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1926 * output signal frequency.
1927 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1928 * @param __TIMCLK__ timer input clock frequency (in Hz)
1929 * @param __PSC__ prescaler
1930 * @param __FREQ__ output signal frequency (in Hz)
1931 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1932 */
1933 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1934 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1935 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1936
1937 /**
1938 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1939 * active/inactive delay.
1940 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1941 * @param __TIMCLK__ timer input clock frequency (in Hz)
1942 * @param __PSC__ prescaler
1943 * @param __DELAY__ timer output compare active/inactive delay (in us)
1944 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1945 */
1946 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1947 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1948 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1949
1950 /**
1951 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1952 * output compare active/inactive delay.
1953 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1954 * @param __TIMCLK__ timer input clock frequency (in Hz)
1955 * @param __PSC__ prescaler
1956 * @param __DELAY__ timer output compare active/inactive delay (in us)
1957 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1958 */
1959 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1960 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1961 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1962
1963 /**
1964 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1965 * (when the timer operates in one pulse mode).
1966 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1967 * @param __TIMCLK__ timer input clock frequency (in Hz)
1968 * @param __PSC__ prescaler
1969 * @param __DELAY__ timer output compare active/inactive delay (in us)
1970 * @param __PULSE__ pulse duration (in us)
1971 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1972 */
1973 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1974 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1975 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1976
1977 /**
1978 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1979 * pulse duration (when the timer operates in one pulse mode).
1980 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1981 * @param __TIMCLK__ timer input clock frequency (in Hz)
1982 * @param __PSC__ prescaler
1983 * @param __DELAY__ timer output compare active/inactive delay (in us)
1984 * @param __PULSE__ pulse duration (in us)
1985 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1986 */
1987 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1988 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1989 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1990
1991 /**
1992 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1993 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1994 * @param __ICPSC__ This parameter can be one of the following values:
1995 * @arg @ref LL_TIM_ICPSC_DIV1
1996 * @arg @ref LL_TIM_ICPSC_DIV2
1997 * @arg @ref LL_TIM_ICPSC_DIV4
1998 * @arg @ref LL_TIM_ICPSC_DIV8
1999 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
2000 */
2001 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
2002 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
2003
2004
2005 /**
2006 * @}
2007 */
2008
2009 /* Exported functions --------------------------------------------------------*/
2010 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
2011 * @{
2012 */
2013
2014 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
2015 * @{
2016 */
2017 /**
2018 * @brief Enable timer counter.
2019 * @rmtoll CR1 CEN LL_TIM_EnableCounter
2020 * @param TIMx Timer instance
2021 * @retval None
2022 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)2023 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
2024 {
2025 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
2026 }
2027
2028 /**
2029 * @brief Disable timer counter.
2030 * @rmtoll CR1 CEN LL_TIM_DisableCounter
2031 * @param TIMx Timer instance
2032 * @retval None
2033 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)2034 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
2035 {
2036 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
2037 }
2038
2039 /**
2040 * @brief Indicates whether the timer counter is enabled.
2041 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
2042 * @param TIMx Timer instance
2043 * @retval State of bit (1 or 0).
2044 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)2045 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
2046 {
2047 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
2048 }
2049
2050 /**
2051 * @brief Enable update event generation.
2052 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
2053 * @param TIMx Timer instance
2054 * @retval None
2055 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)2056 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
2057 {
2058 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
2059 }
2060
2061 /**
2062 * @brief Disable update event generation.
2063 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
2064 * @param TIMx Timer instance
2065 * @retval None
2066 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)2067 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
2068 {
2069 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
2070 }
2071
2072 /**
2073 * @brief Indicates whether update event generation is enabled.
2074 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
2075 * @param TIMx Timer instance
2076 * @retval Inverted state of bit (0 or 1).
2077 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)2078 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
2079 {
2080 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
2081 }
2082
2083 /**
2084 * @brief Set update event source
2085 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
2086 * generate an update interrupt or DMA request if enabled:
2087 * - Counter overflow/underflow
2088 * - Setting the UG bit
2089 * - Update generation through the slave mode controller
2090 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
2091 * overflow/underflow generates an update interrupt or DMA request if enabled.
2092 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
2093 * @param TIMx Timer instance
2094 * @param UpdateSource This parameter can be one of the following values:
2095 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2096 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2097 * @retval None
2098 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)2099 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
2100 {
2101 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
2102 }
2103
2104 /**
2105 * @brief Get actual event update source
2106 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
2107 * @param TIMx Timer instance
2108 * @retval Returned value can be one of the following values:
2109 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2110 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2111 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)2112 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
2113 {
2114 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
2115 }
2116
2117 /**
2118 * @brief Set one pulse mode (one shot v.s. repetitive).
2119 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
2120 * @param TIMx Timer instance
2121 * @param OnePulseMode This parameter can be one of the following values:
2122 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2123 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2124 * @retval None
2125 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)2126 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
2127 {
2128 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
2129 }
2130
2131 /**
2132 * @brief Get actual one pulse mode.
2133 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
2134 * @param TIMx Timer instance
2135 * @retval Returned value can be one of the following values:
2136 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2137 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2138 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)2139 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
2140 {
2141 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
2142 }
2143
2144 /**
2145 * @brief Set the timer counter counting mode.
2146 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2147 * check whether or not the counter mode selection feature is supported
2148 * by a timer instance.
2149 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2150 * requires a timer reset to avoid unexpected direction
2151 * due to DIR bit readonly in center aligned mode.
2152 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
2153 * CR1 CMS LL_TIM_SetCounterMode
2154 * @param TIMx Timer instance
2155 * @param CounterMode This parameter can be one of the following values:
2156 * @arg @ref LL_TIM_COUNTERMODE_UP
2157 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2158 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2159 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2160 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2161 * @retval None
2162 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)2163 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
2164 {
2165 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
2166 }
2167
2168 /**
2169 * @brief Get actual counter mode.
2170 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2171 * check whether or not the counter mode selection feature is supported
2172 * by a timer instance.
2173 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
2174 * CR1 CMS LL_TIM_GetCounterMode
2175 * @param TIMx Timer instance
2176 * @retval Returned value can be one of the following values:
2177 * @arg @ref LL_TIM_COUNTERMODE_UP
2178 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2179 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2180 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2181 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2182 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)2183 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
2184 {
2185 uint32_t counter_mode;
2186
2187 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
2188
2189 if (counter_mode == 0U)
2190 {
2191 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2192 }
2193
2194 return counter_mode;
2195 }
2196
2197 /**
2198 * @brief Enable auto-reload (ARR) preload.
2199 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
2200 * @param TIMx Timer instance
2201 * @retval None
2202 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)2203 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
2204 {
2205 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
2206 }
2207
2208 /**
2209 * @brief Disable auto-reload (ARR) preload.
2210 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
2211 * @param TIMx Timer instance
2212 * @retval None
2213 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)2214 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
2215 {
2216 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
2217 }
2218
2219 /**
2220 * @brief Indicates whether auto-reload (ARR) preload is enabled.
2221 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
2222 * @param TIMx Timer instance
2223 * @retval State of bit (1 or 0).
2224 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)2225 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
2226 {
2227 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
2228 }
2229
2230 /**
2231 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
2232 * (when supported) and the digital filters.
2233 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2234 * whether or not the clock division feature is supported by the timer
2235 * instance.
2236 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
2237 * @param TIMx Timer instance
2238 * @param ClockDivision This parameter can be one of the following values:
2239 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2240 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2241 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2242 * @retval None
2243 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)2244 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
2245 {
2246 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
2247 }
2248
2249 /**
2250 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
2251 * generators (when supported) and the digital filters.
2252 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2253 * whether or not the clock division feature is supported by the timer
2254 * instance.
2255 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
2256 * @param TIMx Timer instance
2257 * @retval Returned value can be one of the following values:
2258 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2259 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2260 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2261 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)2262 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
2263 {
2264 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
2265 }
2266
2267 /**
2268 * @brief Set the counter value.
2269 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2270 * whether or not a timer instance supports a 32 bits counter.
2271 * @note If dithering is activated, pay attention to the Counter value interpretation
2272 * @rmtoll CNT CNT LL_TIM_SetCounter
2273 * @param TIMx Timer instance
2274 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2275 * @retval None
2276 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2277 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2278 {
2279 WRITE_REG(TIMx->CNT, Counter);
2280 }
2281
2282 /**
2283 * @brief Get the counter value.
2284 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2285 * whether or not a timer instance supports a 32 bits counter.
2286 * @note If dithering is activated, pay attention to the Counter value interpretation
2287 * @rmtoll CNT CNT LL_TIM_GetCounter
2288 * @param TIMx Timer instance
2289 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2290 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)2291 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
2292 {
2293 return (uint32_t)(READ_REG(TIMx->CNT));
2294 }
2295
2296 /**
2297 * @brief Get the current direction of the counter
2298 * @rmtoll CR1 DIR LL_TIM_GetDirection
2299 * @param TIMx Timer instance
2300 * @retval Returned value can be one of the following values:
2301 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2302 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2303 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)2304 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
2305 {
2306 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2307 }
2308
2309 /**
2310 * @brief Set the prescaler value.
2311 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2312 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2313 * prescaler ratio is taken into account at the next update event.
2314 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2315 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2316 * @param TIMx Timer instance
2317 * @param Prescaler between Min_Data=0 and Max_Data=65535
2318 * @retval None
2319 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2320 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2321 {
2322 WRITE_REG(TIMx->PSC, Prescaler);
2323 }
2324
2325 /**
2326 * @brief Get the prescaler value.
2327 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2328 * @param TIMx Timer instance
2329 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2330 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)2331 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
2332 {
2333 return (uint32_t)(READ_REG(TIMx->PSC));
2334 }
2335
2336 /**
2337 * @brief Set the auto-reload value.
2338 * @note The counter is blocked while the auto-reload value is null.
2339 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2340 * whether or not a timer instance supports a 32 bits counter.
2341 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2342 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2343 * parameter.
2344 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2345 * @param TIMx Timer instance
2346 * @param AutoReload between Min_Data=0 and Max_Data=65535
2347 * @retval None
2348 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2349 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2350 {
2351 WRITE_REG(TIMx->ARR, AutoReload);
2352 }
2353
2354 /**
2355 * @brief Get the auto-reload value.
2356 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2357 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2358 * whether or not a timer instance supports a 32 bits counter.
2359 * @note If dithering is activated, pay attention to the returned value interpretation
2360 * @param TIMx Timer instance
2361 * @retval Auto-reload value
2362 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2363 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2364 {
2365 return (uint32_t)(READ_REG(TIMx->ARR));
2366 }
2367
2368 /**
2369 * @brief Set the repetition counter value.
2370 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2371 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2372 * whether or not a timer instance supports a repetition counter.
2373 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2374 * @param TIMx Timer instance
2375 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2376 * @retval None
2377 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2378 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2379 {
2380 WRITE_REG(TIMx->RCR, RepetitionCounter);
2381 }
2382
2383 /**
2384 * @brief Get the repetition counter value.
2385 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2386 * whether or not a timer instance supports a repetition counter.
2387 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2388 * @param TIMx Timer instance
2389 * @retval Repetition counter value
2390 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2391 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2392 {
2393 return (uint32_t)(READ_REG(TIMx->RCR));
2394 }
2395
2396 /**
2397 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2398 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2399 * in an atomic way.
2400 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2401 * @param TIMx Timer instance
2402 * @retval None
2403 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2404 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2405 {
2406 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2407 }
2408
2409 /**
2410 * @brief Disable update interrupt flag (UIF) remapping.
2411 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2412 * @param TIMx Timer instance
2413 * @retval None
2414 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2415 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2416 {
2417 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2418 }
2419
2420 /**
2421 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2422 * @param Counter Counter value
2423 * @retval State of bit (1 or 0).
2424 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2425 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2426 {
2427 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2428 }
2429
2430 /**
2431 * @brief Enable dithering.
2432 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2433 * a timer instance provides dithering.
2434 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2435 * @param TIMx Timer instance
2436 * @retval None
2437 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2438 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2439 {
2440 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2441 }
2442
2443 /**
2444 * @brief Disable dithering.
2445 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2446 * a timer instance provides dithering.
2447 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2448 * @param TIMx Timer instance
2449 * @retval None
2450 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2451 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2452 {
2453 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2454 }
2455
2456 /**
2457 * @brief Indicates whether dithering is activated.
2458 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2459 * a timer instance provides dithering.
2460 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2461 * @param TIMx Timer instance
2462 * @retval State of bit (1 or 0).
2463 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2464 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2465 {
2466 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2467 }
2468
2469 /**
2470 * @}
2471 */
2472
2473 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2474 * @{
2475 */
2476 /**
2477 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2478 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2479 * they are updated only when a commutation event (COM) occurs.
2480 * @note Only on channels that have a complementary output.
2481 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2482 * whether or not a timer instance is able to generate a commutation event.
2483 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2484 * @param TIMx Timer instance
2485 * @retval None
2486 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2487 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2488 {
2489 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2490 }
2491
2492 /**
2493 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2494 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2495 * whether or not a timer instance is able to generate a commutation event.
2496 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2497 * @param TIMx Timer instance
2498 * @retval None
2499 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2500 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2501 {
2502 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2503 }
2504
2505 /**
2506 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2507 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2508 * @param TIMx Timer instance
2509 * @retval State of bit (1 or 0).
2510 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2511 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2512 {
2513 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2514 }
2515
2516 /**
2517 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2518 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2519 * whether or not a timer instance is able to generate a commutation event.
2520 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2521 * @param TIMx Timer instance
2522 * @param CCUpdateSource This parameter can be one of the following values:
2523 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2524 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2525 * @retval None
2526 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2527 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2528 {
2529 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2530 }
2531
2532 /**
2533 * @brief Set the trigger of the capture/compare DMA request.
2534 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2535 * @param TIMx Timer instance
2536 * @param DMAReqTrigger This parameter can be one of the following values:
2537 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2538 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2539 * @retval None
2540 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2541 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2542 {
2543 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2544 }
2545
2546 /**
2547 * @brief Get actual trigger of the capture/compare DMA request.
2548 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2549 * @param TIMx Timer instance
2550 * @retval Returned value can be one of the following values:
2551 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2552 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2553 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2554 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2555 {
2556 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2557 }
2558
2559 /**
2560 * @brief Set the lock level to freeze the
2561 * configuration of several capture/compare parameters.
2562 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2563 * the lock mechanism is supported by a timer instance.
2564 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2565 * @param TIMx Timer instance
2566 * @param LockLevel This parameter can be one of the following values:
2567 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2568 * @arg @ref LL_TIM_LOCKLEVEL_1
2569 * @arg @ref LL_TIM_LOCKLEVEL_2
2570 * @arg @ref LL_TIM_LOCKLEVEL_3
2571 * @retval None
2572 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2573 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2574 {
2575 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2576 }
2577
2578 /**
2579 * @brief Enable capture/compare channels.
2580 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2581 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2582 * CCER CC2E LL_TIM_CC_EnableChannel\n
2583 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2584 * CCER CC3E LL_TIM_CC_EnableChannel\n
2585 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2586 * CCER CC4E LL_TIM_CC_EnableChannel\n
2587 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2588 * CCER CC5E LL_TIM_CC_EnableChannel\n
2589 * CCER CC6E LL_TIM_CC_EnableChannel
2590 * @param TIMx Timer instance
2591 * @param Channels This parameter can be a combination of the following values:
2592 * @arg @ref LL_TIM_CHANNEL_CH1
2593 * @arg @ref LL_TIM_CHANNEL_CH1N
2594 * @arg @ref LL_TIM_CHANNEL_CH2
2595 * @arg @ref LL_TIM_CHANNEL_CH2N
2596 * @arg @ref LL_TIM_CHANNEL_CH3
2597 * @arg @ref LL_TIM_CHANNEL_CH3N
2598 * @arg @ref LL_TIM_CHANNEL_CH4
2599 * @arg @ref LL_TIM_CHANNEL_CH4N
2600 * @arg @ref LL_TIM_CHANNEL_CH5
2601 * @arg @ref LL_TIM_CHANNEL_CH6
2602 * @retval None
2603 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2604 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2605 {
2606 SET_BIT(TIMx->CCER, Channels);
2607 }
2608
2609 /**
2610 * @brief Disable capture/compare channels.
2611 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2612 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2613 * CCER CC2E LL_TIM_CC_DisableChannel\n
2614 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2615 * CCER CC3E LL_TIM_CC_DisableChannel\n
2616 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2617 * CCER CC4E LL_TIM_CC_DisableChannel\n
2618 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2619 * CCER CC5E LL_TIM_CC_DisableChannel\n
2620 * CCER CC6E LL_TIM_CC_DisableChannel
2621 * @param TIMx Timer instance
2622 * @param Channels This parameter can be a combination of the following values:
2623 * @arg @ref LL_TIM_CHANNEL_CH1
2624 * @arg @ref LL_TIM_CHANNEL_CH1N
2625 * @arg @ref LL_TIM_CHANNEL_CH2
2626 * @arg @ref LL_TIM_CHANNEL_CH2N
2627 * @arg @ref LL_TIM_CHANNEL_CH3
2628 * @arg @ref LL_TIM_CHANNEL_CH3N
2629 * @arg @ref LL_TIM_CHANNEL_CH4
2630 * @arg @ref LL_TIM_CHANNEL_CH4N
2631 * @arg @ref LL_TIM_CHANNEL_CH5
2632 * @arg @ref LL_TIM_CHANNEL_CH6
2633 * @retval None
2634 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2635 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2636 {
2637 CLEAR_BIT(TIMx->CCER, Channels);
2638 }
2639
2640 /**
2641 * @brief Indicate whether channel(s) is(are) enabled.
2642 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2643 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2644 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2645 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2646 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2647 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2648 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2649 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2650 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2651 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2652 * @param TIMx Timer instance
2653 * @param Channels This parameter can be a combination of the following values:
2654 * @arg @ref LL_TIM_CHANNEL_CH1
2655 * @arg @ref LL_TIM_CHANNEL_CH1N
2656 * @arg @ref LL_TIM_CHANNEL_CH2
2657 * @arg @ref LL_TIM_CHANNEL_CH2N
2658 * @arg @ref LL_TIM_CHANNEL_CH3
2659 * @arg @ref LL_TIM_CHANNEL_CH3N
2660 * @arg @ref LL_TIM_CHANNEL_CH4
2661 * @arg @ref LL_TIM_CHANNEL_CH4N
2662 * @arg @ref LL_TIM_CHANNEL_CH5
2663 * @arg @ref LL_TIM_CHANNEL_CH6
2664 * @retval State of bit (1 or 0).
2665 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2666 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2667 {
2668 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2669 }
2670
2671 /**
2672 * @}
2673 */
2674
2675 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2676 * @{
2677 */
2678 /**
2679 * @brief Configure an output channel.
2680 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2681 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2682 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2683 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2684 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2685 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2686 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2687 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2688 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2689 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2690 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2691 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2692 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2693 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2694 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2695 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2696 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2697 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2698 * @param TIMx Timer instance
2699 * @param Channel This parameter can be one of the following values:
2700 * @arg @ref LL_TIM_CHANNEL_CH1
2701 * @arg @ref LL_TIM_CHANNEL_CH2
2702 * @arg @ref LL_TIM_CHANNEL_CH3
2703 * @arg @ref LL_TIM_CHANNEL_CH4
2704 * @arg @ref LL_TIM_CHANNEL_CH5
2705 * @arg @ref LL_TIM_CHANNEL_CH6
2706 * @param Configuration This parameter must be a combination of all the following values:
2707 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2708 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2709 * @retval None
2710 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2711 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2712 {
2713 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2714 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2715 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2716 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2717 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2718 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2719 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2720 }
2721
2722 /**
2723 * @brief Define the behavior of the output reference signal OCxREF from which
2724 * OCx and OCxN (when relevant) are derived.
2725 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2726 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2727 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2728 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2729 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2730 * CCMR3 OC6M LL_TIM_OC_SetMode
2731 * @param TIMx Timer instance
2732 * @param Channel This parameter can be one of the following values:
2733 * @arg @ref LL_TIM_CHANNEL_CH1
2734 * @arg @ref LL_TIM_CHANNEL_CH2
2735 * @arg @ref LL_TIM_CHANNEL_CH3
2736 * @arg @ref LL_TIM_CHANNEL_CH4
2737 * @arg @ref LL_TIM_CHANNEL_CH5
2738 * @arg @ref LL_TIM_CHANNEL_CH6
2739 * @param Mode This parameter can be one of the following values:
2740 * @arg @ref LL_TIM_OCMODE_FROZEN
2741 * @arg @ref LL_TIM_OCMODE_ACTIVE
2742 * @arg @ref LL_TIM_OCMODE_INACTIVE
2743 * @arg @ref LL_TIM_OCMODE_TOGGLE
2744 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2745 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2746 * @arg @ref LL_TIM_OCMODE_PWM1
2747 * @arg @ref LL_TIM_OCMODE_PWM2
2748 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2749 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2750 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2751 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2752 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2753 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2754 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2755 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2756 * @retval None
2757 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2758 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2759 {
2760 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2761 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2762 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2763 }
2764
2765 /**
2766 * @brief Get the output compare mode of an output channel.
2767 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2768 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2769 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2770 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2771 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2772 * CCMR3 OC6M LL_TIM_OC_GetMode
2773 * @param TIMx Timer instance
2774 * @param Channel This parameter can be one of the following values:
2775 * @arg @ref LL_TIM_CHANNEL_CH1
2776 * @arg @ref LL_TIM_CHANNEL_CH2
2777 * @arg @ref LL_TIM_CHANNEL_CH3
2778 * @arg @ref LL_TIM_CHANNEL_CH4
2779 * @arg @ref LL_TIM_CHANNEL_CH5
2780 * @arg @ref LL_TIM_CHANNEL_CH6
2781 * @retval Returned value can be one of the following values:
2782 * @arg @ref LL_TIM_OCMODE_FROZEN
2783 * @arg @ref LL_TIM_OCMODE_ACTIVE
2784 * @arg @ref LL_TIM_OCMODE_INACTIVE
2785 * @arg @ref LL_TIM_OCMODE_TOGGLE
2786 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2787 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2788 * @arg @ref LL_TIM_OCMODE_PWM1
2789 * @arg @ref LL_TIM_OCMODE_PWM2
2790 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2791 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2792 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2793 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2794 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2795 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2796 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2797 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2798 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2799 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2800 {
2801 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2802 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2803 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2804 }
2805
2806 /**
2807 * @brief Set the polarity of an output channel.
2808 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2809 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2810 * CCER CC2P LL_TIM_OC_SetPolarity\n
2811 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2812 * CCER CC3P LL_TIM_OC_SetPolarity\n
2813 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2814 * CCER CC4P LL_TIM_OC_SetPolarity\n
2815 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2816 * CCER CC5P LL_TIM_OC_SetPolarity\n
2817 * CCER CC6P LL_TIM_OC_SetPolarity
2818 * @param TIMx Timer instance
2819 * @param Channel This parameter can be one of the following values:
2820 * @arg @ref LL_TIM_CHANNEL_CH1
2821 * @arg @ref LL_TIM_CHANNEL_CH1N
2822 * @arg @ref LL_TIM_CHANNEL_CH2
2823 * @arg @ref LL_TIM_CHANNEL_CH2N
2824 * @arg @ref LL_TIM_CHANNEL_CH3
2825 * @arg @ref LL_TIM_CHANNEL_CH3N
2826 * @arg @ref LL_TIM_CHANNEL_CH4
2827 * @arg @ref LL_TIM_CHANNEL_CH4N
2828 * @arg @ref LL_TIM_CHANNEL_CH5
2829 * @arg @ref LL_TIM_CHANNEL_CH6
2830 * @param Polarity This parameter can be one of the following values:
2831 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2832 * @arg @ref LL_TIM_OCPOLARITY_LOW
2833 * @retval None
2834 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2835 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2836 {
2837 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2838 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2839 }
2840
2841 /**
2842 * @brief Get the polarity of an output channel.
2843 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2844 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2845 * CCER CC2P LL_TIM_OC_GetPolarity\n
2846 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2847 * CCER CC3P LL_TIM_OC_GetPolarity\n
2848 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2849 * CCER CC4P LL_TIM_OC_GetPolarity\n
2850 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2851 * CCER CC5P LL_TIM_OC_GetPolarity\n
2852 * CCER CC6P LL_TIM_OC_GetPolarity
2853 * @param TIMx Timer instance
2854 * @param Channel This parameter can be one of the following values:
2855 * @arg @ref LL_TIM_CHANNEL_CH1
2856 * @arg @ref LL_TIM_CHANNEL_CH1N
2857 * @arg @ref LL_TIM_CHANNEL_CH2
2858 * @arg @ref LL_TIM_CHANNEL_CH2N
2859 * @arg @ref LL_TIM_CHANNEL_CH3
2860 * @arg @ref LL_TIM_CHANNEL_CH3N
2861 * @arg @ref LL_TIM_CHANNEL_CH4
2862 * @arg @ref LL_TIM_CHANNEL_CH4N
2863 * @arg @ref LL_TIM_CHANNEL_CH5
2864 * @arg @ref LL_TIM_CHANNEL_CH6
2865 * @retval Returned value can be one of the following values:
2866 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2867 * @arg @ref LL_TIM_OCPOLARITY_LOW
2868 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2869 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2870 {
2871 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2872 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2873 }
2874
2875 /**
2876 * @brief Set the IDLE state of an output channel
2877 * @note This function is significant only for the timer instances
2878 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2879 * can be used to check whether or not a timer instance provides
2880 * a break input.
2881 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2882 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2883 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2884 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2885 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2886 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2887 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2888 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2889 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2890 * CR2 OIS6 LL_TIM_OC_SetIdleState
2891 * @param TIMx Timer instance
2892 * @param Channel This parameter can be one of the following values:
2893 * @arg @ref LL_TIM_CHANNEL_CH1
2894 * @arg @ref LL_TIM_CHANNEL_CH1N
2895 * @arg @ref LL_TIM_CHANNEL_CH2
2896 * @arg @ref LL_TIM_CHANNEL_CH2N
2897 * @arg @ref LL_TIM_CHANNEL_CH3
2898 * @arg @ref LL_TIM_CHANNEL_CH3N
2899 * @arg @ref LL_TIM_CHANNEL_CH4
2900 * @arg @ref LL_TIM_CHANNEL_CH4N
2901 * @arg @ref LL_TIM_CHANNEL_CH5
2902 * @arg @ref LL_TIM_CHANNEL_CH6
2903 * @param IdleState This parameter can be one of the following values:
2904 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2905 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2906 * @retval None
2907 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2908 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2909 {
2910 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2911 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2912 }
2913
2914 /**
2915 * @brief Get the IDLE state of an output channel
2916 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2917 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2918 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2919 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2920 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2921 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2922 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2923 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2924 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2925 * CR2 OIS6 LL_TIM_OC_GetIdleState
2926 * @param TIMx Timer instance
2927 * @param Channel This parameter can be one of the following values:
2928 * @arg @ref LL_TIM_CHANNEL_CH1
2929 * @arg @ref LL_TIM_CHANNEL_CH1N
2930 * @arg @ref LL_TIM_CHANNEL_CH2
2931 * @arg @ref LL_TIM_CHANNEL_CH2N
2932 * @arg @ref LL_TIM_CHANNEL_CH3
2933 * @arg @ref LL_TIM_CHANNEL_CH3N
2934 * @arg @ref LL_TIM_CHANNEL_CH4
2935 * @arg @ref LL_TIM_CHANNEL_CH4N
2936 * @arg @ref LL_TIM_CHANNEL_CH5
2937 * @arg @ref LL_TIM_CHANNEL_CH6
2938 * @retval Returned value can be one of the following values:
2939 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2940 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2941 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2942 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2943 {
2944 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2945 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2946 }
2947
2948 /**
2949 * @brief Enable fast mode for the output channel.
2950 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2951 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2952 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2953 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2954 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2955 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2956 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2957 * @param TIMx Timer instance
2958 * @param Channel This parameter can be one of the following values:
2959 * @arg @ref LL_TIM_CHANNEL_CH1
2960 * @arg @ref LL_TIM_CHANNEL_CH2
2961 * @arg @ref LL_TIM_CHANNEL_CH3
2962 * @arg @ref LL_TIM_CHANNEL_CH4
2963 * @arg @ref LL_TIM_CHANNEL_CH5
2964 * @arg @ref LL_TIM_CHANNEL_CH6
2965 * @retval None
2966 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2967 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2968 {
2969 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2970 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2971 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2972
2973 }
2974
2975 /**
2976 * @brief Disable fast mode for the output channel.
2977 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2978 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2979 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2980 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2981 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2982 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2983 * @param TIMx Timer instance
2984 * @param Channel This parameter can be one of the following values:
2985 * @arg @ref LL_TIM_CHANNEL_CH1
2986 * @arg @ref LL_TIM_CHANNEL_CH2
2987 * @arg @ref LL_TIM_CHANNEL_CH3
2988 * @arg @ref LL_TIM_CHANNEL_CH4
2989 * @arg @ref LL_TIM_CHANNEL_CH5
2990 * @arg @ref LL_TIM_CHANNEL_CH6
2991 * @retval None
2992 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2993 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2994 {
2995 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2996 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2997 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2998
2999 }
3000
3001 /**
3002 * @brief Indicates whether fast mode is enabled for the output channel.
3003 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
3004 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
3005 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
3006 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
3007 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
3008 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
3009 * @param TIMx Timer instance
3010 * @param Channel This parameter can be one of the following values:
3011 * @arg @ref LL_TIM_CHANNEL_CH1
3012 * @arg @ref LL_TIM_CHANNEL_CH2
3013 * @arg @ref LL_TIM_CHANNEL_CH3
3014 * @arg @ref LL_TIM_CHANNEL_CH4
3015 * @arg @ref LL_TIM_CHANNEL_CH5
3016 * @arg @ref LL_TIM_CHANNEL_CH6
3017 * @retval State of bit (1 or 0).
3018 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)3019 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
3020 {
3021 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3022 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3023 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
3024 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3025 }
3026
3027 /**
3028 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
3029 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
3030 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
3031 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
3032 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
3033 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
3034 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
3035 * @param TIMx Timer instance
3036 * @param Channel This parameter can be one of the following values:
3037 * @arg @ref LL_TIM_CHANNEL_CH1
3038 * @arg @ref LL_TIM_CHANNEL_CH2
3039 * @arg @ref LL_TIM_CHANNEL_CH3
3040 * @arg @ref LL_TIM_CHANNEL_CH4
3041 * @arg @ref LL_TIM_CHANNEL_CH5
3042 * @arg @ref LL_TIM_CHANNEL_CH6
3043 * @retval None
3044 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)3045 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
3046 {
3047 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3048 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3049 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
3050 }
3051
3052 /**
3053 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
3054 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
3055 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
3056 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
3057 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
3058 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
3059 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
3060 * @param TIMx Timer instance
3061 * @param Channel This parameter can be one of the following values:
3062 * @arg @ref LL_TIM_CHANNEL_CH1
3063 * @arg @ref LL_TIM_CHANNEL_CH2
3064 * @arg @ref LL_TIM_CHANNEL_CH3
3065 * @arg @ref LL_TIM_CHANNEL_CH4
3066 * @arg @ref LL_TIM_CHANNEL_CH5
3067 * @arg @ref LL_TIM_CHANNEL_CH6
3068 * @retval None
3069 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)3070 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
3071 {
3072 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3073 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3074 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
3075 }
3076
3077 /**
3078 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
3079 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
3080 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
3081 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
3082 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
3083 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
3084 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
3085 * @param TIMx Timer instance
3086 * @param Channel This parameter can be one of the following values:
3087 * @arg @ref LL_TIM_CHANNEL_CH1
3088 * @arg @ref LL_TIM_CHANNEL_CH2
3089 * @arg @ref LL_TIM_CHANNEL_CH3
3090 * @arg @ref LL_TIM_CHANNEL_CH4
3091 * @arg @ref LL_TIM_CHANNEL_CH5
3092 * @arg @ref LL_TIM_CHANNEL_CH6
3093 * @retval State of bit (1 or 0).
3094 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)3095 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
3096 {
3097 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3098 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3099 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
3100 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3101 }
3102
3103 /**
3104 * @brief Enable clearing the output channel on an external event.
3105 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3106 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3107 * or not a timer instance can clear the OCxREF signal on an external event.
3108 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
3109 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
3110 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
3111 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
3112 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
3113 * CCMR3 OC6CE LL_TIM_OC_EnableClear
3114 * @param TIMx Timer instance
3115 * @param Channel This parameter can be one of the following values:
3116 * @arg @ref LL_TIM_CHANNEL_CH1
3117 * @arg @ref LL_TIM_CHANNEL_CH2
3118 * @arg @ref LL_TIM_CHANNEL_CH3
3119 * @arg @ref LL_TIM_CHANNEL_CH4
3120 * @arg @ref LL_TIM_CHANNEL_CH5
3121 * @arg @ref LL_TIM_CHANNEL_CH6
3122 * @retval None
3123 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)3124 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3125 {
3126 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3127 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3128 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3129 }
3130
3131 /**
3132 * @brief Disable clearing the output channel on an external event.
3133 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3134 * or not a timer instance can clear the OCxREF signal on an external event.
3135 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
3136 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
3137 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
3138 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
3139 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
3140 * CCMR3 OC6CE LL_TIM_OC_DisableClear
3141 * @param TIMx Timer instance
3142 * @param Channel This parameter can be one of the following values:
3143 * @arg @ref LL_TIM_CHANNEL_CH1
3144 * @arg @ref LL_TIM_CHANNEL_CH2
3145 * @arg @ref LL_TIM_CHANNEL_CH3
3146 * @arg @ref LL_TIM_CHANNEL_CH4
3147 * @arg @ref LL_TIM_CHANNEL_CH5
3148 * @arg @ref LL_TIM_CHANNEL_CH6
3149 * @retval None
3150 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)3151 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3152 {
3153 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3154 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3155 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3156 }
3157
3158 /**
3159 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
3160 * @note This function enables clearing the output channel on an external event.
3161 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3162 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3163 * or not a timer instance can clear the OCxREF signal on an external event.
3164 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
3165 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
3166 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
3167 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
3168 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
3169 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
3170 * @param TIMx Timer instance
3171 * @param Channel This parameter can be one of the following values:
3172 * @arg @ref LL_TIM_CHANNEL_CH1
3173 * @arg @ref LL_TIM_CHANNEL_CH2
3174 * @arg @ref LL_TIM_CHANNEL_CH3
3175 * @arg @ref LL_TIM_CHANNEL_CH4
3176 * @arg @ref LL_TIM_CHANNEL_CH5
3177 * @arg @ref LL_TIM_CHANNEL_CH6
3178 * @retval State of bit (1 or 0).
3179 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)3180 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
3181 {
3182 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3183 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3184 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
3185 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3186 }
3187
3188 /**
3189 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
3190 * the Ocx and OCxN signals).
3191 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3192 * dead-time insertion feature is supported by a timer instance.
3193 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
3194 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
3195 * @param TIMx Timer instance
3196 * @param DeadTime between Min_Data=0 and Max_Data=255
3197 * @retval None
3198 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)3199 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
3200 {
3201 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
3202 }
3203
3204 /**
3205 * @brief Set compare value for output channel 1 (TIMx_CCR1).
3206 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3207 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3208 * whether or not a timer instance supports a 32 bits counter.
3209 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3210 * output channel 1 is supported by a timer instance.
3211 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3212 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
3213 * @param TIMx Timer instance
3214 * @param CompareValue between Min_Data=0 and Max_Data=65535
3215 * @retval None
3216 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)3217 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
3218 {
3219 WRITE_REG(TIMx->CCR1, CompareValue);
3220 }
3221
3222 /**
3223 * @brief Set compare value for output channel 2 (TIMx_CCR2).
3224 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3225 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3226 * whether or not a timer instance supports a 32 bits counter.
3227 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3228 * output channel 2 is supported by a timer instance.
3229 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3230 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
3231 * @param TIMx Timer instance
3232 * @param CompareValue between Min_Data=0 and Max_Data=65535
3233 * @retval None
3234 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)3235 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
3236 {
3237 WRITE_REG(TIMx->CCR2, CompareValue);
3238 }
3239
3240 /**
3241 * @brief Set compare value for output channel 3 (TIMx_CCR3).
3242 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3243 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3244 * whether or not a timer instance supports a 32 bits counter.
3245 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3246 * output channel is supported by a timer instance.
3247 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3248 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
3249 * @param TIMx Timer instance
3250 * @param CompareValue between Min_Data=0 and Max_Data=65535
3251 * @retval None
3252 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)3253 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
3254 {
3255 WRITE_REG(TIMx->CCR3, CompareValue);
3256 }
3257
3258 /**
3259 * @brief Set compare value for output channel 4 (TIMx_CCR4).
3260 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3261 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3262 * whether or not a timer instance supports a 32 bits counter.
3263 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3264 * output channel 4 is supported by a timer instance.
3265 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3266 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
3267 * @param TIMx Timer instance
3268 * @param CompareValue between Min_Data=0 and Max_Data=65535
3269 * @retval None
3270 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)3271 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
3272 {
3273 WRITE_REG(TIMx->CCR4, CompareValue);
3274 }
3275
3276 /**
3277 * @brief Set compare value for output channel 5 (TIMx_CCR5).
3278 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3279 * output channel 5 is supported by a timer instance.
3280 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3281 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3282 * @param TIMx Timer instance
3283 * @param CompareValue between Min_Data=0 and Max_Data=65535
3284 * @retval None
3285 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3286 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3287 {
3288 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3289 }
3290
3291 /**
3292 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3293 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3294 * output channel 6 is supported by a timer instance.
3295 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3296 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3297 * @param TIMx Timer instance
3298 * @param CompareValue between Min_Data=0 and Max_Data=65535
3299 * @retval None
3300 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3301 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3302 {
3303 WRITE_REG(TIMx->CCR6, CompareValue);
3304 }
3305
3306 /**
3307 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3308 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3309 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3310 * whether or not a timer instance supports a 32 bits counter.
3311 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3312 * output channel 1 is supported by a timer instance.
3313 * @note If dithering is activated, pay attention to the returned value interpretation.
3314 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3315 * @param TIMx Timer instance
3316 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3317 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)3318 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
3319 {
3320 return (uint32_t)(READ_REG(TIMx->CCR1));
3321 }
3322
3323 /**
3324 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3325 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3326 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3327 * whether or not a timer instance supports a 32 bits counter.
3328 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3329 * output channel 2 is supported by a timer instance.
3330 * @note If dithering is activated, pay attention to the returned value interpretation.
3331 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3332 * @param TIMx Timer instance
3333 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3334 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)3335 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
3336 {
3337 return (uint32_t)(READ_REG(TIMx->CCR2));
3338 }
3339
3340 /**
3341 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3342 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3343 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3344 * whether or not a timer instance supports a 32 bits counter.
3345 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3346 * output channel 3 is supported by a timer instance.
3347 * @note If dithering is activated, pay attention to the returned value interpretation.
3348 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3349 * @param TIMx Timer instance
3350 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3351 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)3352 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
3353 {
3354 return (uint32_t)(READ_REG(TIMx->CCR3));
3355 }
3356
3357 /**
3358 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3359 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3360 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3361 * whether or not a timer instance supports a 32 bits counter.
3362 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3363 * output channel 4 is supported by a timer instance.
3364 * @note If dithering is activated, pay attention to the returned value interpretation.
3365 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3366 * @param TIMx Timer instance
3367 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3368 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3369 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3370 {
3371 return (uint32_t)(READ_REG(TIMx->CCR4));
3372 }
3373
3374 /**
3375 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3376 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3377 * output channel 5 is supported by a timer instance.
3378 * @note If dithering is activated, pay attention to the returned value interpretation.
3379 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3380 * @param TIMx Timer instance
3381 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3382 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3383 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3384 {
3385 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3386 }
3387
3388 /**
3389 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3390 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3391 * output channel 6 is supported by a timer instance.
3392 * @note If dithering is activated, pay attention to the returned value interpretation.
3393 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3394 * @param TIMx Timer instance
3395 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3396 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3397 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3398 {
3399 return (uint32_t)(READ_REG(TIMx->CCR6));
3400 }
3401
3402 /**
3403 * @brief Select on which reference signal the OC5REF is combined to.
3404 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3405 * whether or not a timer instance supports the combined 3-phase PWM mode.
3406 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3407 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3408 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3409 * @param TIMx Timer instance
3410 * @param GroupCH5 This parameter can be a combination of the following values:
3411 * @arg @ref LL_TIM_GROUPCH5_NONE
3412 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3413 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3414 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3415 * @retval None
3416 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3417 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3418 {
3419 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3420 }
3421
3422 /**
3423 * @brief Set the pulse on compare pulse width prescaler.
3424 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3425 * whether or not the pulse on compare feature is supported by the timer
3426 * instance.
3427 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3428 * @param TIMx Timer instance
3429 * @param PulseWidthPrescaler This parameter can be one of the following values:
3430 * @arg @ref LL_TIM_PWPRSC_X1
3431 * @arg @ref LL_TIM_PWPRSC_X2
3432 * @arg @ref LL_TIM_PWPRSC_X4
3433 * @arg @ref LL_TIM_PWPRSC_X8
3434 * @arg @ref LL_TIM_PWPRSC_X16
3435 * @arg @ref LL_TIM_PWPRSC_X32
3436 * @arg @ref LL_TIM_PWPRSC_X64
3437 * @arg @ref LL_TIM_PWPRSC_X128
3438 * @retval None
3439 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3440 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3441 {
3442 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3443 }
3444
3445 /**
3446 * @brief Get the pulse on compare pulse width prescaler.
3447 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3448 * whether or not the pulse on compare feature is supported by the timer
3449 * instance.
3450 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3451 * @param TIMx Timer instance
3452 * @retval Returned value can be one of the following values:
3453 * @arg @ref LL_TIM_PWPRSC_X1
3454 * @arg @ref LL_TIM_PWPRSC_X2
3455 * @arg @ref LL_TIM_PWPRSC_X4
3456 * @arg @ref LL_TIM_PWPRSC_X8
3457 * @arg @ref LL_TIM_PWPRSC_X16
3458 * @arg @ref LL_TIM_PWPRSC_X32
3459 * @arg @ref LL_TIM_PWPRSC_X64
3460 * @arg @ref LL_TIM_PWPRSC_X128
3461 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3462 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3463 {
3464 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3465 }
3466
3467 /**
3468 * @brief Set the pulse on compare pulse width duration.
3469 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3470 * whether or not the pulse on compare feature is supported by the timer
3471 * instance.
3472 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3473 * @param TIMx Timer instance
3474 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3475 * @retval None
3476 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3477 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3478 {
3479 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3480 }
3481
3482 /**
3483 * @brief Get the pulse on compare pulse width duration.
3484 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3485 * whether or not the pulse on compare feature is supported by the timer
3486 * instance.
3487 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3488 * @param TIMx Timer instance
3489 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3490 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3491 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3492 {
3493 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3494 }
3495
3496 /**
3497 * @}
3498 */
3499
3500 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3501 * @{
3502 */
3503 /**
3504 * @brief Configure input channel.
3505 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3506 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3507 * CCMR1 IC1F LL_TIM_IC_Config\n
3508 * CCMR1 CC2S LL_TIM_IC_Config\n
3509 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3510 * CCMR1 IC2F LL_TIM_IC_Config\n
3511 * CCMR2 CC3S LL_TIM_IC_Config\n
3512 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3513 * CCMR2 IC3F LL_TIM_IC_Config\n
3514 * CCMR2 CC4S LL_TIM_IC_Config\n
3515 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3516 * CCMR2 IC4F LL_TIM_IC_Config\n
3517 * CCER CC1P LL_TIM_IC_Config\n
3518 * CCER CC1NP LL_TIM_IC_Config\n
3519 * CCER CC2P LL_TIM_IC_Config\n
3520 * CCER CC2NP LL_TIM_IC_Config\n
3521 * CCER CC3P LL_TIM_IC_Config\n
3522 * CCER CC3NP LL_TIM_IC_Config\n
3523 * CCER CC4P LL_TIM_IC_Config\n
3524 * CCER CC4NP LL_TIM_IC_Config
3525 * @param TIMx Timer instance
3526 * @param Channel This parameter can be one of the following values:
3527 * @arg @ref LL_TIM_CHANNEL_CH1
3528 * @arg @ref LL_TIM_CHANNEL_CH2
3529 * @arg @ref LL_TIM_CHANNEL_CH3
3530 * @arg @ref LL_TIM_CHANNEL_CH4
3531 * @param Configuration This parameter must be a combination of all the following values:
3532 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3533 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3534 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3535 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3536 * @retval None
3537 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3538 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3539 {
3540 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3541 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3542 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3543 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3544 << SHIFT_TAB_ICxx[iChannel]);
3545 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3546 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3547 }
3548
3549 /**
3550 * @brief Set the active input.
3551 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3552 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3553 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3554 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3555 * @param TIMx Timer instance
3556 * @param Channel This parameter can be one of the following values:
3557 * @arg @ref LL_TIM_CHANNEL_CH1
3558 * @arg @ref LL_TIM_CHANNEL_CH2
3559 * @arg @ref LL_TIM_CHANNEL_CH3
3560 * @arg @ref LL_TIM_CHANNEL_CH4
3561 * @param ICActiveInput This parameter can be one of the following values:
3562 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3563 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3564 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3565 * @retval None
3566 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3567 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3568 {
3569 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3570 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3571 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3572 }
3573
3574 /**
3575 * @brief Get the current active input.
3576 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3577 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3578 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3579 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3580 * @param TIMx Timer instance
3581 * @param Channel This parameter can be one of the following values:
3582 * @arg @ref LL_TIM_CHANNEL_CH1
3583 * @arg @ref LL_TIM_CHANNEL_CH2
3584 * @arg @ref LL_TIM_CHANNEL_CH3
3585 * @arg @ref LL_TIM_CHANNEL_CH4
3586 * @retval Returned value can be one of the following values:
3587 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3588 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3589 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3590 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3591 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3592 {
3593 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3594 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3595 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3596 }
3597
3598 /**
3599 * @brief Set the prescaler of input channel.
3600 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3601 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3602 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3603 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3604 * @param TIMx Timer instance
3605 * @param Channel This parameter can be one of the following values:
3606 * @arg @ref LL_TIM_CHANNEL_CH1
3607 * @arg @ref LL_TIM_CHANNEL_CH2
3608 * @arg @ref LL_TIM_CHANNEL_CH3
3609 * @arg @ref LL_TIM_CHANNEL_CH4
3610 * @param ICPrescaler This parameter can be one of the following values:
3611 * @arg @ref LL_TIM_ICPSC_DIV1
3612 * @arg @ref LL_TIM_ICPSC_DIV2
3613 * @arg @ref LL_TIM_ICPSC_DIV4
3614 * @arg @ref LL_TIM_ICPSC_DIV8
3615 * @retval None
3616 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3617 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3618 {
3619 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3620 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3621 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3622 }
3623
3624 /**
3625 * @brief Get the current prescaler value acting on an input channel.
3626 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3627 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3628 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3629 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3630 * @param TIMx Timer instance
3631 * @param Channel This parameter can be one of the following values:
3632 * @arg @ref LL_TIM_CHANNEL_CH1
3633 * @arg @ref LL_TIM_CHANNEL_CH2
3634 * @arg @ref LL_TIM_CHANNEL_CH3
3635 * @arg @ref LL_TIM_CHANNEL_CH4
3636 * @retval Returned value can be one of the following values:
3637 * @arg @ref LL_TIM_ICPSC_DIV1
3638 * @arg @ref LL_TIM_ICPSC_DIV2
3639 * @arg @ref LL_TIM_ICPSC_DIV4
3640 * @arg @ref LL_TIM_ICPSC_DIV8
3641 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3642 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3643 {
3644 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3645 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3646 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3647 }
3648
3649 /**
3650 * @brief Set the input filter duration.
3651 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3652 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3653 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3654 * CCMR2 IC4F LL_TIM_IC_SetFilter
3655 * @param TIMx Timer instance
3656 * @param Channel This parameter can be one of the following values:
3657 * @arg @ref LL_TIM_CHANNEL_CH1
3658 * @arg @ref LL_TIM_CHANNEL_CH2
3659 * @arg @ref LL_TIM_CHANNEL_CH3
3660 * @arg @ref LL_TIM_CHANNEL_CH4
3661 * @param ICFilter This parameter can be one of the following values:
3662 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3663 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3664 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3665 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3666 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3667 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3668 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3669 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3670 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3671 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3672 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3673 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3674 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3675 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3676 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3677 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3678 * @retval None
3679 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3680 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3681 {
3682 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3683 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3684 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3685 }
3686
3687 /**
3688 * @brief Get the input filter duration.
3689 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3690 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3691 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3692 * CCMR2 IC4F LL_TIM_IC_GetFilter
3693 * @param TIMx Timer instance
3694 * @param Channel This parameter can be one of the following values:
3695 * @arg @ref LL_TIM_CHANNEL_CH1
3696 * @arg @ref LL_TIM_CHANNEL_CH2
3697 * @arg @ref LL_TIM_CHANNEL_CH3
3698 * @arg @ref LL_TIM_CHANNEL_CH4
3699 * @retval Returned value can be one of the following values:
3700 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3701 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3702 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3703 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3704 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3705 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3706 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3707 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3708 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3709 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3710 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3711 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3712 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3713 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3714 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3715 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3716 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3717 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3718 {
3719 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3720 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3721 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3722 }
3723
3724 /**
3725 * @brief Set the input channel polarity.
3726 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3727 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3728 * CCER CC2P LL_TIM_IC_SetPolarity\n
3729 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3730 * CCER CC3P LL_TIM_IC_SetPolarity\n
3731 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3732 * CCER CC4P LL_TIM_IC_SetPolarity\n
3733 * CCER CC4NP LL_TIM_IC_SetPolarity
3734 * @param TIMx Timer instance
3735 * @param Channel This parameter can be one of the following values:
3736 * @arg @ref LL_TIM_CHANNEL_CH1
3737 * @arg @ref LL_TIM_CHANNEL_CH2
3738 * @arg @ref LL_TIM_CHANNEL_CH3
3739 * @arg @ref LL_TIM_CHANNEL_CH4
3740 * @param ICPolarity This parameter can be one of the following values:
3741 * @arg @ref LL_TIM_IC_POLARITY_RISING
3742 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3743 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3744 * @retval None
3745 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3746 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3747 {
3748 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3749 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3750 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3751 }
3752
3753 /**
3754 * @brief Get the current input channel polarity.
3755 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3756 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3757 * CCER CC2P LL_TIM_IC_GetPolarity\n
3758 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3759 * CCER CC3P LL_TIM_IC_GetPolarity\n
3760 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3761 * CCER CC4P LL_TIM_IC_GetPolarity\n
3762 * CCER CC4NP LL_TIM_IC_GetPolarity
3763 * @param TIMx Timer instance
3764 * @param Channel This parameter can be one of the following values:
3765 * @arg @ref LL_TIM_CHANNEL_CH1
3766 * @arg @ref LL_TIM_CHANNEL_CH2
3767 * @arg @ref LL_TIM_CHANNEL_CH3
3768 * @arg @ref LL_TIM_CHANNEL_CH4
3769 * @retval Returned value can be one of the following values:
3770 * @arg @ref LL_TIM_IC_POLARITY_RISING
3771 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3772 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3773 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3774 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3775 {
3776 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3777 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3778 SHIFT_TAB_CCxP[iChannel]);
3779 }
3780
3781 /**
3782 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3783 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3784 * a timer instance provides an XOR input.
3785 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3786 * @param TIMx Timer instance
3787 * @retval None
3788 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3789 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3790 {
3791 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3792 }
3793
3794 /**
3795 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3796 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3797 * a timer instance provides an XOR input.
3798 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3799 * @param TIMx Timer instance
3800 * @retval None
3801 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3802 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3803 {
3804 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3805 }
3806
3807 /**
3808 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3809 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3810 * a timer instance provides an XOR input.
3811 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3812 * @param TIMx Timer instance
3813 * @retval State of bit (1 or 0).
3814 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3815 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3816 {
3817 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3818 }
3819
3820 /**
3821 * @brief Get captured value for input channel 1.
3822 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3823 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3824 * whether or not a timer instance supports a 32 bits counter.
3825 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3826 * input channel 1 is supported by a timer instance.
3827 * @note If dithering is activated, pay attention to the returned value interpretation.
3828 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3829 * @param TIMx Timer instance
3830 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3831 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3832 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3833 {
3834 return (uint32_t)(READ_REG(TIMx->CCR1));
3835 }
3836
3837 /**
3838 * @brief Get captured value for input channel 2.
3839 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3840 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3841 * whether or not a timer instance supports a 32 bits counter.
3842 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3843 * input channel 2 is supported by a timer instance.
3844 * @note If dithering is activated, pay attention to the returned value interpretation.
3845 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3846 * @param TIMx Timer instance
3847 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3848 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3849 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3850 {
3851 return (uint32_t)(READ_REG(TIMx->CCR2));
3852 }
3853
3854 /**
3855 * @brief Get captured value for input channel 3.
3856 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3857 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3858 * whether or not a timer instance supports a 32 bits counter.
3859 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3860 * input channel 3 is supported by a timer instance.
3861 * @note If dithering is activated, pay attention to the returned value interpretation.
3862 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3863 * @param TIMx Timer instance
3864 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3865 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3866 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3867 {
3868 return (uint32_t)(READ_REG(TIMx->CCR3));
3869 }
3870
3871 /**
3872 * @brief Get captured value for input channel 4.
3873 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3874 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3875 * whether or not a timer instance supports a 32 bits counter.
3876 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3877 * input channel 4 is supported by a timer instance.
3878 * @note If dithering is activated, pay attention to the returned value interpretation.
3879 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3880 * @param TIMx Timer instance
3881 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3882 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3883 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3884 {
3885 return (uint32_t)(READ_REG(TIMx->CCR4));
3886 }
3887
3888 /**
3889 * @}
3890 */
3891
3892 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3893 * @{
3894 */
3895 /**
3896 * @brief Enable external clock mode 2.
3897 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3898 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3899 * whether or not a timer instance supports external clock mode2.
3900 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3901 * @param TIMx Timer instance
3902 * @retval None
3903 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3904 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3905 {
3906 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3907 }
3908
3909 /**
3910 * @brief Disable external clock mode 2.
3911 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3912 * whether or not a timer instance supports external clock mode2.
3913 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3914 * @param TIMx Timer instance
3915 * @retval None
3916 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3917 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3918 {
3919 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3920 }
3921
3922 /**
3923 * @brief Indicate whether external clock mode 2 is enabled.
3924 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3925 * whether or not a timer instance supports external clock mode2.
3926 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3927 * @param TIMx Timer instance
3928 * @retval State of bit (1 or 0).
3929 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3930 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3931 {
3932 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3933 }
3934
3935 /**
3936 * @brief Set the clock source of the counter clock.
3937 * @note when selected clock source is external clock mode 1, the timer input
3938 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3939 * function. This timer input must be configured by calling
3940 * the @ref LL_TIM_IC_Config() function.
3941 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3942 * whether or not a timer instance supports external clock mode1.
3943 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3944 * whether or not a timer instance supports external clock mode2.
3945 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3946 * SMCR ECE LL_TIM_SetClockSource
3947 * @param TIMx Timer instance
3948 * @param ClockSource This parameter can be one of the following values:
3949 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3950 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3951 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3952 * @retval None
3953 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3954 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3955 {
3956 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3957 }
3958
3959 /**
3960 * @brief Set the encoder interface mode.
3961 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3962 * whether or not a timer instance supports the encoder mode.
3963 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3964 * @param TIMx Timer instance
3965 * @param EncoderMode This parameter can be one of the following values:
3966 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3967 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3968 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3969 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3970 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3971 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3972 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3973 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3974 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3975 * @retval None
3976 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3977 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3978 {
3979 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3980 }
3981
3982 /**
3983 * @}
3984 */
3985
3986 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3987 * @{
3988 */
3989 /**
3990 * @brief Set the trigger output (TRGO) used for timer synchronization .
3991 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3992 * whether or not a timer instance can operate as a master timer.
3993 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3994 * @param TIMx Timer instance
3995 * @param TimerSynchronization This parameter can be one of the following values:
3996 * @arg @ref LL_TIM_TRGO_RESET
3997 * @arg @ref LL_TIM_TRGO_ENABLE
3998 * @arg @ref LL_TIM_TRGO_UPDATE
3999 * @arg @ref LL_TIM_TRGO_CC1IF
4000 * @arg @ref LL_TIM_TRGO_OC1REF
4001 * @arg @ref LL_TIM_TRGO_OC2REF
4002 * @arg @ref LL_TIM_TRGO_OC3REF
4003 * @arg @ref LL_TIM_TRGO_OC4REF
4004 * @arg @ref LL_TIM_TRGO_ENCODERCLK
4005 * @retval None
4006 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)4007 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
4008 {
4009 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
4010 }
4011
4012 /**
4013 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
4014 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
4015 * whether or not a timer instance can be used for ADC synchronization.
4016 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
4017 * @param TIMx Timer Instance
4018 * @param ADCSynchronization This parameter can be one of the following values:
4019 * @arg @ref LL_TIM_TRGO2_RESET
4020 * @arg @ref LL_TIM_TRGO2_ENABLE
4021 * @arg @ref LL_TIM_TRGO2_UPDATE
4022 * @arg @ref LL_TIM_TRGO2_CC1F
4023 * @arg @ref LL_TIM_TRGO2_OC1
4024 * @arg @ref LL_TIM_TRGO2_OC2
4025 * @arg @ref LL_TIM_TRGO2_OC3
4026 * @arg @ref LL_TIM_TRGO2_OC4
4027 * @arg @ref LL_TIM_TRGO2_OC5
4028 * @arg @ref LL_TIM_TRGO2_OC6
4029 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
4030 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
4031 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
4032 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
4033 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
4034 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
4035 * @retval None
4036 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)4037 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
4038 {
4039 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
4040 }
4041
4042 /**
4043 * @brief Set the synchronization mode of a slave timer.
4044 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4045 * a timer instance can operate as a slave timer.
4046 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
4047 * @param TIMx Timer instance
4048 * @param SlaveMode This parameter can be one of the following values:
4049 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
4050 * @arg @ref LL_TIM_SLAVEMODE_RESET
4051 * @arg @ref LL_TIM_SLAVEMODE_GATED
4052 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
4053 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
4054 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
4055 * @retval None
4056 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)4057 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
4058 {
4059 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
4060 }
4061
4062 /**
4063 * @brief Set the selects the trigger input to be used to synchronize the counter.
4064 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4065 * a timer instance can operate as a slave timer.
4066 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
4067 * @param TIMx Timer instance
4068 * @param TriggerInput This parameter can be one of the following values:
4069 * @arg @ref LL_TIM_TS_ITR0
4070 * @arg @ref LL_TIM_TS_ITR1
4071 * @arg @ref LL_TIM_TS_ITR2
4072 * @arg @ref LL_TIM_TS_ITR3
4073 * @arg @ref LL_TIM_TS_ITR4
4074 * @arg @ref LL_TIM_TS_ITR5
4075 * @arg @ref LL_TIM_TS_ITR6
4076 * @arg @ref LL_TIM_TS_ITR7
4077 * @arg @ref LL_TIM_TS_ITR8
4078 * @arg @ref LL_TIM_TS_ITR9
4079 * @arg @ref LL_TIM_TS_ITR10
4080 * @arg @ref LL_TIM_TS_ITR11
4081 * @arg @ref LL_TIM_TS_TI1F_ED
4082 * @arg @ref LL_TIM_TS_TI1FP1
4083 * @arg @ref LL_TIM_TS_TI2FP2
4084 * @arg @ref LL_TIM_TS_ETRF
4085 * @retval None
4086 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)4087 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
4088 {
4089 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
4090 }
4091
4092 /**
4093 * @brief Enable the Master/Slave mode.
4094 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4095 * a timer instance can operate as a slave timer.
4096 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
4097 * @param TIMx Timer instance
4098 * @retval None
4099 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)4100 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
4101 {
4102 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4103 }
4104
4105 /**
4106 * @brief Disable the Master/Slave mode.
4107 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4108 * a timer instance can operate as a slave timer.
4109 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
4110 * @param TIMx Timer instance
4111 * @retval None
4112 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)4113 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
4114 {
4115 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4116 }
4117
4118 /**
4119 * @brief Indicates whether the Master/Slave mode is enabled.
4120 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4121 * a timer instance can operate as a slave timer.
4122 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
4123 * @param TIMx Timer instance
4124 * @retval State of bit (1 or 0).
4125 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)4126 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
4127 {
4128 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
4129 }
4130
4131 /**
4132 * @brief Configure the external trigger (ETR) input.
4133 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
4134 * a timer instance provides an external trigger input.
4135 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
4136 * SMCR ETPS LL_TIM_ConfigETR\n
4137 * SMCR ETF LL_TIM_ConfigETR
4138 * @param TIMx Timer instance
4139 * @param ETRPolarity This parameter can be one of the following values:
4140 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
4141 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
4142 * @param ETRPrescaler This parameter can be one of the following values:
4143 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
4144 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
4145 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
4146 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
4147 * @param ETRFilter This parameter can be one of the following values:
4148 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
4149 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
4150 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
4151 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
4152 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
4153 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
4154 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
4155 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
4156 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
4157 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
4158 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
4159 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
4160 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
4161 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
4162 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
4163 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
4164 * @retval None
4165 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)4166 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
4167 uint32_t ETRFilter)
4168 {
4169 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
4170 }
4171
4172 /**
4173 * @brief Select the external trigger (ETR) input source.
4174 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
4175 * not a timer instance supports ETR source selection.
4176 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
4177 * @param TIMx Timer instance
4178 * @param ETRSource This parameter can be one of the following values:
4179 *
4180 * TIM1: any combination of ETR_RMP where
4181 *
4182 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
4183 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
4184 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
4185 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
4186 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
4187 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
4188 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
4189 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
4190 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
4191 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
4192 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
4193 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
4194 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
4195 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)
4196 *
4197 * TIM2: any combination of ETR_RMP where
4198 *
4199 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
4200 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
4201 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
4202 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
4203 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
4204 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
4205 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
4206 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
4207 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
4208 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
4209 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
4210 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
4211 *
4212 * TIM3: any combination of ETR_RMP where
4213 *
4214 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
4215 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
4216 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
4217 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
4218 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
4219 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
4220 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
4221 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
4222 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
4223 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
4224 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
4225 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
4226 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
4227 *
4228 * TIM4: any combination of ETR_RMP where
4229 *
4230 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
4231 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
4232 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
4233 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
4234 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
4235 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
4236 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
4237 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
4238 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
4239 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)
4240 *
4241 * TIM5: any combination of ETR_RMP where (**)
4242 *
4243 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*)
4244 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
4245 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
4246 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
4247 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
4248 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
4249 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
4250 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
4251 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
4252 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)
4253 *
4254 * TIM8: any combination of ETR_RMP where
4255 *
4256 * . . ETR_RMP can be one of the following values
4257 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
4258 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
4259 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
4260 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
4261 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
4262 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
4263 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
4264 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
4265 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
4266 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
4267 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
4268 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
4269 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
4270 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
4271 *
4272 * TIM20: any combination of ETR_RMP where (**)
4273 *
4274 * . . ETR_RMP can be one of the following values
4275 * @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*)
4276 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
4277 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
4278 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
4279 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
4280 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
4281 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
4282 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
4283 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
4284 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
4285 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
4286 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
4287 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
4288 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)
4289 *
4290 * (*) Value not defined in all devices. \n
4291 * (**) Register not available in all devices.
4292 * @retval None
4293 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)4294 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
4295 {
4296 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
4297 }
4298
4299 /**
4300 * @brief Enable SMS preload.
4301 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4302 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4303 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
4304 * @param TIMx Timer instance
4305 * @retval None
4306 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)4307 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
4308 {
4309 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4310 }
4311
4312 /**
4313 * @brief Disable SMS preload.
4314 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4315 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4316 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
4317 * @param TIMx Timer instance
4318 * @retval None
4319 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)4320 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
4321 {
4322 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4323 }
4324
4325 /**
4326 * @brief Indicate whether SMS preload is enabled.
4327 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4328 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4329 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
4330 * @param TIMx Timer instance
4331 * @retval State of bit (1 or 0).
4332 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)4333 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
4334 {
4335 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4336 }
4337
4338 /**
4339 * @brief Set the preload source of SMS.
4340 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4341 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4342 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4343 * @param TIMx Timer instance
4344 * @param PreloadSource This parameter can be one of the following values:
4345 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4346 * @arg @ref LL_TIM_SMSPS_INDEX
4347 * @retval None
4348 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4349 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4350 {
4351 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4352 }
4353
4354 /**
4355 * @brief Get the preload source of SMS.
4356 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4357 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4358 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4359 * @param TIMx Timer instance
4360 * @retval Returned value can be one of the following values:
4361 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4362 * @arg @ref LL_TIM_SMSPS_INDEX
4363 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)4364 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
4365 {
4366 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4367 }
4368
4369 /**
4370 * @}
4371 */
4372
4373 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4374 * @{
4375 */
4376 /**
4377 * @brief Enable the break function.
4378 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4379 * a timer instance provides a break input.
4380 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4381 * @param TIMx Timer instance
4382 * @retval None
4383 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4384 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4385 {
4386 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4387 }
4388
4389 /**
4390 * @brief Disable the break function.
4391 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4392 * @param TIMx Timer instance
4393 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4394 * a timer instance provides a break input.
4395 * @retval None
4396 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4397 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4398 {
4399 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4400 }
4401
4402 /**
4403 * @brief Configure the break input.
4404 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4405 * a timer instance provides a break input.
4406 * @note Bidirectional mode is only supported by advanced timer instances.
4407 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4408 * a timer instance is an advanced-control timer.
4409 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4410 * in input mode and in open drain output mode. Any active Break event will
4411 * assert a low logic level on the Break input to indicate an internal break
4412 * event to external devices.
4413 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4414 * LL_TIM_BREAK_AFMODE_INPUT.
4415 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4416 * BDTR BKF LL_TIM_ConfigBRK\n
4417 * BDTR BKBID LL_TIM_ConfigBRK
4418 * @param TIMx Timer instance
4419 * @param BreakPolarity This parameter can be one of the following values:
4420 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4421 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4422 * @param BreakFilter This parameter can be one of the following values:
4423 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4424 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4425 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4426 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4427 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4428 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4429 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4430 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4431 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4432 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4433 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4434 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4435 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4436 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4437 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4438 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4439 * @param BreakAFMode This parameter can be one of the following values:
4440 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4441 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4442 * @retval None
4443 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4444 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4445 uint32_t BreakAFMode)
4446 {
4447 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4448 }
4449
4450 /**
4451 * @brief Disarm the break input (when it operates in bidirectional mode).
4452 * @note The break input can be disarmed only when it is configured in
4453 * bidirectional mode and when when MOE is reset.
4454 * @note Purpose is to be able to have the input voltage back to high-state,
4455 * whatever the time constant on the output .
4456 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4457 * @param TIMx Timer instance
4458 * @retval None
4459 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4460 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4461 {
4462 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4463 }
4464
4465 /**
4466 * @brief Enable the break 2 function.
4467 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4468 * a timer instance provides a second break input.
4469 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4470 * @param TIMx Timer instance
4471 * @retval None
4472 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4473 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4474 {
4475 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4476 }
4477
4478 /**
4479 * @brief Disable the break 2 function.
4480 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4481 * a timer instance provides a second break input.
4482 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4483 * @param TIMx Timer instance
4484 * @retval None
4485 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4486 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4487 {
4488 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4489 }
4490
4491 /**
4492 * @brief Configure the break 2 input.
4493 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4494 * a timer instance provides a second break input.
4495 * @note Bidirectional mode is only supported by advanced timer instances.
4496 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4497 * a timer instance is an advanced-control timer.
4498 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4499 * in input mode and in open drain output mode. Any active Break event will
4500 * assert a low logic level on the Break 2 input to indicate an internal break
4501 * event to external devices.
4502 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4503 * LL_TIM_BREAK2_AFMODE_INPUT.
4504 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4505 * BDTR BK2F LL_TIM_ConfigBRK2\n
4506 * BDTR BK2BID LL_TIM_ConfigBRK2
4507 * @param TIMx Timer instance
4508 * @param Break2Polarity This parameter can be one of the following values:
4509 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4510 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4511 * @param Break2Filter This parameter can be one of the following values:
4512 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4513 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4514 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4515 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4516 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4517 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4518 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4519 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4520 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4521 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4522 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4523 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4524 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4525 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4526 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4527 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4528 * @param Break2AFMode This parameter can be one of the following values:
4529 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4530 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4531 * @retval None
4532 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4533 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4534 uint32_t Break2AFMode)
4535 {
4536 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4537 }
4538
4539 /**
4540 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4541 * @note The break 2 input can be disarmed only when it is configured in
4542 * bidirectional mode and when when MOE is reset.
4543 * @note Purpose is to be able to have the input voltage back to high-state,
4544 * whatever the time constant on the output.
4545 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4546 * @param TIMx Timer instance
4547 * @retval None
4548 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4549 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4550 {
4551 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4552 }
4553
4554 /**
4555 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4556 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4557 * a timer instance provides a break input.
4558 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4559 * BDTR OSSR LL_TIM_SetOffStates
4560 * @param TIMx Timer instance
4561 * @param OffStateIdle This parameter can be one of the following values:
4562 * @arg @ref LL_TIM_OSSI_DISABLE
4563 * @arg @ref LL_TIM_OSSI_ENABLE
4564 * @param OffStateRun This parameter can be one of the following values:
4565 * @arg @ref LL_TIM_OSSR_DISABLE
4566 * @arg @ref LL_TIM_OSSR_ENABLE
4567 * @retval None
4568 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4569 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4570 {
4571 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4572 }
4573
4574 /**
4575 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4576 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4577 * a timer instance provides a break input.
4578 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4579 * @param TIMx Timer instance
4580 * @retval None
4581 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4582 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4583 {
4584 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4585 }
4586
4587 /**
4588 * @brief Disable automatic output (MOE can be set only by software).
4589 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4590 * a timer instance provides a break input.
4591 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4592 * @param TIMx Timer instance
4593 * @retval None
4594 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4595 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4596 {
4597 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4598 }
4599
4600 /**
4601 * @brief Indicate whether automatic output is enabled.
4602 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4603 * a timer instance provides a break input.
4604 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4605 * @param TIMx Timer instance
4606 * @retval State of bit (1 or 0).
4607 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4608 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4609 {
4610 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4611 }
4612
4613 /**
4614 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4615 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4616 * software and is reset in case of break or break2 event
4617 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4618 * a timer instance provides a break input.
4619 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4620 * @param TIMx Timer instance
4621 * @retval None
4622 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4623 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4624 {
4625 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4626 }
4627
4628 /**
4629 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4630 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4631 * software and is reset in case of break or break2 event.
4632 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4633 * a timer instance provides a break input.
4634 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4635 * @param TIMx Timer instance
4636 * @retval None
4637 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4638 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4639 {
4640 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4641 }
4642
4643 /**
4644 * @brief Indicates whether outputs are enabled.
4645 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4646 * a timer instance provides a break input.
4647 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4648 * @param TIMx Timer instance
4649 * @retval State of bit (1 or 0).
4650 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4651 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4652 {
4653 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4654 }
4655
4656 /**
4657 * @brief Enable the signals connected to the designated timer break input.
4658 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4659 * or not a timer instance allows for break input selection.
4660 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4661 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4662 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4663 * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
4664 * AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n
4665 * AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n
4666 * AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n
4667 * AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n
4668 * AF2 BK2NE LL_TIM_EnableBreakInputSource\n
4669 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4670 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4671 * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
4672 * AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n
4673 * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n
4674 * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n
4675 * AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
4676 * @param TIMx Timer instance
4677 * @param BreakInput This parameter can be one of the following values:
4678 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4679 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4680 * @param Source This parameter can be one of the following values:
4681 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4682 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4683 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4684 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4685 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4686 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4687 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4688 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4689 *
4690 * (*) Value not defined in all devices.
4691 * @retval None
4692 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4693 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4694 {
4695 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4696 SET_BIT(*pReg, Source);
4697 }
4698
4699 /**
4700 * @brief Disable the signals connected to the designated timer break input.
4701 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4702 * or not a timer instance allows for break input selection.
4703 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4704 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4705 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4706 * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
4707 * AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n
4708 * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n
4709 * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n
4710 * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n
4711 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4712 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4713 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n
4714 * AF2 BK2CMP3E LL_TIM_DisableBreakInputSource\n
4715 * AF2 BK2CMP4E LL_TIM_DisableBreakInputSource\n
4716 * AF2 BK2CMP5E LL_TIM_DisableBreakInputSource\n
4717 * AF2 BK2CMP6E LL_TIM_DisableBreakInputSource\n
4718 * AF2 BK2CMP7E LL_TIM_DisableBreakInputSource
4719 * @param TIMx Timer instance
4720 * @param BreakInput This parameter can be one of the following values:
4721 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4722 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4723 * @param Source This parameter can be one of the following values:
4724 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4725 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4726 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4727 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4728 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4729 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4730 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4731 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4732 *
4733 * (*) Value not defined in all devices.
4734 * @retval None
4735 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4736 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4737 {
4738 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4739 CLEAR_BIT(*pReg, Source);
4740 }
4741
4742 /**
4743 * @brief Set the polarity of the break signal for the timer break input.
4744 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4745 * or not a timer instance allows for break input selection.
4746 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4747 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4748 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4749 * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
4750 * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n
4751 * AF1 BKCMP5P LL_TIM_SetBreakInputSourcePolarity\n
4752 * AF1 BKCMP6P LL_TIM_SetBreakInputSourcePolarity\n
4753 * AF1 BKCMP7P LL_TIM_SetBreakInputSourcePolarity\n
4754 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4755 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4756 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
4757 * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n
4758 * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity\n
4759 * AF2 BK2CMP5P LL_TIM_SetBreakInputSourcePolarity\n
4760 * AF2 BK2CMP6P LL_TIM_SetBreakInputSourcePolarity\n
4761 * AF2 BK2CMP7P LL_TIM_SetBreakInputSourcePolarity
4762 * @param TIMx Timer instance
4763 * @param BreakInput This parameter can be one of the following values:
4764 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4765 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4766 * @param Source This parameter can be one of the following values:
4767 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4768 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4769 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4770 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4771 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4772 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4773 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4774 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4775 * @param Polarity This parameter can be one of the following values:
4776 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4777 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4778 *
4779 * (*) Value not defined in all devices.
4780 * @retval None
4781 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4782 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4783 uint32_t Polarity)
4784 {
4785 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4786 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4787 }
4788 /**
4789 * @brief Enable asymmetrical deadtime.
4790 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4791 * a timer instance provides asymmetrical deadtime.
4792 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4793 * @param TIMx Timer instance
4794 * @retval None
4795 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4796 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4797 {
4798 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4799 }
4800
4801 /**
4802 * @brief Disable asymmetrical dead-time.
4803 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4804 * a timer instance provides asymmetrical deadtime.
4805 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4806 * @param TIMx Timer instance
4807 * @retval None
4808 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4809 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4810 {
4811 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4812 }
4813
4814 /**
4815 * @brief Indicates whether asymmetrical deadtime is activated.
4816 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4817 * a timer instance provides asymmetrical deadtime.
4818 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4819 * @param TIMx Timer instance
4820 * @retval State of bit (1 or 0).
4821 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4822 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4823 {
4824 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4825 }
4826
4827 /**
4828 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4829 * rising edge of OCxN signals).
4830 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4831 * asymmetrical dead-time insertion feature is supported by a timer instance.
4832 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4833 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4834 * (LOCK bits in TIMx_BDTR register).
4835 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4836 * @param TIMx Timer instance
4837 * @param DeadTime between Min_Data=0 and Max_Data=255
4838 * @retval None
4839 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4840 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4841 {
4842 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4843 }
4844
4845 /**
4846 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4847 * the rising edge of OCxN signals).
4848 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4849 * asymmetrical dead-time insertion feature is supported by a timer instance.
4850 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4851 * (LOCK bits in TIMx_BDTR register).
4852 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4853 * @param TIMx Timer instance
4854 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4855 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4856 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4857 {
4858 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4859 }
4860
4861 /**
4862 * @brief Enable deadtime preload.
4863 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4864 * a timer instance provides deadtime preload.
4865 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4866 * @param TIMx Timer instance
4867 * @retval None
4868 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4869 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4870 {
4871 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4872 }
4873
4874 /**
4875 * @brief Disable dead-time preload.
4876 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4877 * a timer instance provides deadtime preload.
4878 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4879 * @param TIMx Timer instance
4880 * @retval None
4881 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4882 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4883 {
4884 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4885 }
4886
4887 /**
4888 * @brief Indicates whether deadtime preload is activated.
4889 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4890 * a timer instance provides deadtime preload.
4891 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4892 * @param TIMx Timer instance
4893 * @retval State of bit (1 or 0).
4894 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4895 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4896 {
4897 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4898 }
4899
4900 /**
4901 * @}
4902 */
4903
4904 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4905 * @{
4906 */
4907 /**
4908 * @brief Configures the timer DMA burst feature.
4909 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4910 * not a timer instance supports the DMA burst mode.
4911 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4912 * DCR DBA LL_TIM_ConfigDMABurst
4913 * @param TIMx Timer instance
4914 * @param DMABurstBaseAddress This parameter can be one of the following values:
4915 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4916 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4917 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4918 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4919 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4920 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4921 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4922 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4923 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4924 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4925 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4926 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4927 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4928 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4929 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4930 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4931 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4932 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4933 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4934 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4935 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4936 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4937 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4938 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4939 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4940 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4941 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
4942 * @param DMABurstLength This parameter can be one of the following values:
4943 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4944 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4945 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4946 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4947 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4948 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4949 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4950 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4951 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4952 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4953 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4954 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4955 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4956 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4957 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4958 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4959 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4960 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4961 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4962 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4963 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4964 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4965 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4966 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4967 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4968 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4969 * @retval None
4970 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)4971 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
4972 {
4973 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
4974 }
4975
4976 /**
4977 * @}
4978 */
4979
4980 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4981 * @{
4982 */
4983
4984 /**
4985 * @brief Enable encoder index.
4986 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4987 * a timer instance provides an index input.
4988 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4989 * @param TIMx Timer instance
4990 * @retval None
4991 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4992 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4993 {
4994 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4995 }
4996
4997 /**
4998 * @brief Disable encoder index.
4999 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5000 * a timer instance provides an index input.
5001 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
5002 * @param TIMx Timer instance
5003 * @retval None
5004 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)5005 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
5006 {
5007 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
5008 }
5009
5010 /**
5011 * @brief Indicate whether encoder index is enabled.
5012 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5013 * a timer instance provides an index input.
5014 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
5015 * @param TIMx Timer instance
5016 * @retval State of bit (1 or 0).
5017 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)5018 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
5019 {
5020 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
5021 }
5022
5023 /**
5024 * @brief Set index direction
5025 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5026 * a timer instance provides an index input.
5027 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
5028 * @param TIMx Timer instance
5029 * @param IndexDirection This parameter can be one of the following values:
5030 * @arg @ref LL_TIM_INDEX_UP_DOWN
5031 * @arg @ref LL_TIM_INDEX_UP
5032 * @arg @ref LL_TIM_INDEX_DOWN
5033 * @retval None
5034 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)5035 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
5036 {
5037 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
5038 }
5039
5040 /**
5041 * @brief Get actual index direction
5042 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5043 * a timer instance provides an index input.
5044 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
5045 * @param TIMx Timer instance
5046 * @retval Returned value can be one of the following values:
5047 * @arg @ref LL_TIM_INDEX_UP_DOWN
5048 * @arg @ref LL_TIM_INDEX_UP
5049 * @arg @ref LL_TIM_INDEX_DOWN
5050 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)5051 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
5052 {
5053 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
5054 }
5055
5056 /**
5057 * @brief Enable first index.
5058 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5059 * a timer instance provides an index input.
5060 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
5061 * @param TIMx Timer instance
5062 * @retval None
5063 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)5064 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
5065 {
5066 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
5067 }
5068
5069 /**
5070 * @brief Disable first index.
5071 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5072 * a timer instance provides an index input.
5073 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
5074 * @param TIMx Timer instance
5075 * @retval None
5076 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)5077 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
5078 {
5079 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
5080 }
5081
5082 /**
5083 * @brief Indicates whether first index is enabled.
5084 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5085 * a timer instance provides an index input.
5086 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
5087 * @param TIMx Timer instance
5088 * @retval State of bit (1 or 0).
5089 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)5090 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
5091 {
5092 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
5093 }
5094
5095 /**
5096 * @brief Set index positioning
5097 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5098 * a timer instance provides an index input.
5099 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
5100 * @param TIMx Timer instance
5101 * @param IndexPositionning This parameter can be one of the following values:
5102 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5103 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5104 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5105 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5106 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5107 * @arg @ref LL_TIM_INDEX_POSITION_UP
5108 * @retval None
5109 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)5110 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
5111 {
5112 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
5113 }
5114
5115 /**
5116 * @brief Get actual index positioning
5117 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5118 * a timer instance provides an index input.
5119 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
5120 * @param TIMx Timer instance
5121 * @retval Returned value can be one of the following values:
5122 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5123 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5124 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5125 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5126 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5127 * @arg @ref LL_TIM_INDEX_POSITION_UP
5128 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)5129 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
5130 {
5131 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
5132 }
5133
5134 /**
5135 * @brief Configure encoder index.
5136 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5137 * a timer instance provides an index input.
5138 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
5139 * ECR FIDX LL_TIM_ConfigIDX\n
5140 * ECR IPOS LL_TIM_ConfigIDX
5141 * @param TIMx Timer instance
5142 * @param Configuration This parameter must be a combination of all the following values:
5143 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
5144 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
5145 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
5146 * @retval None
5147 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)5148 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
5149 {
5150 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
5151 }
5152
5153 /**
5154 * @}
5155 */
5156
5157 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
5158 * @{
5159 */
5160 /**
5161 * @brief Remap TIM inputs (input channel, internal/external triggers).
5162 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
5163 * a some timer inputs can be remapped.
5164 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
5165 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
5166 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
5167 * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
5168 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
5169 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
5170 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
5171 * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
5172 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
5173 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
5174 * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
5175 * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
5176 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
5177 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
5178 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
5179 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
5180 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
5181 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
5182 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
5183 * TIM20_TISEL TI1SEL LL_TIM_SetRemap
5184 * @param TIMx Timer instance
5185 * @param Remap Remap param depends on the TIMx. Description available only
5186 * in CHM version of the User Manual (not in .pdf).
5187 * Otherwise see Reference Manual description of TISEL registers.
5188 *
5189 * Below description summarizes "Timer Instance" and "Remap" param combinations:
5190 *
5191 * TIM1: one of the following values
5192 *
5193 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
5194 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
5195 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
5196 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
5197 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
5198 *
5199 * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
5200 *
5201 * . . TI1_RMP can be one of the following values
5202 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
5203 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
5204 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
5205 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
5206 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
5207 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
5208 *
5209 * . . TI2_RMP can be one of the following values
5210 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
5211 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
5212 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
5213 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
5214 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
5215 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
5216 *
5217 * . . TI3_RMP can be one of the following values
5218 * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
5219 * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
5220 *
5221 * . . TI4_RMP can be one of the following values
5222 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
5223 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
5224 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
5225 *
5226 * TIM3: any combination of TI1_RMP and TI2_RMP where
5227 *
5228 * . . TI1_RMP can be one of the following values
5229 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
5230 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
5231 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
5232 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
5233 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
5234 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
5235 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
5236 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
5237 *
5238 * . . TI2_RMP can be one of the following values
5239 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
5240 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
5241 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
5242 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
5243 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
5244 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
5245 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
5246 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
5247 *
5248 * . . TI3_RMP can be one of the following values
5249 * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
5250 * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
5251 *
5252 * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
5253 *
5254 * . . TI1_RMP can be one of the following values
5255 * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
5256 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
5257 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
5258 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
5259 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
5260 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
5261 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
5262 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
5263 *
5264 * . . TI2_RMP can be one of the following values
5265 * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
5266 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
5267 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
5268 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
5269 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
5270 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
5271 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
5272 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
5273 *
5274 * . . TI3_RMP can be one of the following values
5275 * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
5276 * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
5277 *
5278 * . . TI4_RMP can be one of the following values
5279 * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
5280 * @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
5281 *
5282 * TIM5: any combination of TI1_RMP and TI2_RMP where (**)
5283 *
5284 * . . TI1_RMP can be one of the following values
5285 * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*)
5286 * @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*)
5287 * @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*)
5288 * @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
5289 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*)
5290 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*)
5291 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*)
5292 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*)
5293 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*)
5294 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*)
5295 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*)
5296 *
5297 * . . TI2_RMP can be one of the following values
5298 * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*)
5299 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
5300 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
5301 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
5302 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
5303 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
5304 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
5305 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
5306 *
5307 * TIM8: one of the following values
5308 *
5309 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
5310 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
5311 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
5312 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
5313 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
5314 *
5315 * TIM15: any combination of TI1_RMP and TI2_RMP where
5316 *
5317 * . . TI1_RMP can be one of the following values
5318 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
5319 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
5320 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
5321 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
5322 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
5323 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
5324 *
5325 * . . TI2_RMP can be one of the following values
5326 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
5327 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
5328 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
5329 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
5330 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
5331 *
5332 * TIM16: one of the following values
5333 *
5334 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
5335 * @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
5336 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
5337 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
5338 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
5339 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
5340 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
5341 *
5342 * TIM17: one of the following values
5343 *
5344 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
5345 * @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
5346 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
5347 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
5348 * @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
5349 * @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
5350 * @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
5351 *
5352 * TIM20: one of the following values (**)
5353 *
5354 * @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*)
5355 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
5356 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
5357 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
5358 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
5359 *
5360 * (*) Value not defined in all devices. \n
5361 * (**) Register not available in all devices.
5362 *
5363 *
5364 * @retval None
5365 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)5366 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
5367 {
5368 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
5369 }
5370
5371 /**
5372 * @brief Enable request for HSE/32 clock used for TISEL remap.
5373 * @note Only TIM16 and TIM17 support HSE/32 remap
5374 * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
5375 * @param TIMx Timer instance
5376 * @retval None
5377 */
LL_TIM_EnableHSE32(TIM_TypeDef * TIMx)5378 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
5379 {
5380 SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
5381 }
5382
5383 /**
5384 * @brief Disable request for HSE/32 clock used for TISEL remap.
5385 * @note Only TIM16 and TIM17 support HSE/32 remap
5386 * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
5387 * @param TIMx Timer instance
5388 * @retval None
5389 */
LL_TIM_DisableHSE32(TIM_TypeDef * TIMx)5390 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
5391 {
5392 CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
5393 }
5394
5395 /**
5396 * @brief Indicate whether request for HSE/32 clock is enabled.
5397 * @note Only TIM16 and TIM17 support HSE/32 remap
5398 * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
5399 * @param TIMx Timer instance
5400 * @retval State of bit (1 or 0).
5401 */
LL_TIM_IsEnabledHSE32(const TIM_TypeDef * TIMx)5402 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx)
5403 {
5404 return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
5405 }
5406
5407 /**
5408 * @}
5409 */
5410
5411 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
5412 * @{
5413 */
5414 /**
5415 * @brief Set the OCREF clear input source
5416 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
5417 * @note This function can only be used in Output compare and PWM modes.
5418 * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
5419 * or not a timer instance can configure OCREF clear input source.
5420 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
5421 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
5422 * @param TIMx Timer instance
5423 * @param OCRefClearInputSource This parameter can be one of the following values:
5424 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
5425 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
5426 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
5427 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
5428 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
5429 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
5430 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
5431 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
5432 *
5433 * (*) Value not defined in all devices. \n
5434 * @retval None
5435 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)5436 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
5437 {
5438 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
5439 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
5440 MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
5441 }
5442 /**
5443 * @}
5444 */
5445
5446 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
5447 * @{
5448 */
5449 /**
5450 * @brief Clear the update interrupt flag (UIF).
5451 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5452 * @param TIMx Timer instance
5453 * @retval None
5454 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5455 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5456 {
5457 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5458 }
5459
5460 /**
5461 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5462 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5463 * @param TIMx Timer instance
5464 * @retval State of bit (1 or 0).
5465 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)5466 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
5467 {
5468 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5469 }
5470
5471 /**
5472 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5473 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5474 * @param TIMx Timer instance
5475 * @retval None
5476 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5477 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5478 {
5479 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5480 }
5481
5482 /**
5483 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5484 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5485 * @param TIMx Timer instance
5486 * @retval State of bit (1 or 0).
5487 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)5488 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
5489 {
5490 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5491 }
5492
5493 /**
5494 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5495 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5496 * @param TIMx Timer instance
5497 * @retval None
5498 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5499 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5500 {
5501 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5502 }
5503
5504 /**
5505 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5506 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5507 * @param TIMx Timer instance
5508 * @retval State of bit (1 or 0).
5509 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)5510 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
5511 {
5512 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5513 }
5514
5515 /**
5516 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5517 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5518 * @param TIMx Timer instance
5519 * @retval None
5520 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5521 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5522 {
5523 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5524 }
5525
5526 /**
5527 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5528 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5529 * @param TIMx Timer instance
5530 * @retval State of bit (1 or 0).
5531 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)5532 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
5533 {
5534 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5535 }
5536
5537 /**
5538 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5539 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5540 * @param TIMx Timer instance
5541 * @retval None
5542 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5543 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5544 {
5545 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5546 }
5547
5548 /**
5549 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5550 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5551 * @param TIMx Timer instance
5552 * @retval State of bit (1 or 0).
5553 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)5554 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
5555 {
5556 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5557 }
5558
5559 /**
5560 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5561 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5562 * @param TIMx Timer instance
5563 * @retval None
5564 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5565 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5566 {
5567 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5568 }
5569
5570 /**
5571 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5572 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5573 * @param TIMx Timer instance
5574 * @retval State of bit (1 or 0).
5575 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)5576 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
5577 {
5578 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5579 }
5580
5581 /**
5582 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5583 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5584 * @param TIMx Timer instance
5585 * @retval None
5586 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5587 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5588 {
5589 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5590 }
5591
5592 /**
5593 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5594 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5595 * @param TIMx Timer instance
5596 * @retval State of bit (1 or 0).
5597 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)5598 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
5599 {
5600 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5601 }
5602
5603 /**
5604 * @brief Clear the commutation interrupt flag (COMIF).
5605 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5606 * @param TIMx Timer instance
5607 * @retval None
5608 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5609 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5610 {
5611 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5612 }
5613
5614 /**
5615 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5616 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5617 * @param TIMx Timer instance
5618 * @retval State of bit (1 or 0).
5619 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5620 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5621 {
5622 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5623 }
5624
5625 /**
5626 * @brief Clear the trigger interrupt flag (TIF).
5627 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5628 * @param TIMx Timer instance
5629 * @retval None
5630 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5631 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5632 {
5633 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5634 }
5635
5636 /**
5637 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5638 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5639 * @param TIMx Timer instance
5640 * @retval State of bit (1 or 0).
5641 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5642 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5643 {
5644 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5645 }
5646
5647 /**
5648 * @brief Clear the break interrupt flag (BIF).
5649 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5650 * @param TIMx Timer instance
5651 * @retval None
5652 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5653 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5654 {
5655 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5656 }
5657
5658 /**
5659 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5660 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5661 * @param TIMx Timer instance
5662 * @retval State of bit (1 or 0).
5663 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5664 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5665 {
5666 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5667 }
5668
5669 /**
5670 * @brief Clear the break 2 interrupt flag (B2IF).
5671 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5672 * @param TIMx Timer instance
5673 * @retval None
5674 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5675 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5676 {
5677 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5678 }
5679
5680 /**
5681 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5682 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5683 * @param TIMx Timer instance
5684 * @retval State of bit (1 or 0).
5685 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5686 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5687 {
5688 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5689 }
5690
5691 /**
5692 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5693 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5694 * @param TIMx Timer instance
5695 * @retval None
5696 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5697 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5698 {
5699 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5700 }
5701
5702 /**
5703 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5704 * (Capture/Compare 1 interrupt is pending).
5705 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5706 * @param TIMx Timer instance
5707 * @retval State of bit (1 or 0).
5708 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5709 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5710 {
5711 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5712 }
5713
5714 /**
5715 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5716 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5717 * @param TIMx Timer instance
5718 * @retval None
5719 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5720 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5721 {
5722 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5723 }
5724
5725 /**
5726 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5727 * (Capture/Compare 2 over-capture interrupt is pending).
5728 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5729 * @param TIMx Timer instance
5730 * @retval State of bit (1 or 0).
5731 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5732 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5733 {
5734 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5735 }
5736
5737 /**
5738 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5739 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5740 * @param TIMx Timer instance
5741 * @retval None
5742 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5743 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5744 {
5745 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5746 }
5747
5748 /**
5749 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5750 * (Capture/Compare 3 over-capture interrupt is pending).
5751 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5752 * @param TIMx Timer instance
5753 * @retval State of bit (1 or 0).
5754 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5755 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5756 {
5757 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5758 }
5759
5760 /**
5761 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5762 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5763 * @param TIMx Timer instance
5764 * @retval None
5765 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5766 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5767 {
5768 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5769 }
5770
5771 /**
5772 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5773 * (Capture/Compare 4 over-capture interrupt is pending).
5774 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5775 * @param TIMx Timer instance
5776 * @retval State of bit (1 or 0).
5777 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5778 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5779 {
5780 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5781 }
5782
5783 /**
5784 * @brief Clear the system break interrupt flag (SBIF).
5785 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5786 * @param TIMx Timer instance
5787 * @retval None
5788 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5789 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5790 {
5791 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5792 }
5793
5794 /**
5795 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5796 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5797 * @param TIMx Timer instance
5798 * @retval State of bit (1 or 0).
5799 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5800 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5801 {
5802 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5803 }
5804
5805 /**
5806 * @brief Clear the transition error interrupt flag (TERRF).
5807 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5808 * a timer instance provides encoder error management.
5809 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5810 * @param TIMx Timer instance
5811 * @retval None
5812 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5813 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5814 {
5815 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5816 }
5817
5818 /**
5819 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5820 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5821 * a timer instance provides encoder error management.
5822 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5823 * @param TIMx Timer instance
5824 * @retval State of bit (1 or 0).
5825 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5826 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5827 {
5828 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5829 }
5830
5831 /**
5832 * @brief Clear the index error interrupt flag (IERRF).
5833 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5834 * a timer instance provides encoder error management.
5835 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5836 * @param TIMx Timer instance
5837 * @retval None
5838 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5839 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5840 {
5841 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5842 }
5843
5844 /**
5845 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5846 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5847 * a timer instance provides encoder error management.
5848 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5849 * @param TIMx Timer instance
5850 * @retval State of bit (1 or 0).
5851 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5852 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5853 {
5854 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5855 }
5856
5857 /**
5858 * @brief Clear the direction change interrupt flag (DIRF).
5859 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5860 * a timer instance provides encoder interrupt management.
5861 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5862 * @param TIMx Timer instance
5863 * @retval None
5864 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5865 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5866 {
5867 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5868 }
5869
5870 /**
5871 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5872 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5873 * a timer instance provides encoder interrupt management.
5874 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5875 * @param TIMx Timer instance
5876 * @retval State of bit (1 or 0).
5877 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5878 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5879 {
5880 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5881 }
5882
5883 /**
5884 * @brief Clear the index interrupt flag (IDXF).
5885 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5886 * a timer instance provides encoder interrupt management.
5887 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5888 * @param TIMx Timer instance
5889 * @retval None
5890 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5891 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5892 {
5893 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5894 }
5895
5896 /**
5897 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5898 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5899 * a timer instance provides encoder interrupt management.
5900 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5901 * @param TIMx Timer instance
5902 * @retval State of bit (1 or 0).
5903 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5904 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5905 {
5906 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5907 }
5908 /**
5909 * @}
5910 */
5911
5912 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5913 * @{
5914 */
5915 /**
5916 * @brief Enable update interrupt (UIE).
5917 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5918 * @param TIMx Timer instance
5919 * @retval None
5920 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5921 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5922 {
5923 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5924 }
5925
5926 /**
5927 * @brief Disable update interrupt (UIE).
5928 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5929 * @param TIMx Timer instance
5930 * @retval None
5931 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5932 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5933 {
5934 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5935 }
5936
5937 /**
5938 * @brief Indicates whether the update interrupt (UIE) is enabled.
5939 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5940 * @param TIMx Timer instance
5941 * @retval State of bit (1 or 0).
5942 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5943 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5944 {
5945 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5946 }
5947
5948 /**
5949 * @brief Enable capture/compare 1 interrupt (CC1IE).
5950 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5951 * @param TIMx Timer instance
5952 * @retval None
5953 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5954 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5955 {
5956 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5957 }
5958
5959 /**
5960 * @brief Disable capture/compare 1 interrupt (CC1IE).
5961 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5962 * @param TIMx Timer instance
5963 * @retval None
5964 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5965 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5966 {
5967 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5968 }
5969
5970 /**
5971 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5972 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5973 * @param TIMx Timer instance
5974 * @retval State of bit (1 or 0).
5975 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5976 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5977 {
5978 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5979 }
5980
5981 /**
5982 * @brief Enable capture/compare 2 interrupt (CC2IE).
5983 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5984 * @param TIMx Timer instance
5985 * @retval None
5986 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5987 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5988 {
5989 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5990 }
5991
5992 /**
5993 * @brief Disable capture/compare 2 interrupt (CC2IE).
5994 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5995 * @param TIMx Timer instance
5996 * @retval None
5997 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5998 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5999 {
6000 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
6001 }
6002
6003 /**
6004 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
6005 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
6006 * @param TIMx Timer instance
6007 * @retval State of bit (1 or 0).
6008 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)6009 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
6010 {
6011 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
6012 }
6013
6014 /**
6015 * @brief Enable capture/compare 3 interrupt (CC3IE).
6016 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
6017 * @param TIMx Timer instance
6018 * @retval None
6019 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)6020 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
6021 {
6022 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
6023 }
6024
6025 /**
6026 * @brief Disable capture/compare 3 interrupt (CC3IE).
6027 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
6028 * @param TIMx Timer instance
6029 * @retval None
6030 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)6031 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
6032 {
6033 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
6034 }
6035
6036 /**
6037 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
6038 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
6039 * @param TIMx Timer instance
6040 * @retval State of bit (1 or 0).
6041 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)6042 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
6043 {
6044 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
6045 }
6046
6047 /**
6048 * @brief Enable capture/compare 4 interrupt (CC4IE).
6049 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
6050 * @param TIMx Timer instance
6051 * @retval None
6052 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)6053 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
6054 {
6055 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
6056 }
6057
6058 /**
6059 * @brief Disable capture/compare 4 interrupt (CC4IE).
6060 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
6061 * @param TIMx Timer instance
6062 * @retval None
6063 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)6064 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
6065 {
6066 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
6067 }
6068
6069 /**
6070 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
6071 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
6072 * @param TIMx Timer instance
6073 * @retval State of bit (1 or 0).
6074 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)6075 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
6076 {
6077 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
6078 }
6079
6080 /**
6081 * @brief Enable commutation interrupt (COMIE).
6082 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
6083 * @param TIMx Timer instance
6084 * @retval None
6085 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)6086 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
6087 {
6088 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
6089 }
6090
6091 /**
6092 * @brief Disable commutation interrupt (COMIE).
6093 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
6094 * @param TIMx Timer instance
6095 * @retval None
6096 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)6097 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
6098 {
6099 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
6100 }
6101
6102 /**
6103 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
6104 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
6105 * @param TIMx Timer instance
6106 * @retval State of bit (1 or 0).
6107 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)6108 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
6109 {
6110 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
6111 }
6112
6113 /**
6114 * @brief Enable trigger interrupt (TIE).
6115 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
6116 * @param TIMx Timer instance
6117 * @retval None
6118 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)6119 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
6120 {
6121 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
6122 }
6123
6124 /**
6125 * @brief Disable trigger interrupt (TIE).
6126 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
6127 * @param TIMx Timer instance
6128 * @retval None
6129 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)6130 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
6131 {
6132 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
6133 }
6134
6135 /**
6136 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
6137 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
6138 * @param TIMx Timer instance
6139 * @retval State of bit (1 or 0).
6140 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)6141 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
6142 {
6143 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
6144 }
6145
6146 /**
6147 * @brief Enable break interrupt (BIE).
6148 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
6149 * @param TIMx Timer instance
6150 * @retval None
6151 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)6152 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
6153 {
6154 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
6155 }
6156
6157 /**
6158 * @brief Disable break interrupt (BIE).
6159 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
6160 * @param TIMx Timer instance
6161 * @retval None
6162 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)6163 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
6164 {
6165 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
6166 }
6167
6168 /**
6169 * @brief Indicates whether the break interrupt (BIE) is enabled.
6170 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
6171 * @param TIMx Timer instance
6172 * @retval State of bit (1 or 0).
6173 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)6174 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
6175 {
6176 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
6177 }
6178
6179 /**
6180 * @brief Enable transition error interrupt (TERRIE).
6181 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6182 * a timer instance provides encoder error management.
6183 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
6184 * @param TIMx Timer instance
6185 * @retval None
6186 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)6187 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
6188 {
6189 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6190 }
6191
6192 /**
6193 * @brief Disable transition error interrupt (TERRIE).
6194 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6195 * a timer instance provides encoder error management.
6196 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
6197 * @param TIMx Timer instance
6198 * @retval None
6199 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)6200 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
6201 {
6202 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6203 }
6204
6205 /**
6206 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
6207 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6208 * a timer instance provides encoder error management.
6209 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
6210 * @param TIMx Timer instance
6211 * @retval State of bit (1 or 0).
6212 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)6213 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
6214 {
6215 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
6216 }
6217
6218 /**
6219 * @brief Enable index error interrupt (IERRIE).
6220 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6221 * a timer instance provides encoder error management.
6222 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
6223 * @param TIMx Timer instance
6224 * @retval None
6225 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)6226 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
6227 {
6228 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6229 }
6230
6231 /**
6232 * @brief Disable index error interrupt (IERRIE).
6233 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6234 * a timer instance provides encoder error management.
6235 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
6236 * @param TIMx Timer instance
6237 * @retval None
6238 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)6239 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
6240 {
6241 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6242 }
6243
6244 /**
6245 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
6246 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6247 * a timer instance provides encoder error management.
6248 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
6249 * @param TIMx Timer instance
6250 * @retval State of bit (1 or 0).
6251 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)6252 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
6253 {
6254 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
6255 }
6256
6257 /**
6258 * @brief Enable direction change interrupt (DIRIE).
6259 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6260 * a timer instance provides encoder interrupt management.
6261 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
6262 * @param TIMx Timer instance
6263 * @retval None
6264 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)6265 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
6266 {
6267 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6268 }
6269
6270 /**
6271 * @brief Disable direction change interrupt (DIRIE).
6272 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6273 * a timer instance provides encoder interrupt management.
6274 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
6275 * @param TIMx Timer instance
6276 * @retval None
6277 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)6278 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
6279 {
6280 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6281 }
6282
6283 /**
6284 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
6285 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6286 * a timer instance provides encoder interrupt management.
6287 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
6288 * @param TIMx Timer instance
6289 * @retval State of bit (1 or 0).
6290 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)6291 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
6292 {
6293 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
6294 }
6295
6296 /**
6297 * @brief Enable index interrupt (IDXIE).
6298 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6299 * a timer instance provides encoder interrupt management.
6300 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
6301 * @param TIMx Timer instance
6302 * @retval None
6303 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)6304 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
6305 {
6306 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6307 }
6308
6309 /**
6310 * @brief Disable index interrupt (IDXIE).
6311 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6312 * a timer instance provides encoder interrupt management.
6313 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
6314 * @param TIMx Timer instance
6315 * @retval None
6316 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)6317 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
6318 {
6319 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6320 }
6321
6322 /**
6323 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
6324 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6325 * a timer instance provides encoder interrupt management.
6326 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
6327 * @param TIMx Timer instance
6328 * @retval State of bit (1 or 0).
6329 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)6330 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
6331 {
6332 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
6333 }
6334
6335 /**
6336 * @}
6337 */
6338
6339 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
6340 * @{
6341 */
6342 /**
6343 * @brief Enable update DMA request (UDE).
6344 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
6345 * @param TIMx Timer instance
6346 * @retval None
6347 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)6348 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6349 {
6350 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
6351 }
6352
6353 /**
6354 * @brief Disable update DMA request (UDE).
6355 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
6356 * @param TIMx Timer instance
6357 * @retval None
6358 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)6359 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6360 {
6361 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
6362 }
6363
6364 /**
6365 * @brief Indicates whether the update DMA request (UDE) is enabled.
6366 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
6367 * @param TIMx Timer instance
6368 * @retval State of bit (1 or 0).
6369 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)6370 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
6371 {
6372 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
6373 }
6374
6375 /**
6376 * @brief Enable capture/compare 1 DMA request (CC1DE).
6377 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
6378 * @param TIMx Timer instance
6379 * @retval None
6380 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)6381 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
6382 {
6383 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6384 }
6385
6386 /**
6387 * @brief Disable capture/compare 1 DMA request (CC1DE).
6388 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
6389 * @param TIMx Timer instance
6390 * @retval None
6391 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)6392 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
6393 {
6394 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6395 }
6396
6397 /**
6398 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
6399 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
6400 * @param TIMx Timer instance
6401 * @retval State of bit (1 or 0).
6402 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)6403 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
6404 {
6405 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
6406 }
6407
6408 /**
6409 * @brief Enable capture/compare 2 DMA request (CC2DE).
6410 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
6411 * @param TIMx Timer instance
6412 * @retval None
6413 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)6414 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
6415 {
6416 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6417 }
6418
6419 /**
6420 * @brief Disable capture/compare 2 DMA request (CC2DE).
6421 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
6422 * @param TIMx Timer instance
6423 * @retval None
6424 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)6425 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
6426 {
6427 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6428 }
6429
6430 /**
6431 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
6432 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
6433 * @param TIMx Timer instance
6434 * @retval State of bit (1 or 0).
6435 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)6436 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
6437 {
6438 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
6439 }
6440
6441 /**
6442 * @brief Enable capture/compare 3 DMA request (CC3DE).
6443 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
6444 * @param TIMx Timer instance
6445 * @retval None
6446 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)6447 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
6448 {
6449 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6450 }
6451
6452 /**
6453 * @brief Disable capture/compare 3 DMA request (CC3DE).
6454 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6455 * @param TIMx Timer instance
6456 * @retval None
6457 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6458 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6459 {
6460 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6461 }
6462
6463 /**
6464 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6465 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6466 * @param TIMx Timer instance
6467 * @retval State of bit (1 or 0).
6468 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)6469 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
6470 {
6471 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6472 }
6473
6474 /**
6475 * @brief Enable capture/compare 4 DMA request (CC4DE).
6476 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6477 * @param TIMx Timer instance
6478 * @retval None
6479 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6480 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6481 {
6482 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6483 }
6484
6485 /**
6486 * @brief Disable capture/compare 4 DMA request (CC4DE).
6487 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6488 * @param TIMx Timer instance
6489 * @retval None
6490 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6491 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6492 {
6493 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6494 }
6495
6496 /**
6497 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6498 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6499 * @param TIMx Timer instance
6500 * @retval State of bit (1 or 0).
6501 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)6502 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
6503 {
6504 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6505 }
6506
6507 /**
6508 * @brief Enable commutation DMA request (COMDE).
6509 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6510 * @param TIMx Timer instance
6511 * @retval None
6512 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6513 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6514 {
6515 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6516 }
6517
6518 /**
6519 * @brief Disable commutation DMA request (COMDE).
6520 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6521 * @param TIMx Timer instance
6522 * @retval None
6523 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6524 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6525 {
6526 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6527 }
6528
6529 /**
6530 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6531 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6532 * @param TIMx Timer instance
6533 * @retval State of bit (1 or 0).
6534 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)6535 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
6536 {
6537 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6538 }
6539
6540 /**
6541 * @brief Enable trigger interrupt (TDE).
6542 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6543 * @param TIMx Timer instance
6544 * @retval None
6545 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6546 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6547 {
6548 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6549 }
6550
6551 /**
6552 * @brief Disable trigger interrupt (TDE).
6553 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6554 * @param TIMx Timer instance
6555 * @retval None
6556 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6557 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6558 {
6559 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6560 }
6561
6562 /**
6563 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6564 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6565 * @param TIMx Timer instance
6566 * @retval State of bit (1 or 0).
6567 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)6568 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
6569 {
6570 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6571 }
6572
6573 /**
6574 * @}
6575 */
6576
6577 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6578 * @{
6579 */
6580 /**
6581 * @brief Generate an update event.
6582 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6583 * @param TIMx Timer instance
6584 * @retval None
6585 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6586 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6587 {
6588 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6589 }
6590
6591 /**
6592 * @brief Generate Capture/Compare 1 event.
6593 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6594 * @param TIMx Timer instance
6595 * @retval None
6596 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6597 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6598 {
6599 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6600 }
6601
6602 /**
6603 * @brief Generate Capture/Compare 2 event.
6604 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6605 * @param TIMx Timer instance
6606 * @retval None
6607 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6608 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6609 {
6610 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6611 }
6612
6613 /**
6614 * @brief Generate Capture/Compare 3 event.
6615 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6616 * @param TIMx Timer instance
6617 * @retval None
6618 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6619 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6620 {
6621 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6622 }
6623
6624 /**
6625 * @brief Generate Capture/Compare 4 event.
6626 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6627 * @param TIMx Timer instance
6628 * @retval None
6629 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6630 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6631 {
6632 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6633 }
6634
6635 /**
6636 * @brief Generate commutation event.
6637 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6638 * @param TIMx Timer instance
6639 * @retval None
6640 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6641 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6642 {
6643 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6644 }
6645
6646 /**
6647 * @brief Generate trigger event.
6648 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6649 * @param TIMx Timer instance
6650 * @retval None
6651 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6652 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6653 {
6654 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6655 }
6656
6657 /**
6658 * @brief Generate break event.
6659 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6660 * @param TIMx Timer instance
6661 * @retval None
6662 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6663 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6664 {
6665 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6666 }
6667
6668 /**
6669 * @brief Generate break 2 event.
6670 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6671 * @param TIMx Timer instance
6672 * @retval None
6673 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6674 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6675 {
6676 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6677 }
6678
6679 /**
6680 * @}
6681 */
6682
6683 #if defined(USE_FULL_LL_DRIVER)
6684 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6685 * @{
6686 */
6687
6688 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6689 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6690 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6691 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6692 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6693 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6694 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6695 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6696 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6697 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6698 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6699 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6700 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6701 /**
6702 * @}
6703 */
6704 #endif /* USE_FULL_LL_DRIVER */
6705
6706 /**
6707 * @}
6708 */
6709
6710 /**
6711 * @}
6712 */
6713
6714 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
6715
6716 /**
6717 * @}
6718 */
6719
6720 #ifdef __cplusplus
6721 }
6722 #endif
6723
6724 #endif /* __STM32G4xx_LL_TIM_H */
6725
