1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32N6xx_LL_TIM_H
21 #define __STM32N6xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx.h"
29
30 /** @addtogroup STM32N6xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM9) \
43 || defined (TIM10) \
44 || defined (TIM11) \
45 || defined (TIM12) \
46 || defined (TIM13) \
47 || defined (TIM14) \
48 || defined (TIM15) \
49 || defined (TIM16) \
50 || defined (TIM17) \
51 || defined (TIM18)
52
53 /** @defgroup TIM_LL TIM
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
60 * @{
61 */
62 static const uint8_t OFFSET_TAB_CCMRx[] =
63 {
64 0x00U, /* 0: TIMx_CH1 */
65 0x00U, /* 1: TIMx_CH1N */
66 0x00U, /* 2: TIMx_CH2 */
67 0x00U, /* 3: TIMx_CH2N */
68 0x04U, /* 4: TIMx_CH3 */
69 0x04U, /* 5: TIMx_CH3N */
70 0x04U, /* 6: TIMx_CH4 */
71 0x04U, /* 7: TIMx_CH4N */
72 0x38U, /* 8: TIMx_CH5 */
73 0x38U /* 9: TIMx_CH6 */
74
75 };
76
77 static const uint8_t SHIFT_TAB_OCxx[] =
78 {
79 0U, /* 0: OC1M, OC1FE, OC1PE */
80 0U, /* 1: - NA */
81 8U, /* 2: OC2M, OC2FE, OC2PE */
82 0U, /* 3: - NA */
83 0U, /* 4: OC3M, OC3FE, OC3PE */
84 0U, /* 5: - NA */
85 8U, /* 6: OC4M, OC4FE, OC4PE */
86 0U, /* 7: - NA */
87 0U, /* 8: OC5M, OC5FE, OC5PE */
88 8U /* 9: OC6M, OC6FE, OC6PE */
89 };
90
91 static const uint8_t SHIFT_TAB_ICxx[] =
92 {
93 0U, /* 0: CC1S, IC1PSC, IC1F */
94 0U, /* 1: - NA */
95 8U, /* 2: CC2S, IC2PSC, IC2F */
96 0U, /* 3: - NA */
97 0U, /* 4: CC3S, IC3PSC, IC3F */
98 0U, /* 5: - NA */
99 8U, /* 6: CC4S, IC4PSC, IC4F */
100 0U, /* 7: - NA */
101 0U, /* 8: - NA */
102 0U /* 9: - NA */
103 };
104
105 static const uint8_t SHIFT_TAB_CCxP[] =
106 {
107 0U, /* 0: CC1P */
108 2U, /* 1: CC1NP */
109 4U, /* 2: CC2P */
110 6U, /* 3: CC2NP */
111 8U, /* 4: CC3P */
112 10U, /* 5: CC3NP */
113 12U, /* 6: CC4P */
114 14U, /* 7: CC4NP */
115 16U, /* 8: CC5P */
116 20U /* 9: CC6P */
117 };
118
119 static const uint8_t SHIFT_TAB_OISx[] =
120 {
121 0U, /* 0: OIS1 */
122 1U, /* 1: OIS1N */
123 2U, /* 2: OIS2 */
124 3U, /* 3: OIS2N */
125 4U, /* 4: OIS3 */
126 5U, /* 5: OIS3N */
127 6U, /* 6: OIS4 */
128 7U, /* 7: OIS4N */
129 8U, /* 8: OIS5 */
130 10U /* 9: OIS6 */
131 };
132 /**
133 * @}
134 */
135
136 /* Private constants ---------------------------------------------------------*/
137 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
138 * @{
139 */
140
141 /* Defines used for the bit position in the register and perform offsets */
142 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
143
144 /* Generic bit definitions for TIMx_AF1 register */
145 #define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */
146 #define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */
147
148
149 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
150 #define DT_DELAY_1 ((uint8_t)0x7F)
151 #define DT_DELAY_2 ((uint8_t)0x3F)
152 #define DT_DELAY_3 ((uint8_t)0x1F)
153 #define DT_DELAY_4 ((uint8_t)0x1F)
154
155 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
156 #define DT_RANGE_1 ((uint8_t)0x00)
157 #define DT_RANGE_2 ((uint8_t)0x80)
158 #define DT_RANGE_3 ((uint8_t)0xC0)
159 #define DT_RANGE_4 ((uint8_t)0xE0)
160
161 /** Legacy definitions for compatibility purpose
162 @cond 0
163 */
164 /**
165 @endcond
166 */
167
168 /**
169 * @}
170 */
171
172 /* Private macros ------------------------------------------------------------*/
173 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
174 * @{
175 */
176 /** @brief Convert channel id into channel index.
177 * @param __CHANNEL__ This parameter can be one of the following values:
178 * @arg @ref LL_TIM_CHANNEL_CH1
179 * @arg @ref LL_TIM_CHANNEL_CH1N
180 * @arg @ref LL_TIM_CHANNEL_CH2
181 * @arg @ref LL_TIM_CHANNEL_CH2N
182 * @arg @ref LL_TIM_CHANNEL_CH3
183 * @arg @ref LL_TIM_CHANNEL_CH3N
184 * @arg @ref LL_TIM_CHANNEL_CH4
185 * @arg @ref LL_TIM_CHANNEL_CH4N
186 * @arg @ref LL_TIM_CHANNEL_CH5
187 * @arg @ref LL_TIM_CHANNEL_CH6
188 * @retval none
189 */
190 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
191 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
196 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
197 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
198 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
199 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
200
201 /** @brief Calculate the deadtime sampling period(in ps).
202 * @param __TIMCLK__ timer input clock frequency (in Hz).
203 * @param __CKD__ This parameter can be one of the following values:
204 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
205 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
206 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
207 * @retval none
208 */
209 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
210 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
211 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
212 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
213 /**
214 * @}
215 */
216
217
218 /* Exported types ------------------------------------------------------------*/
219 #if defined(USE_FULL_LL_DRIVER)
220 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
221 * @{
222 */
223
224 /**
225 * @brief TIM Time Base configuration structure definition.
226 */
227 typedef struct
228 {
229 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
230 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
231
232 This feature can be modified afterwards using unitary function
233 @ref LL_TIM_SetPrescaler().*/
234
235 uint32_t CounterMode; /*!< Specifies the counter mode.
236 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
237
238 This feature can be modified afterwards using unitary function
239 @ref LL_TIM_SetCounterMode().*/
240
241 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
242 Auto-Reload Register at the next update event.
243 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
244 Some timer instances may support 32 bits counters. In that case this parameter must
245 be a number between 0x0000 and 0xFFFFFFFF.
246
247 This feature can be modified afterwards using unitary function
248 @ref LL_TIM_SetAutoReload().*/
249
250 uint32_t ClockDivision; /*!< Specifies the clock division.
251 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
252
253 This feature can be modified afterwards using unitary function
254 @ref LL_TIM_SetClockDivision().*/
255
256 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
257 reaches zero, an update event is generated and counting restarts
258 from the RCR value (N).
259 This means in PWM mode that (N+1) corresponds to:
260 - the number of PWM periods in edge-aligned mode
261 - the number of half PWM period in center-aligned mode
262 GP timers: this parameter must be a number between Min_Data = 0x00 and
263 Max_Data = 0xFF.
264 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
265 Max_Data = 0xFFFF.
266
267 This feature can be modified afterwards using unitary function
268 @ref LL_TIM_SetRepetitionCounter().*/
269 } LL_TIM_InitTypeDef;
270
271 /**
272 * @brief TIM Output Compare configuration structure definition.
273 */
274 typedef struct
275 {
276 uint32_t OCMode; /*!< Specifies the output mode.
277 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
278
279 This feature can be modified afterwards using unitary function
280 @ref LL_TIM_OC_SetMode().*/
281
282 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
283 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
284
285 This feature can be modified afterwards using unitary functions
286 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
287
288 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
289 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
290
291 This feature can be modified afterwards using unitary functions
292 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
293
294 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
295 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
296
297 This feature can be modified afterwards using unitary function
298 LL_TIM_OC_SetCompareCHx (x=1..6).*/
299
300 uint32_t OCPolarity; /*!< Specifies the output polarity.
301 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
302
303 This feature can be modified afterwards using unitary function
304 @ref LL_TIM_OC_SetPolarity().*/
305
306 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
307 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
308
309 This feature can be modified afterwards using unitary function
310 @ref LL_TIM_OC_SetPolarity().*/
311
312
313 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
314 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
315
316 This feature can be modified afterwards using unitary function
317 @ref LL_TIM_OC_SetIdleState().*/
318
319 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
320 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
321
322 This feature can be modified afterwards using unitary function
323 @ref LL_TIM_OC_SetIdleState().*/
324 } LL_TIM_OC_InitTypeDef;
325
326 /**
327 * @brief TIM Input Capture configuration structure definition.
328 */
329
330 typedef struct
331 {
332
333 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
334 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
335
336 This feature can be modified afterwards using unitary function
337 @ref LL_TIM_IC_SetPolarity().*/
338
339 uint32_t ICActiveInput; /*!< Specifies the input.
340 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
341
342 This feature can be modified afterwards using unitary function
343 @ref LL_TIM_IC_SetActiveInput().*/
344
345 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
346 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
347
348 This feature can be modified afterwards using unitary function
349 @ref LL_TIM_IC_SetPrescaler().*/
350
351 uint32_t ICFilter; /*!< Specifies the input capture filter.
352 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
353
354 This feature can be modified afterwards using unitary function
355 @ref LL_TIM_IC_SetFilter().*/
356 } LL_TIM_IC_InitTypeDef;
357
358
359 /**
360 * @brief TIM Encoder interface configuration structure definition.
361 */
362 typedef struct
363 {
364 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
365 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
366
367 This feature can be modified afterwards using unitary function
368 @ref LL_TIM_SetEncoderMode().*/
369
370 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
371 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
372
373 This feature can be modified afterwards using unitary function
374 @ref LL_TIM_IC_SetPolarity().*/
375
376 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
377 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
378
379 This feature can be modified afterwards using unitary function
380 @ref LL_TIM_IC_SetActiveInput().*/
381
382 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
383 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
384
385 This feature can be modified afterwards using unitary function
386 @ref LL_TIM_IC_SetPrescaler().*/
387
388 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
389 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
390
391 This feature can be modified afterwards using unitary function
392 @ref LL_TIM_IC_SetFilter().*/
393
394 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
395 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
396
397 This feature can be modified afterwards using unitary function
398 @ref LL_TIM_IC_SetPolarity().*/
399
400 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
401 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
402
403 This feature can be modified afterwards using unitary function
404 @ref LL_TIM_IC_SetActiveInput().*/
405
406 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
407 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
408
409 This feature can be modified afterwards using unitary function
410 @ref LL_TIM_IC_SetPrescaler().*/
411
412 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
413 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
414
415 This feature can be modified afterwards using unitary function
416 @ref LL_TIM_IC_SetFilter().*/
417
418 } LL_TIM_ENCODER_InitTypeDef;
419
420 /**
421 * @brief TIM Hall sensor interface configuration structure definition.
422 */
423 typedef struct
424 {
425
426 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
427 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
428
429 This feature can be modified afterwards using unitary function
430 @ref LL_TIM_IC_SetPolarity().*/
431
432 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
433 Prescaler must be set to get a maximum counter period longer than the
434 time interval between 2 consecutive changes on the Hall inputs.
435 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
436
437 This feature can be modified afterwards using unitary function
438 @ref LL_TIM_IC_SetPrescaler().*/
439
440 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
441 This parameter can be a value of
442 @ref TIM_LL_EC_IC_FILTER.
443
444 This feature can be modified afterwards using unitary function
445 @ref LL_TIM_IC_SetFilter().*/
446
447 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
448 A positive pulse (TRGO event) is generated with a programmable delay every time
449 a change occurs on the Hall inputs.
450 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
451
452 This feature can be modified afterwards using unitary function
453 @ref LL_TIM_OC_SetCompareCH2().*/
454 } LL_TIM_HALLSENSOR_InitTypeDef;
455
456 /**
457 * @brief BDTR (Break and Dead Time) structure definition
458 */
459 typedef struct
460 {
461 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
462 This parameter can be a value of @ref TIM_LL_EC_OSSR
463
464 This feature can be modified afterwards using unitary function
465 @ref LL_TIM_SetOffStates()
466
467 @note This bit-field cannot be modified as long as LOCK level 2 has been
468 programmed. */
469
470 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
471 This parameter can be a value of @ref TIM_LL_EC_OSSI
472
473 This feature can be modified afterwards using unitary function
474 @ref LL_TIM_SetOffStates()
475
476 @note This bit-field cannot be modified as long as LOCK level 2 has been
477 programmed. */
478
479 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
480 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
481
482 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
483 register has been written, their content is frozen until the next reset.*/
484
485 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
486 switching-on of the outputs.
487 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
488
489 This feature can be modified afterwards using unitary function
490 @ref LL_TIM_OC_SetDeadTime()
491
492 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
493 programmed. */
494
495 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
496 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
497
498 This feature can be modified afterwards using unitary functions
499 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
500
501 @note This bit-field can not be modified as long as LOCK level 1 has been
502 programmed. */
503
504 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
505 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
506
507 This feature can be modified afterwards using unitary function
508 @ref LL_TIM_ConfigBRK()
509
510 @note This bit-field can not be modified as long as LOCK level 1 has been
511 programmed. */
512
513 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
514 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
515
516 This feature can be modified afterwards using unitary function
517 @ref LL_TIM_ConfigBRK()
518
519 @note This bit-field can not be modified as long as LOCK level 1 has been
520 programmed. */
521
522 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
523 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
524
525 This feature can be modified afterwards using unitary functions
526 @ref LL_TIM_ConfigBRK()
527
528 @note Bidirectional break input is only supported by advanced timers instances.
529
530 @note This bit-field can not be modified as long as LOCK level 1 has been
531 programmed. */
532
533 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
534 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
535
536 This feature can be modified afterwards using unitary functions
537 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
538
539 @note This bit-field can not be modified as long as LOCK level 1 has been
540 programmed. */
541
542 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
543 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
544
545 This feature can be modified afterwards using unitary function
546 @ref LL_TIM_ConfigBRK2()
547
548 @note This bit-field can not be modified as long as LOCK level 1 has been
549 programmed. */
550
551 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
552 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
553
554 This feature can be modified afterwards using unitary function
555 @ref LL_TIM_ConfigBRK2()
556
557 @note This bit-field can not be modified as long as LOCK level 1 has been
558 programmed. */
559
560 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
561 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
562
563 This feature can be modified afterwards using unitary functions
564 @ref LL_TIM_ConfigBRK2()
565
566 @note Bidirectional break input is only supported by advanced timers instances.
567
568 @note This bit-field can not be modified as long as LOCK level 1 has been
569 programmed. */
570
571 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
572 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
573
574 This feature can be modified afterwards using unitary functions
575 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
576
577 @note This bit-field can not be modified as long as LOCK level 1 has been
578 programmed. */
579 } LL_TIM_BDTR_InitTypeDef;
580
581 /**
582 * @}
583 */
584 #endif /* USE_FULL_LL_DRIVER */
585
586 /* Exported constants --------------------------------------------------------*/
587 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
588 * @{
589 */
590
591 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
592 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
593 * @{
594 */
595 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
596 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
597 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
598 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
599 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
600 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
601 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
602 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
603 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
604 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
605 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
606 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
607 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
608 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
609 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
610 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
611 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
612 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
613 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
614 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
615 /**
616 * @}
617 */
618
619 #if defined(USE_FULL_LL_DRIVER)
620 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
621 * @{
622 */
623 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
624 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
625 /**
626 * @}
627 */
628
629 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
630 * @{
631 */
632 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
633 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
634 /**
635 * @}
636 */
637
638 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
639 * @{
640 */
641 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
642 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
643 /**
644 * @}
645 */
646 #endif /* USE_FULL_LL_DRIVER */
647
648 /** @defgroup TIM_LL_EC_IT IT Defines
649 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
650 * @{
651 */
652 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
653 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
654 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
655 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
656 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
657 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
658 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
659 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
660 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
661 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
662 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
663 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
664 /**
665 * @}
666 */
667
668 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
669 * @{
670 */
671 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
672 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
673 /**
674 * @}
675 */
676
677 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
678 * @{
679 */
680 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
681 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
682 /**
683 * @}
684 */
685
686 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
687 * @{
688 */
689 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
690 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
691 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
692 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
693 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
694 /**
695 * @}
696 */
697
698 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
699 * @{
700 */
701 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
702 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
703 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
704 /**
705 * @}
706 */
707
708 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
709 * @{
710 */
711 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
712 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
713 /**
714 * @}
715 */
716
717 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
718 * @{
719 */
720 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
721 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
722 /**
723 * @}
724 */
725
726 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
727 * @{
728 */
729 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
730 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
736 * @{
737 */
738 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
739 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
740 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
741 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
742 /**
743 * @}
744 */
745
746 /** @defgroup TIM_LL_EC_CHANNEL Channel
747 * @{
748 */
749 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
750 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
751 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
752 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
753 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
754 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
755 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
756 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
757 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
758 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
759 /**
760 * @}
761 */
762
763 #if defined(USE_FULL_LL_DRIVER)
764 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
765 * @{
766 */
767 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
768 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
769 /**
770 * @}
771 */
772 #endif /* USE_FULL_LL_DRIVER */
773
774 /** Legacy definitions for compatibility purpose
775 @cond 0
776 */
777 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
778 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
779 /**
780 @endcond
781 */
782
783 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
784 * @{
785 */
786 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
787 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
788 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
789 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
790 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
791 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
792 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
793 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
794 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
795 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
796 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
797 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
798 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
799 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
800 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
801 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
802 /**
803 * @}
804 */
805
806 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
807 * @{
808 */
809 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
810 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
811 /**
812 * @}
813 */
814
815 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
816 * @{
817 */
818 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
819 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
820 /**
821 * @}
822 */
823
824 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
825 * @{
826 */
827 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
828 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
829 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
830 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
831 /**
832 * @}
833 */
834
835 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
836 * @{
837 */
838 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
839 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
840 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
841 /**
842 * @}
843 */
844
845 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
846 * @{
847 */
848 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
849 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
850 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
851 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
852 /**
853 * @}
854 */
855
856 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
857 * @{
858 */
859 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
860 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
861 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
862 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
863 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
864 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
865 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
866 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
867 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
868 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
869 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
870 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
871 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
872 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
873 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
874 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
875 /**
876 * @}
877 */
878
879 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
880 * @{
881 */
882 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
883 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
884 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
885 /**
886 * @}
887 */
888
889 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
890 * @{
891 */
892 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
893 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
894 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
895 /**
896 * @}
897 */
898
899 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
900 * @{
901 */
902 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
903 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
904 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
905 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
906 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
907 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
908 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
909 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
910 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
911 /**
912 * @}
913 */
914
915 /** @defgroup TIM_LL_EC_TRGO Trigger Output
916 * @{
917 */
918 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
919 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
920 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
921 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
922 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
923 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
924 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
925 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
926 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
927 /**
928 * @}
929 */
930
931 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
932 * @{
933 */
934 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
935 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
936 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
937 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
938 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
939 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
940 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
941 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
942 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
943 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
944 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
945 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
946 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
947 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
948 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
949 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
950 /**
951 * @}
952 */
953
954 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
955 * @{
956 */
957 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
958 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
959 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
960 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
961 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
962 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
963 the counter are controlled. */
964 /**
965 * @}
966 */
967
968 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
969 * @{
970 */
971 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
972 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
973 /**
974 * @}
975 */
976
977 /** @defgroup TIM_LL_EC_TS Trigger Selection
978 * @{
979 */
980 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
981 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
982 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
983 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
984 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */
985 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
986 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
987 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
988 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
989 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
990 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
991 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
992 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
993 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_4 | TIM_SMCR_TS_0) /*!< Internal Trigger 13 (ITR13) is used as trigger input */
994 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
995 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
996 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
997 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
998 /**
999 * @}
1000 */
1001
1002 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
1003 * @{
1004 */
1005 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
1006 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
1007 /**
1008 * @}
1009 */
1010
1011 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
1012 * @{
1013 */
1014 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
1015 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
1016 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1017 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1023 * @{
1024 */
1025 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1026 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1027 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1028 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1029 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1030 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1031 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1032 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1033 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1034 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1035 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1036 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1037 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1038 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1039 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1040 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1046 * @{
1047 */
1048 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000UL /*!< TIM1_ETR is connected to I/O */
1049 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
1050 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to ADC1 AWD2 */
1051 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
1052 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD1 */
1053 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC2 AWD2 */
1054 #define LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3 TIM_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC2 AWD3 */
1055 /**
1056 * @}
1057 */
1058
1059 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1060 * @{
1061 */
1062 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000UL /*!< TIM2_ETR is connected to I/O */
1063 #define LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC TIM_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to DCMIPP HSYNC */
1064 #define LL_TIM_TIM2_ETRSOURCE_LCD_HSYNC TIM_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to LCD HSYNC */
1065 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
1066 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */
1067 #define LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to GFXTIM TE */
1068 #define LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DCMIPP VSYNC */
1069 #define LL_TIM_TIM2_ETRSOURCE_LCD_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to LCD VSYNC */
1070 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM3 ETR */
1071 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */
1072 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM2_ETR is connected to TIM5 ETR */
1073 #define LL_TIM_TIM2_ETRSOURCE_ETH1_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to ETH1 PPS */
1074 #define LL_TIM_TIM2_ETRSOURCE_USB1_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to USB1 OTG SOF */
1075 #define LL_TIM_TIM2_ETRSOURCE_USB2_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to USB2 OTG SOF */
1076 /**
1077 * @}
1078 */
1079
1080 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1081 * @{
1082 */
1083 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000UL /*!< TIM3_ETR is connected to I/O */
1084 #define LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC TIM_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to DCMIPP HSYNC */
1085 #define LL_TIM_TIM3_ETRSOURCE_LCD_HSYNC TIM_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to LCD HSYNC */
1086 #define LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to GFXTIM TE */
1087 #define LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to DCMIPP VSYNC */
1088 #define LL_TIM_TIM3_ETRSOURCE_LCD_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to LCD VSYNC */
1089 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM2 ETR */
1090 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */
1091 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to TIM5 ETR */
1092 #define LL_TIM_TIM3_ETRSOURCE_ETH1_PPS (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ETH1 PPS */
1093 /**
1094 * @}
1095 */
1096
1097 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1098 * @{
1099 */
1100 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000UL /*!< TIM4_ETR is connected to I/O */
1101 #define LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC TIM_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to DCMIPP HSYNC */
1102 #define LL_TIM_TIM4_ETRSOURCE_LCD_HSYNC TIM_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to LCD HSYNC */
1103 #define LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to GFXTIM TE */
1104 #define LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to DCMIPP VSYNC */
1105 #define LL_TIM_TIM4_ETRSOURCE_LCD_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to LCD VSYNC */
1106 #define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM2 ETR */
1107 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to TIM3 ETR */
1108 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM4_ETR is connected to TIM5 ETR */
1109 /**
1110 * @}
1111 */
1112
1113 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1114 * @{
1115 */
1116 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000UL /*!< TIM5_ETR is connected to I/O */
1117 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */
1118 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */
1119 #define LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to DCMIPP HSYNC */
1120 #define LL_TIM_TIM5_ETRSOURCE_LCD_HSYNC TIM_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to LCD HSYNC */
1121 #define LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to GFXTIM TE */
1122 #define LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to DCMIPP VSYNC */
1123 #define LL_TIM_TIM5_ETRSOURCE_LCD_VSYNC TIM_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to LCD VSYNC */
1124 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM2 ETR */
1125 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to TIM3 ETR */
1126 #define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM5 ETR */
1127 #define LL_TIM_TIM5_ETRSOURCE_USB1_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to USB1 OTG SOF */
1128 #define LL_TIM_TIM5_ETRSOURCE_USB2_SOF (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to USB2 OTG SOF */
1129 /**
1130 * @}
1131 */
1132
1133 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1134 * @{
1135 */
1136 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000UL /*!< TIM8_ETR is connected to I/O */
1137 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */
1138 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 TIM_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to ADC2 AWD2 */
1139 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */
1140 /**
1141 * @}
1142 */
1143
1144 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1145 * @{
1146 */
1147 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1148 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1149 /**
1150 * @}
1151 */
1152
1153 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1154 * @{
1155 */
1156 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1157 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1158 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1159 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1160 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1161 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1162 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1163 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1164 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1165 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1166 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1167 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1168 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1169 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1170 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1171 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1172 /**
1173 * @}
1174 */
1175
1176 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1177 * @{
1178 */
1179 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1180 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1181 /**
1182 * @}
1183 */
1184
1185 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1186 * @{
1187 */
1188 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1189 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1190 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1191 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1192 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1193 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1194 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1195 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1196 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1197 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1198 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1199 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1200 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1201 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1202 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1203 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1204 /**
1205 * @}
1206 */
1207
1208 /** @defgroup TIM_LL_EC_OSSI OSSI
1209 * @{
1210 */
1211 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1212 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1213 /**
1214 * @}
1215 */
1216
1217 /** @defgroup TIM_LL_EC_OSSR OSSR
1218 * @{
1219 */
1220 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1221 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1227 * @{
1228 */
1229 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1230 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1236 * @{
1237 */
1238 #define LL_TIM_BKIN_SOURCE_BKIN TIM_AF1_BKINE /*!< BKIN input from AF controller */
1239 #define LL_TIM_BKIN_SOURCE_MDF1 TIM_AF1_BKCMP8E /*!< internal signal: MDF1 output */
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1245 * @{
1246 */
1247 #define LL_TIM_BKIN_POLARITY_LOW TIM_AF1_BKINP /*!< BRK BKIN input is active low */
1248 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1254 * @{
1255 */
1256 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1257 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1263 * @{
1264 */
1265 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1266 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1267 /**
1268 * @}
1269 */
1270
1271 /** Legacy definitions for compatibility purpose
1272 @cond 0
1273 */
1274 #define LL_TIM_ReArmBRK(_PARAM_)
1275 #define LL_TIM_ReArmBRK2(_PARAM_)
1276 /**
1277 @endcond
1278 */
1279
1280 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1281 * @{
1282 */
1283 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1284 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1285 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1286 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1287 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1288 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1289 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1290 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1291 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1292 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1293 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1294 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1295 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1296 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1297 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1298 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1299 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1300 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1301 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1302 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1303 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1304 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1305 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1306 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1307 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1308 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1309 /**
1310 * @}
1311 */
1312
1313 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1314 * @{
1315 */
1316 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1317 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1318 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1319 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1320 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1321 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1322 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1323 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1324 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1325 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1326 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1327 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1328 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1329 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1330 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1331 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1332 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1333 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1334 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1335 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1336 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1337 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1338 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1339 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1340 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1341 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1342 /**
1343 * @}
1344 */
1345
1346 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1347 * @{
1348 */
1349 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1350 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1351 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1352 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1353 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1354 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1355 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1356 /**
1357 * @}
1358 */
1359
1360 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1361 * @{
1362 */
1363 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1364 #define LL_TIM_TIM2_TI1_RMP_ETH1_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH1 PPS */
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1370 * @{
1371 */
1372 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
1373 #define LL_TIM_TIM3_TI1_RMP_ETH1_PPS TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to ETH1 PPS */
1374 #define LL_TIM_TIM3_TI1_RMP_FDCAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to FDCAN RTP */
1375 #define LL_TIM_TIM3_TI1_RMP_FDCAN_TMP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3_TI1 is connected to FDCAN TMP */
1376 #define LL_TIM_TIM3_TI1_RMP_FDCAN_SOC TIM_TISEL_TI1SEL_2 /*!< TIM3_TI1 is connected to FDCAN SOC */
1377 /**
1378 * @}
1379 */
1380
1381 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 External Input Ch1 Remap
1382 * @{
1383 */
1384 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */
1385 #define LL_TIM_TIM5_TI1_RMP_FDCAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to FDCAN RTP */
1386 #define LL_TIM_TIM5_TI1_RMP_FDCAN_TMP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to FDCAN TMP */
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 External Input Ch1 Remap
1392 * @{
1393 */
1394 #define LL_TIM_TIM9_TI1_RMP_GPIO 0x00000000UL /*!< TIM9_TI1 is connected to GPIO */
1395 #define LL_TIM_TIM9_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_2 /*!< TIM9_TI1 is connected to MCO1 */
1396 #define LL_TIM_TIM9_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM9_TI1 is connected to MCO2 */
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP TIM10 External Input Ch1 Remap
1402 * @{
1403 */
1404 #define LL_TIM_TIM10_TI1_RMP_GPIO 0x00000000UL /*!< TIM10_TI1 is connected to GPIO */
1405 #define LL_TIM_TIM10_TI1_RMP_I3C1_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM10_TI1 is connected to I3C1 IBI ACK */
1406 /**
1407 * @}
1408 */
1409
1410 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Ch1 Remap
1411 * @{
1412 */
1413 #define LL_TIM_TIM11_TI1_RMP_GPIO 0x00000000UL /*!< TIM11_TI1 is connected to GPIO */
1414 #define LL_TIM_TIM11_TI1_RMP_I3C2_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM11_TI1 is connected to I3C2 IBI ACK */
1415 /**
1416 * @}
1417 */
1418
1419 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 External Input Ch1 Remap
1420 * @{
1421 */
1422 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */
1423 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */
1424 #define LL_TIM_TIM12_TI1_RMP_HSI_1024 TIM_TISEL_TI1SEL_1 /*!< TIM12_TI1 is connected to HSI/1024 */
1425 #define LL_TIM_TIM12_TI1_RMP_MSI_128 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to MSI/128 */
1426 #define LL_TIM_TIM12_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to MCO1 */
1427 #define LL_TIM_TIM12_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to MCO2 */
1428 /**
1429 * @}
1430 */
1431
1432 /** @defgroup TIM_LL_EC_TIM13_TI1_RMP TIM13 External Input Ch1 Remap
1433 * @{
1434 */
1435 #define LL_TIM_TIM13_TI1_RMP_GPIO 0x00000000UL /*!< TIM13_TI1 is connected to GPIO */
1436 #define LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM13_TI1 is connected to I3C1 IBI ACK */
1437 /**
1438 * @}
1439 */
1440
1441 /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 External Input Ch1 Remap
1442 * @{
1443 */
1444 #define LL_TIM_TIM14_TI1_RMP_GPIO 0x00000000UL /*!< TIM14_TI1 is connected to GPIO */
1445 #define LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK TIM_TISEL_TI1SEL_0 /*!< TIM14_TI1 is connected to I3C2 IBI ACK */
1446 /**
1447 * @}
1448 */
1449
1450 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1451 * @{
1452 */
1453 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1454 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 GPIO */
1455 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 GPIO */
1456 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 CH1 GPIO */
1457 #define LL_TIM_TIM15_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to MCO1 */
1458 #define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to MCO2 */
1459 /**
1460 * @}
1461 */
1462
1463 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
1464 * @{
1465 */
1466 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */
1467 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 CH2 GPIO */
1468 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 CH2 GPIO */
1469 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 CH2 GPIO */
1470 /**
1471 * @}
1472 */
1473
1474 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1475 * @{
1476 */
1477 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */
1478 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 TI1 is connected to LSI */
1479 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to LSE */
1480 #define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC Wakeup */
1481 /**
1482 * @}
1483 */
1484
1485 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1486 * @{
1487 */
1488 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
1489 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17_TI1 is connected to SPDIFRX FS */
1490 #define LL_TIM_TIM17_TI1_RMP_HSE_1024 TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to HSE/1024 */
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1496 * @{
1497 */
1498 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1499 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1500 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1501 /**
1502 * @}
1503 */
1504
1505 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1506 * @{
1507 */
1508 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1509 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1510 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1511 /**
1512 * @}
1513 */
1514
1515 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1516 * @{
1517 */
1518 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1519 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1520 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1521 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1522 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1523 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1524 /**
1525 * @}
1526 */
1527
1528 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1529 * @{
1530 */
1531 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1532 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1533 /**
1534 * @}
1535 */
1536 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1537 * @{
1538 */
1539 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1540 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1541 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1542 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1543 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1544 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1545 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1546 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1547 /**
1548 * @}
1549 */
1550
1551 /** Legacy definitions for compatibility purpose
1552 @cond 0
1553 */
1554 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1555 /**
1556 @endcond
1557 */
1558
1559 /**
1560 * @}
1561 */
1562
1563 /* Exported macro ------------------------------------------------------------*/
1564 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1565 * @{
1566 */
1567
1568 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1569 * @{
1570 */
1571 /**
1572 * @brief Write a value in TIM register.
1573 * @param __INSTANCE__ TIM Instance
1574 * @param __REG__ Register to be written
1575 * @param __VALUE__ Value to be written in the register
1576 * @retval None
1577 */
1578 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1579
1580 /**
1581 * @brief Read a value in TIM register.
1582 * @param __INSTANCE__ TIM Instance
1583 * @param __REG__ Register to be read
1584 * @retval Register value
1585 */
1586 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1587 /**
1588 * @}
1589 */
1590
1591 /**
1592 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1593 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1594 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1595 * to TIMx_CNT register bit 31)
1596 * @param __CNT__ Counter value
1597 * @retval UIF status bit
1598 */
1599 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1600 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1601
1602 /**
1603 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1604 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1605 * @param __TIMCLK__ timer input clock frequency (in Hz)
1606 * @param __CKD__ This parameter can be one of the following values:
1607 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1608 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1609 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1610 * @param __DT__ deadtime duration (in ns)
1611 * @retval DTG[0:7]
1612 */
1613 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1614 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1615 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1616 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1617 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1618 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1619 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1620 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1621 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1622 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1623 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1624 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1625 0U)
1626
1627 /**
1628 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1629 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1630 * @param __TIMCLK__ timer input clock frequency (in Hz)
1631 * @param __CNTCLK__ counter clock frequency (in Hz)
1632 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1633 */
1634 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1635 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1636
1637 /**
1638 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1639 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1640 * @param __TIMCLK__ timer input clock frequency (in Hz)
1641 * @param __PSC__ prescaler
1642 * @param __FREQ__ output signal frequency (in Hz)
1643 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1644 */
1645 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1646 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1647
1648 /**
1649 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1650 * output signal frequency.
1651 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1652 * @param __TIMCLK__ timer input clock frequency (in Hz)
1653 * @param __PSC__ prescaler
1654 * @param __FREQ__ output signal frequency (in Hz)
1655 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1656 */
1657 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1658 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1659 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1660
1661 /**
1662 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1663 * active/inactive delay.
1664 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1665 * @param __TIMCLK__ timer input clock frequency (in Hz)
1666 * @param __PSC__ prescaler
1667 * @param __DELAY__ timer output compare active/inactive delay (in us)
1668 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1669 */
1670 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1671 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1672 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1673
1674 /**
1675 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1676 * output compare active/inactive delay.
1677 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1678 * @param __TIMCLK__ timer input clock frequency (in Hz)
1679 * @param __PSC__ prescaler
1680 * @param __DELAY__ timer output compare active/inactive delay (in us)
1681 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1682 */
1683 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1684 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1685 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1686
1687 /**
1688 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1689 * (when the timer operates in one pulse mode).
1690 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1691 * @param __TIMCLK__ timer input clock frequency (in Hz)
1692 * @param __PSC__ prescaler
1693 * @param __DELAY__ timer output compare active/inactive delay (in us)
1694 * @param __PULSE__ pulse duration (in us)
1695 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1696 */
1697 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1698 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1699 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1700
1701 /**
1702 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1703 * pulse duration (when the timer operates in one pulse mode).
1704 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1705 * @param __TIMCLK__ timer input clock frequency (in Hz)
1706 * @param __PSC__ prescaler
1707 * @param __DELAY__ timer output compare active/inactive delay (in us)
1708 * @param __PULSE__ pulse duration (in us)
1709 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1710 */
1711 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1712 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1713 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1714
1715 /**
1716 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1717 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1718 * @param __ICPSC__ This parameter can be one of the following values:
1719 * @arg @ref LL_TIM_ICPSC_DIV1
1720 * @arg @ref LL_TIM_ICPSC_DIV2
1721 * @arg @ref LL_TIM_ICPSC_DIV4
1722 * @arg @ref LL_TIM_ICPSC_DIV8
1723 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1724 */
1725 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1726 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1727
1728
1729 /**
1730 * @}
1731 */
1732
1733 /* Exported functions --------------------------------------------------------*/
1734 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1735 * @{
1736 */
1737
1738 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1739 * @{
1740 */
1741 /**
1742 * @brief Enable timer counter.
1743 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1744 * @param TIMx Timer instance
1745 * @retval None
1746 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1747 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1748 {
1749 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1750 }
1751
1752 /**
1753 * @brief Disable timer counter.
1754 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1755 * @param TIMx Timer instance
1756 * @retval None
1757 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1758 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1759 {
1760 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1761 }
1762
1763 /**
1764 * @brief Indicates whether the timer counter is enabled.
1765 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1766 * @param TIMx Timer instance
1767 * @retval State of bit (1 or 0).
1768 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1769 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1770 {
1771 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1772 }
1773
1774 /**
1775 * @brief Enable update event generation.
1776 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1777 * @param TIMx Timer instance
1778 * @retval None
1779 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1780 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1781 {
1782 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1783 }
1784
1785 /**
1786 * @brief Disable update event generation.
1787 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1788 * @param TIMx Timer instance
1789 * @retval None
1790 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1791 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1792 {
1793 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1794 }
1795
1796 /**
1797 * @brief Indicates whether update event generation is enabled.
1798 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1799 * @param TIMx Timer instance
1800 * @retval Inverted state of bit (0 or 1).
1801 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1802 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1803 {
1804 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1805 }
1806
1807 /**
1808 * @brief Set update event source
1809 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1810 * generate an update interrupt or DMA request if enabled:
1811 * - Counter overflow/underflow
1812 * - Setting the UG bit
1813 * - Update generation through the slave mode controller
1814 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1815 * overflow/underflow generates an update interrupt or DMA request if enabled.
1816 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1817 * @param TIMx Timer instance
1818 * @param UpdateSource This parameter can be one of the following values:
1819 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1820 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1821 * @retval None
1822 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1823 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1824 {
1825 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1826 }
1827
1828 /**
1829 * @brief Get actual event update source
1830 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1831 * @param TIMx Timer instance
1832 * @retval Returned value can be one of the following values:
1833 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1834 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1835 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1836 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1837 {
1838 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1839 }
1840
1841 /**
1842 * @brief Set one pulse mode (one shot v.s. repetitive).
1843 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1844 * @param TIMx Timer instance
1845 * @param OnePulseMode This parameter can be one of the following values:
1846 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1847 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1848 * @retval None
1849 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1850 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1851 {
1852 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1853 }
1854
1855 /**
1856 * @brief Get actual one pulse mode.
1857 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1858 * @param TIMx Timer instance
1859 * @retval Returned value can be one of the following values:
1860 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1861 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1862 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1863 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1864 {
1865 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1866 }
1867
1868 /**
1869 * @brief Set the timer counter counting mode.
1870 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1871 * check whether or not the counter mode selection feature is supported
1872 * by a timer instance.
1873 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1874 * requires a timer reset to avoid unexpected direction
1875 * due to DIR bit readonly in center aligned mode.
1876 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1877 * CR1 CMS LL_TIM_SetCounterMode
1878 * @param TIMx Timer instance
1879 * @param CounterMode This parameter can be one of the following values:
1880 * @arg @ref LL_TIM_COUNTERMODE_UP
1881 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1882 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1883 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1884 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1885 * @retval None
1886 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1887 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1888 {
1889 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1890 }
1891
1892 /**
1893 * @brief Get actual counter mode.
1894 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1895 * check whether or not the counter mode selection feature is supported
1896 * by a timer instance.
1897 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1898 * CR1 CMS LL_TIM_GetCounterMode
1899 * @param TIMx Timer instance
1900 * @retval Returned value can be one of the following values:
1901 * @arg @ref LL_TIM_COUNTERMODE_UP
1902 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1903 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1904 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1905 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1906 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1907 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1908 {
1909 uint32_t counter_mode;
1910
1911 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1912
1913 if (counter_mode == 0U)
1914 {
1915 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1916 }
1917
1918 return counter_mode;
1919 }
1920
1921 /**
1922 * @brief Enable auto-reload (ARR) preload.
1923 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1924 * @param TIMx Timer instance
1925 * @retval None
1926 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1927 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1928 {
1929 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1930 }
1931
1932 /**
1933 * @brief Disable auto-reload (ARR) preload.
1934 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1935 * @param TIMx Timer instance
1936 * @retval None
1937 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1938 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1939 {
1940 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1941 }
1942
1943 /**
1944 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1945 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1946 * @param TIMx Timer instance
1947 * @retval State of bit (1 or 0).
1948 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1949 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1950 {
1951 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1952 }
1953
1954 /**
1955 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1956 * (when supported) and the digital filters.
1957 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1958 * whether or not the clock division feature is supported by the timer
1959 * instance.
1960 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1961 * @param TIMx Timer instance
1962 * @param ClockDivision This parameter can be one of the following values:
1963 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1964 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1965 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1966 * @retval None
1967 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1968 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1969 {
1970 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1971 }
1972
1973 /**
1974 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1975 * generators (when supported) and the digital filters.
1976 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1977 * whether or not the clock division feature is supported by the timer
1978 * instance.
1979 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1980 * @param TIMx Timer instance
1981 * @retval Returned value can be one of the following values:
1982 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1983 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1984 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1985 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1986 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1987 {
1988 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1989 }
1990
1991 /**
1992 * @brief Set the counter value.
1993 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1994 * whether or not a timer instance supports a 32 bits counter.
1995 * @note If dithering is activated, pay attention to the Counter value interpretation
1996 * @rmtoll CNT CNT LL_TIM_SetCounter
1997 * @param TIMx Timer instance
1998 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1999 * @retval None
2000 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2001 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2002 {
2003 WRITE_REG(TIMx->CNT, Counter);
2004 }
2005
2006 /**
2007 * @brief Get the counter value.
2008 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2009 * whether or not a timer instance supports a 32 bits counter.
2010 * @note If dithering is activated, pay attention to the Counter value interpretation
2011 * @rmtoll CNT CNT LL_TIM_GetCounter
2012 * @param TIMx Timer instance
2013 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2014 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)2015 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
2016 {
2017 return (uint32_t)(READ_REG(TIMx->CNT));
2018 }
2019
2020 /**
2021 * @brief Get the current direction of the counter
2022 * @rmtoll CR1 DIR LL_TIM_GetDirection
2023 * @param TIMx Timer instance
2024 * @retval Returned value can be one of the following values:
2025 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2026 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2027 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)2028 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
2029 {
2030 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2031 }
2032
2033 /**
2034 * @brief Set the prescaler value.
2035 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2036 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2037 * prescaler ratio is taken into account at the next update event.
2038 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2039 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2040 * @param TIMx Timer instance
2041 * @param Prescaler between Min_Data=0 and Max_Data=65535
2042 * @retval None
2043 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2044 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2045 {
2046 WRITE_REG(TIMx->PSC, Prescaler);
2047 }
2048
2049 /**
2050 * @brief Get the prescaler value.
2051 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2052 * @param TIMx Timer instance
2053 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2054 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)2055 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
2056 {
2057 return (uint32_t)(READ_REG(TIMx->PSC));
2058 }
2059
2060 /**
2061 * @brief Set the auto-reload value.
2062 * @note The counter is blocked while the auto-reload value is null.
2063 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2064 * whether or not a timer instance supports a 32 bits counter.
2065 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2066 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2067 * parameter.
2068 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2069 * @param TIMx Timer instance
2070 * @param AutoReload between Min_Data=0 and Max_Data=65535
2071 * @retval None
2072 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2073 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2074 {
2075 WRITE_REG(TIMx->ARR, AutoReload);
2076 }
2077
2078 /**
2079 * @brief Get the auto-reload value.
2080 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2081 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2082 * whether or not a timer instance supports a 32 bits counter.
2083 * @note If dithering is activated, pay attention to the returned value interpretation
2084 * @param TIMx Timer instance
2085 * @retval Auto-reload value
2086 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2087 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2088 {
2089 return (uint32_t)(READ_REG(TIMx->ARR));
2090 }
2091
2092 /**
2093 * @brief Set the repetition counter value.
2094 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2095 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2096 * whether or not a timer instance supports a repetition counter.
2097 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2098 * @param TIMx Timer instance
2099 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2100 * @retval None
2101 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2102 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2103 {
2104 WRITE_REG(TIMx->RCR, RepetitionCounter);
2105 }
2106
2107 /**
2108 * @brief Get the repetition counter value.
2109 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2110 * whether or not a timer instance supports a repetition counter.
2111 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2112 * @param TIMx Timer instance
2113 * @retval Repetition counter value
2114 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2115 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2116 {
2117 return (uint32_t)(READ_REG(TIMx->RCR));
2118 }
2119
2120 /**
2121 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2122 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2123 * in an atomic way.
2124 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2125 * @param TIMx Timer instance
2126 * @retval None
2127 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2128 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2129 {
2130 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2131 }
2132
2133 /**
2134 * @brief Disable update interrupt flag (UIF) remapping.
2135 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2136 * @param TIMx Timer instance
2137 * @retval None
2138 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2139 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2140 {
2141 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2142 }
2143
2144 /**
2145 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2146 * @param Counter Counter value
2147 * @retval State of bit (1 or 0).
2148 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2149 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2150 {
2151 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2152 }
2153
2154 /**
2155 * @brief Enable dithering.
2156 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2157 * a timer instance provides dithering.
2158 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2159 * @param TIMx Timer instance
2160 * @retval None
2161 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2162 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2163 {
2164 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2165 }
2166
2167 /**
2168 * @brief Disable dithering.
2169 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2170 * a timer instance provides dithering.
2171 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2172 * @param TIMx Timer instance
2173 * @retval None
2174 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2175 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2176 {
2177 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2178 }
2179
2180 /**
2181 * @brief Indicates whether dithering is activated.
2182 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2183 * a timer instance provides dithering.
2184 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2185 * @param TIMx Timer instance
2186 * @retval State of bit (1 or 0).
2187 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2188 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2189 {
2190 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2191 }
2192
2193 /**
2194 * @}
2195 */
2196
2197 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2198 * @{
2199 */
2200 /**
2201 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2202 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2203 * they are updated only when a commutation event (COM) occurs.
2204 * @note Only on channels that have a complementary output.
2205 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2206 * whether or not a timer instance is able to generate a commutation event.
2207 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2208 * @param TIMx Timer instance
2209 * @retval None
2210 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2211 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2212 {
2213 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2214 }
2215
2216 /**
2217 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2218 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2219 * whether or not a timer instance is able to generate a commutation event.
2220 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2221 * @param TIMx Timer instance
2222 * @retval None
2223 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2224 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2225 {
2226 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2227 }
2228
2229 /**
2230 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
2231 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
2232 * @param TIMx Timer instance
2233 * @retval State of bit (1 or 0).
2234 */
LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef * TIMx)2235 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
2236 {
2237 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
2238 }
2239
2240 /**
2241 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2242 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2243 * whether or not a timer instance is able to generate a commutation event.
2244 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2245 * @param TIMx Timer instance
2246 * @param CCUpdateSource This parameter can be one of the following values:
2247 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2248 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2249 * @retval None
2250 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2251 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2252 {
2253 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2254 }
2255
2256 /**
2257 * @brief Set the trigger of the capture/compare DMA request.
2258 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2259 * @param TIMx Timer instance
2260 * @param DMAReqTrigger This parameter can be one of the following values:
2261 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2262 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2263 * @retval None
2264 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2265 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2266 {
2267 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2268 }
2269
2270 /**
2271 * @brief Get actual trigger of the capture/compare DMA request.
2272 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2273 * @param TIMx Timer instance
2274 * @retval Returned value can be one of the following values:
2275 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2276 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2277 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2278 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2279 {
2280 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2281 }
2282
2283 /**
2284 * @brief Set the lock level to freeze the
2285 * configuration of several capture/compare parameters.
2286 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2287 * the lock mechanism is supported by a timer instance.
2288 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2289 * @param TIMx Timer instance
2290 * @param LockLevel This parameter can be one of the following values:
2291 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2292 * @arg @ref LL_TIM_LOCKLEVEL_1
2293 * @arg @ref LL_TIM_LOCKLEVEL_2
2294 * @arg @ref LL_TIM_LOCKLEVEL_3
2295 * @retval None
2296 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2297 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2298 {
2299 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2300 }
2301
2302 /**
2303 * @brief Enable capture/compare channels.
2304 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2305 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2306 * CCER CC2E LL_TIM_CC_EnableChannel\n
2307 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2308 * CCER CC3E LL_TIM_CC_EnableChannel\n
2309 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2310 * CCER CC4E LL_TIM_CC_EnableChannel\n
2311 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2312 * CCER CC5E LL_TIM_CC_EnableChannel\n
2313 * CCER CC6E LL_TIM_CC_EnableChannel
2314 * @param TIMx Timer instance
2315 * @param Channels This parameter can be a combination of the following values:
2316 * @arg @ref LL_TIM_CHANNEL_CH1
2317 * @arg @ref LL_TIM_CHANNEL_CH1N
2318 * @arg @ref LL_TIM_CHANNEL_CH2
2319 * @arg @ref LL_TIM_CHANNEL_CH2N
2320 * @arg @ref LL_TIM_CHANNEL_CH3
2321 * @arg @ref LL_TIM_CHANNEL_CH3N
2322 * @arg @ref LL_TIM_CHANNEL_CH4
2323 * @arg @ref LL_TIM_CHANNEL_CH4N
2324 * @arg @ref LL_TIM_CHANNEL_CH5
2325 * @arg @ref LL_TIM_CHANNEL_CH6
2326 * @retval None
2327 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2328 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2329 {
2330 SET_BIT(TIMx->CCER, Channels);
2331 }
2332
2333 /**
2334 * @brief Disable capture/compare channels.
2335 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2336 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2337 * CCER CC2E LL_TIM_CC_DisableChannel\n
2338 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2339 * CCER CC3E LL_TIM_CC_DisableChannel\n
2340 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2341 * CCER CC4E LL_TIM_CC_DisableChannel\n
2342 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2343 * CCER CC5E LL_TIM_CC_DisableChannel\n
2344 * CCER CC6E LL_TIM_CC_DisableChannel
2345 * @param TIMx Timer instance
2346 * @param Channels This parameter can be a combination of the following values:
2347 * @arg @ref LL_TIM_CHANNEL_CH1
2348 * @arg @ref LL_TIM_CHANNEL_CH1N
2349 * @arg @ref LL_TIM_CHANNEL_CH2
2350 * @arg @ref LL_TIM_CHANNEL_CH2N
2351 * @arg @ref LL_TIM_CHANNEL_CH3
2352 * @arg @ref LL_TIM_CHANNEL_CH3N
2353 * @arg @ref LL_TIM_CHANNEL_CH4
2354 * @arg @ref LL_TIM_CHANNEL_CH4N
2355 * @arg @ref LL_TIM_CHANNEL_CH5
2356 * @arg @ref LL_TIM_CHANNEL_CH6
2357 * @retval None
2358 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2359 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2360 {
2361 CLEAR_BIT(TIMx->CCER, Channels);
2362 }
2363
2364 /**
2365 * @brief Indicate whether channel(s) is(are) enabled.
2366 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2367 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2368 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2369 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2370 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2371 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2372 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2373 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2374 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2375 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2376 * @param TIMx Timer instance
2377 * @param Channels This parameter can be a combination of the following values:
2378 * @arg @ref LL_TIM_CHANNEL_CH1
2379 * @arg @ref LL_TIM_CHANNEL_CH1N
2380 * @arg @ref LL_TIM_CHANNEL_CH2
2381 * @arg @ref LL_TIM_CHANNEL_CH2N
2382 * @arg @ref LL_TIM_CHANNEL_CH3
2383 * @arg @ref LL_TIM_CHANNEL_CH3N
2384 * @arg @ref LL_TIM_CHANNEL_CH4
2385 * @arg @ref LL_TIM_CHANNEL_CH4N
2386 * @arg @ref LL_TIM_CHANNEL_CH5
2387 * @arg @ref LL_TIM_CHANNEL_CH6
2388 * @retval State of bit (1 or 0).
2389 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2390 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2391 {
2392 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2393 }
2394
2395 /**
2396 * @}
2397 */
2398
2399 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2400 * @{
2401 */
2402 /**
2403 * @brief Configure an output channel.
2404 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2405 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2406 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2407 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2408 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2409 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2410 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2411 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2412 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2413 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2414 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2415 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2416 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2417 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2418 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2419 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2420 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2421 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2422 * @param TIMx Timer instance
2423 * @param Channel This parameter can be one of the following values:
2424 * @arg @ref LL_TIM_CHANNEL_CH1
2425 * @arg @ref LL_TIM_CHANNEL_CH2
2426 * @arg @ref LL_TIM_CHANNEL_CH3
2427 * @arg @ref LL_TIM_CHANNEL_CH4
2428 * @arg @ref LL_TIM_CHANNEL_CH5
2429 * @arg @ref LL_TIM_CHANNEL_CH6
2430 * @param Configuration This parameter must be a combination of all the following values:
2431 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2432 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2433 * @retval None
2434 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2435 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2436 {
2437 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2438 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2439 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2440 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2441 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2442 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2443 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2444 }
2445
2446 /**
2447 * @brief Define the behavior of the output reference signal OCxREF from which
2448 * OCx and OCxN (when relevant) are derived.
2449 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2450 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2451 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2452 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2453 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2454 * CCMR3 OC6M LL_TIM_OC_SetMode
2455 * @param TIMx Timer instance
2456 * @param Channel This parameter can be one of the following values:
2457 * @arg @ref LL_TIM_CHANNEL_CH1
2458 * @arg @ref LL_TIM_CHANNEL_CH2
2459 * @arg @ref LL_TIM_CHANNEL_CH3
2460 * @arg @ref LL_TIM_CHANNEL_CH4
2461 * @arg @ref LL_TIM_CHANNEL_CH5
2462 * @arg @ref LL_TIM_CHANNEL_CH6
2463 * @param Mode This parameter can be one of the following values:
2464 * @arg @ref LL_TIM_OCMODE_FROZEN
2465 * @arg @ref LL_TIM_OCMODE_ACTIVE
2466 * @arg @ref LL_TIM_OCMODE_INACTIVE
2467 * @arg @ref LL_TIM_OCMODE_TOGGLE
2468 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2469 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2470 * @arg @ref LL_TIM_OCMODE_PWM1
2471 * @arg @ref LL_TIM_OCMODE_PWM2
2472 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2473 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2474 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2475 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2476 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2477 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2478 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2479 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2480 * @retval None
2481 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2482 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2483 {
2484 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2485 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2486 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2487 }
2488
2489 /**
2490 * @brief Get the output compare mode of an output channel.
2491 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2492 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2493 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2494 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2495 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2496 * CCMR3 OC6M LL_TIM_OC_GetMode
2497 * @param TIMx Timer instance
2498 * @param Channel This parameter can be one of the following values:
2499 * @arg @ref LL_TIM_CHANNEL_CH1
2500 * @arg @ref LL_TIM_CHANNEL_CH2
2501 * @arg @ref LL_TIM_CHANNEL_CH3
2502 * @arg @ref LL_TIM_CHANNEL_CH4
2503 * @arg @ref LL_TIM_CHANNEL_CH5
2504 * @arg @ref LL_TIM_CHANNEL_CH6
2505 * @retval Returned value can be one of the following values:
2506 * @arg @ref LL_TIM_OCMODE_FROZEN
2507 * @arg @ref LL_TIM_OCMODE_ACTIVE
2508 * @arg @ref LL_TIM_OCMODE_INACTIVE
2509 * @arg @ref LL_TIM_OCMODE_TOGGLE
2510 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2511 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2512 * @arg @ref LL_TIM_OCMODE_PWM1
2513 * @arg @ref LL_TIM_OCMODE_PWM2
2514 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2515 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2516 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2517 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2518 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
2519 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
2520 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2521 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2522 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2523 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2524 {
2525 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2526 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2527 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2528 }
2529
2530 /**
2531 * @brief Set the polarity of an output channel.
2532 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2533 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2534 * CCER CC2P LL_TIM_OC_SetPolarity\n
2535 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2536 * CCER CC3P LL_TIM_OC_SetPolarity\n
2537 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2538 * CCER CC4P LL_TIM_OC_SetPolarity\n
2539 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2540 * CCER CC5P LL_TIM_OC_SetPolarity\n
2541 * CCER CC6P LL_TIM_OC_SetPolarity
2542 * @param TIMx Timer instance
2543 * @param Channel This parameter can be one of the following values:
2544 * @arg @ref LL_TIM_CHANNEL_CH1
2545 * @arg @ref LL_TIM_CHANNEL_CH1N
2546 * @arg @ref LL_TIM_CHANNEL_CH2
2547 * @arg @ref LL_TIM_CHANNEL_CH2N
2548 * @arg @ref LL_TIM_CHANNEL_CH3
2549 * @arg @ref LL_TIM_CHANNEL_CH3N
2550 * @arg @ref LL_TIM_CHANNEL_CH4
2551 * @arg @ref LL_TIM_CHANNEL_CH4N
2552 * @arg @ref LL_TIM_CHANNEL_CH5
2553 * @arg @ref LL_TIM_CHANNEL_CH6
2554 * @param Polarity This parameter can be one of the following values:
2555 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2556 * @arg @ref LL_TIM_OCPOLARITY_LOW
2557 * @retval None
2558 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2559 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2560 {
2561 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2562 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2563 }
2564
2565 /**
2566 * @brief Get the polarity of an output channel.
2567 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2568 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2569 * CCER CC2P LL_TIM_OC_GetPolarity\n
2570 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2571 * CCER CC3P LL_TIM_OC_GetPolarity\n
2572 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2573 * CCER CC4P LL_TIM_OC_GetPolarity\n
2574 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2575 * CCER CC5P LL_TIM_OC_GetPolarity\n
2576 * CCER CC6P LL_TIM_OC_GetPolarity
2577 * @param TIMx Timer instance
2578 * @param Channel This parameter can be one of the following values:
2579 * @arg @ref LL_TIM_CHANNEL_CH1
2580 * @arg @ref LL_TIM_CHANNEL_CH1N
2581 * @arg @ref LL_TIM_CHANNEL_CH2
2582 * @arg @ref LL_TIM_CHANNEL_CH2N
2583 * @arg @ref LL_TIM_CHANNEL_CH3
2584 * @arg @ref LL_TIM_CHANNEL_CH3N
2585 * @arg @ref LL_TIM_CHANNEL_CH4
2586 * @arg @ref LL_TIM_CHANNEL_CH4N
2587 * @arg @ref LL_TIM_CHANNEL_CH5
2588 * @arg @ref LL_TIM_CHANNEL_CH6
2589 * @retval Returned value can be one of the following values:
2590 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2591 * @arg @ref LL_TIM_OCPOLARITY_LOW
2592 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2593 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2594 {
2595 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2596 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2597 }
2598
2599 /**
2600 * @brief Set the IDLE state of an output channel
2601 * @note This function is significant only for the timer instances
2602 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2603 * can be used to check whether or not a timer instance provides
2604 * a break input.
2605 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2606 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2607 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2608 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2609 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2610 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2611 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2612 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2613 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2614 * CR2 OIS6 LL_TIM_OC_SetIdleState
2615 * @param TIMx Timer instance
2616 * @param Channel This parameter can be one of the following values:
2617 * @arg @ref LL_TIM_CHANNEL_CH1
2618 * @arg @ref LL_TIM_CHANNEL_CH1N
2619 * @arg @ref LL_TIM_CHANNEL_CH2
2620 * @arg @ref LL_TIM_CHANNEL_CH2N
2621 * @arg @ref LL_TIM_CHANNEL_CH3
2622 * @arg @ref LL_TIM_CHANNEL_CH3N
2623 * @arg @ref LL_TIM_CHANNEL_CH4
2624 * @arg @ref LL_TIM_CHANNEL_CH4N
2625 * @arg @ref LL_TIM_CHANNEL_CH5
2626 * @arg @ref LL_TIM_CHANNEL_CH6
2627 * @param IdleState This parameter can be one of the following values:
2628 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2629 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2630 * @retval None
2631 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2632 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2633 {
2634 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2635 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2636 }
2637
2638 /**
2639 * @brief Get the IDLE state of an output channel
2640 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2641 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2642 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2643 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2644 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2645 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2646 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2647 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2648 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2649 * CR2 OIS6 LL_TIM_OC_GetIdleState
2650 * @param TIMx Timer instance
2651 * @param Channel This parameter can be one of the following values:
2652 * @arg @ref LL_TIM_CHANNEL_CH1
2653 * @arg @ref LL_TIM_CHANNEL_CH1N
2654 * @arg @ref LL_TIM_CHANNEL_CH2
2655 * @arg @ref LL_TIM_CHANNEL_CH2N
2656 * @arg @ref LL_TIM_CHANNEL_CH3
2657 * @arg @ref LL_TIM_CHANNEL_CH3N
2658 * @arg @ref LL_TIM_CHANNEL_CH4
2659 * @arg @ref LL_TIM_CHANNEL_CH4N
2660 * @arg @ref LL_TIM_CHANNEL_CH5
2661 * @arg @ref LL_TIM_CHANNEL_CH6
2662 * @retval Returned value can be one of the following values:
2663 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2664 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2665 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2666 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2667 {
2668 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2669 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2670 }
2671
2672 /**
2673 * @brief Enable fast mode for the output channel.
2674 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2675 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2676 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2677 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2678 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2679 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2680 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2681 * @param TIMx Timer instance
2682 * @param Channel This parameter can be one of the following values:
2683 * @arg @ref LL_TIM_CHANNEL_CH1
2684 * @arg @ref LL_TIM_CHANNEL_CH2
2685 * @arg @ref LL_TIM_CHANNEL_CH3
2686 * @arg @ref LL_TIM_CHANNEL_CH4
2687 * @arg @ref LL_TIM_CHANNEL_CH5
2688 * @arg @ref LL_TIM_CHANNEL_CH6
2689 * @retval None
2690 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2691 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2692 {
2693 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2694 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2695 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2696
2697 }
2698
2699 /**
2700 * @brief Disable fast mode for the output channel.
2701 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2702 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2703 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2704 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2705 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2706 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2707 * @param TIMx Timer instance
2708 * @param Channel This parameter can be one of the following values:
2709 * @arg @ref LL_TIM_CHANNEL_CH1
2710 * @arg @ref LL_TIM_CHANNEL_CH2
2711 * @arg @ref LL_TIM_CHANNEL_CH3
2712 * @arg @ref LL_TIM_CHANNEL_CH4
2713 * @arg @ref LL_TIM_CHANNEL_CH5
2714 * @arg @ref LL_TIM_CHANNEL_CH6
2715 * @retval None
2716 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2717 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2718 {
2719 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2720 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2721 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2722
2723 }
2724
2725 /**
2726 * @brief Indicates whether fast mode is enabled for the output channel.
2727 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2728 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2729 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2730 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2731 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2732 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2733 * @param TIMx Timer instance
2734 * @param Channel This parameter can be one of the following values:
2735 * @arg @ref LL_TIM_CHANNEL_CH1
2736 * @arg @ref LL_TIM_CHANNEL_CH2
2737 * @arg @ref LL_TIM_CHANNEL_CH3
2738 * @arg @ref LL_TIM_CHANNEL_CH4
2739 * @arg @ref LL_TIM_CHANNEL_CH5
2740 * @arg @ref LL_TIM_CHANNEL_CH6
2741 * @retval State of bit (1 or 0).
2742 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2743 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2744 {
2745 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2746 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2747 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2748 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2749 }
2750
2751 /**
2752 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2753 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2754 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2755 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2756 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2757 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2758 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2759 * @param TIMx Timer instance
2760 * @param Channel This parameter can be one of the following values:
2761 * @arg @ref LL_TIM_CHANNEL_CH1
2762 * @arg @ref LL_TIM_CHANNEL_CH2
2763 * @arg @ref LL_TIM_CHANNEL_CH3
2764 * @arg @ref LL_TIM_CHANNEL_CH4
2765 * @arg @ref LL_TIM_CHANNEL_CH5
2766 * @arg @ref LL_TIM_CHANNEL_CH6
2767 * @retval None
2768 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2769 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2770 {
2771 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2772 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2773 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2774 }
2775
2776 /**
2777 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2778 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2779 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2780 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2781 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2782 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2783 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2784 * @param TIMx Timer instance
2785 * @param Channel This parameter can be one of the following values:
2786 * @arg @ref LL_TIM_CHANNEL_CH1
2787 * @arg @ref LL_TIM_CHANNEL_CH2
2788 * @arg @ref LL_TIM_CHANNEL_CH3
2789 * @arg @ref LL_TIM_CHANNEL_CH4
2790 * @arg @ref LL_TIM_CHANNEL_CH5
2791 * @arg @ref LL_TIM_CHANNEL_CH6
2792 * @retval None
2793 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2794 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2795 {
2796 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2797 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2798 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2799 }
2800
2801 /**
2802 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2803 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2804 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2805 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2806 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2807 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2808 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2809 * @param TIMx Timer instance
2810 * @param Channel This parameter can be one of the following values:
2811 * @arg @ref LL_TIM_CHANNEL_CH1
2812 * @arg @ref LL_TIM_CHANNEL_CH2
2813 * @arg @ref LL_TIM_CHANNEL_CH3
2814 * @arg @ref LL_TIM_CHANNEL_CH4
2815 * @arg @ref LL_TIM_CHANNEL_CH5
2816 * @arg @ref LL_TIM_CHANNEL_CH6
2817 * @retval State of bit (1 or 0).
2818 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2819 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2820 {
2821 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2822 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2823 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2824 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2825 }
2826
2827 /**
2828 * @brief Enable clearing the output channel on an external event.
2829 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2830 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2831 * or not a timer instance can clear the OCxREF signal on an external event.
2832 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2833 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2834 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2835 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2836 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2837 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2838 * @param TIMx Timer instance
2839 * @param Channel This parameter can be one of the following values:
2840 * @arg @ref LL_TIM_CHANNEL_CH1
2841 * @arg @ref LL_TIM_CHANNEL_CH2
2842 * @arg @ref LL_TIM_CHANNEL_CH3
2843 * @arg @ref LL_TIM_CHANNEL_CH4
2844 * @arg @ref LL_TIM_CHANNEL_CH5
2845 * @arg @ref LL_TIM_CHANNEL_CH6
2846 * @retval None
2847 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2848 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2849 {
2850 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2851 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2852 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2853 }
2854
2855 /**
2856 * @brief Disable clearing the output channel on an external event.
2857 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2858 * or not a timer instance can clear the OCxREF signal on an external event.
2859 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2860 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2861 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2862 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2863 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2864 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2865 * @param TIMx Timer instance
2866 * @param Channel This parameter can be one of the following values:
2867 * @arg @ref LL_TIM_CHANNEL_CH1
2868 * @arg @ref LL_TIM_CHANNEL_CH2
2869 * @arg @ref LL_TIM_CHANNEL_CH3
2870 * @arg @ref LL_TIM_CHANNEL_CH4
2871 * @arg @ref LL_TIM_CHANNEL_CH5
2872 * @arg @ref LL_TIM_CHANNEL_CH6
2873 * @retval None
2874 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2875 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2876 {
2877 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2878 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2879 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2880 }
2881
2882 /**
2883 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2884 * @note This function enables clearing the output channel on an external event.
2885 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2886 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2887 * or not a timer instance can clear the OCxREF signal on an external event.
2888 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2889 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2890 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2891 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2892 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2893 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2894 * @param TIMx Timer instance
2895 * @param Channel This parameter can be one of the following values:
2896 * @arg @ref LL_TIM_CHANNEL_CH1
2897 * @arg @ref LL_TIM_CHANNEL_CH2
2898 * @arg @ref LL_TIM_CHANNEL_CH3
2899 * @arg @ref LL_TIM_CHANNEL_CH4
2900 * @arg @ref LL_TIM_CHANNEL_CH5
2901 * @arg @ref LL_TIM_CHANNEL_CH6
2902 * @retval State of bit (1 or 0).
2903 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2904 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2905 {
2906 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2907 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2908 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2909 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2910 }
2911
2912 /**
2913 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2914 * the Ocx and OCxN signals).
2915 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2916 * dead-time insertion feature is supported by a timer instance.
2917 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2918 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2919 * @param TIMx Timer instance
2920 * @param DeadTime between Min_Data=0 and Max_Data=255
2921 * @retval None
2922 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2923 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2924 {
2925 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2926 }
2927
2928 /**
2929 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2930 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2931 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2932 * whether or not a timer instance supports a 32 bits counter.
2933 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2934 * output channel 1 is supported by a timer instance.
2935 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2936 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2937 * @param TIMx Timer instance
2938 * @param CompareValue between Min_Data=0 and Max_Data=65535
2939 * @retval None
2940 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2941 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2942 {
2943 WRITE_REG(TIMx->CCR1, CompareValue);
2944 }
2945
2946 /**
2947 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2948 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2949 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2950 * whether or not a timer instance supports a 32 bits counter.
2951 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2952 * output channel 2 is supported by a timer instance.
2953 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2954 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2955 * @param TIMx Timer instance
2956 * @param CompareValue between Min_Data=0 and Max_Data=65535
2957 * @retval None
2958 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2959 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2960 {
2961 WRITE_REG(TIMx->CCR2, CompareValue);
2962 }
2963
2964 /**
2965 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2966 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2967 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2968 * whether or not a timer instance supports a 32 bits counter.
2969 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2970 * output channel is supported by a timer instance.
2971 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2972 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2973 * @param TIMx Timer instance
2974 * @param CompareValue between Min_Data=0 and Max_Data=65535
2975 * @retval None
2976 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2977 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2978 {
2979 WRITE_REG(TIMx->CCR3, CompareValue);
2980 }
2981
2982 /**
2983 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2984 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2985 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2986 * whether or not a timer instance supports a 32 bits counter.
2987 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2988 * output channel 4 is supported by a timer instance.
2989 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2990 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2991 * @param TIMx Timer instance
2992 * @param CompareValue between Min_Data=0 and Max_Data=65535
2993 * @retval None
2994 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2995 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2996 {
2997 WRITE_REG(TIMx->CCR4, CompareValue);
2998 }
2999
3000 /**
3001 * @brief Set compare value for output channel 5 (TIMx_CCR5).
3002 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3003 * output channel 5 is supported by a timer instance.
3004 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3005 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3006 * @param TIMx Timer instance
3007 * @param CompareValue between Min_Data=0 and Max_Data=65535
3008 * @retval None
3009 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3010 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3011 {
3012 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3013 }
3014
3015 /**
3016 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3017 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3018 * output channel 6 is supported by a timer instance.
3019 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3020 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3021 * @param TIMx Timer instance
3022 * @param CompareValue between Min_Data=0 and Max_Data=65535
3023 * @retval None
3024 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3025 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3026 {
3027 WRITE_REG(TIMx->CCR6, CompareValue);
3028 }
3029
3030 /**
3031 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3032 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3033 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3034 * whether or not a timer instance supports a 32 bits counter.
3035 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3036 * output channel 1 is supported by a timer instance.
3037 * @note If dithering is activated, pay attention to the returned value interpretation.
3038 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3039 * @param TIMx Timer instance
3040 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3041 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)3042 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
3043 {
3044 return (uint32_t)(READ_REG(TIMx->CCR1));
3045 }
3046
3047 /**
3048 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3049 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3050 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3051 * whether or not a timer instance supports a 32 bits counter.
3052 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3053 * output channel 2 is supported by a timer instance.
3054 * @note If dithering is activated, pay attention to the returned value interpretation.
3055 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3056 * @param TIMx Timer instance
3057 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3058 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)3059 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
3060 {
3061 return (uint32_t)(READ_REG(TIMx->CCR2));
3062 }
3063
3064 /**
3065 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3066 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3067 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3068 * whether or not a timer instance supports a 32 bits counter.
3069 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3070 * output channel 3 is supported by a timer instance.
3071 * @note If dithering is activated, pay attention to the returned value interpretation.
3072 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3073 * @param TIMx Timer instance
3074 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3075 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)3076 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
3077 {
3078 return (uint32_t)(READ_REG(TIMx->CCR3));
3079 }
3080
3081 /**
3082 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3083 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3084 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3085 * whether or not a timer instance supports a 32 bits counter.
3086 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3087 * output channel 4 is supported by a timer instance.
3088 * @note If dithering is activated, pay attention to the returned value interpretation.
3089 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3090 * @param TIMx Timer instance
3091 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3092 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3093 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3094 {
3095 return (uint32_t)(READ_REG(TIMx->CCR4));
3096 }
3097
3098 /**
3099 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3100 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3101 * output channel 5 is supported by a timer instance.
3102 * @note If dithering is activated, pay attention to the returned value interpretation.
3103 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3104 * @param TIMx Timer instance
3105 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3106 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3107 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3108 {
3109 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3110 }
3111
3112 /**
3113 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3114 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3115 * output channel 6 is supported by a timer instance.
3116 * @note If dithering is activated, pay attention to the returned value interpretation.
3117 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3118 * @param TIMx Timer instance
3119 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3120 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3121 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3122 {
3123 return (uint32_t)(READ_REG(TIMx->CCR6));
3124 }
3125
3126 /**
3127 * @brief Select on which reference signal the OC5REF is combined to.
3128 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3129 * whether or not a timer instance supports the combined 3-phase PWM mode.
3130 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3131 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3132 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3133 * @param TIMx Timer instance
3134 * @param GroupCH5 This parameter can be a combination of the following values:
3135 * @arg @ref LL_TIM_GROUPCH5_NONE
3136 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3137 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3138 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3139 * @retval None
3140 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3141 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3142 {
3143 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3144 }
3145
3146 /**
3147 * @brief Set the pulse on compare pulse width prescaler.
3148 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3149 * whether or not the pulse on compare feature is supported by the timer
3150 * instance.
3151 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3152 * @param TIMx Timer instance
3153 * @param PulseWidthPrescaler This parameter can be one of the following values:
3154 * @arg @ref LL_TIM_PWPRSC_X1
3155 * @arg @ref LL_TIM_PWPRSC_X2
3156 * @arg @ref LL_TIM_PWPRSC_X4
3157 * @arg @ref LL_TIM_PWPRSC_X8
3158 * @arg @ref LL_TIM_PWPRSC_X16
3159 * @arg @ref LL_TIM_PWPRSC_X32
3160 * @arg @ref LL_TIM_PWPRSC_X64
3161 * @arg @ref LL_TIM_PWPRSC_X128
3162 * @retval None
3163 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3164 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3165 {
3166 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3167 }
3168
3169 /**
3170 * @brief Get the pulse on compare pulse width prescaler.
3171 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3172 * whether or not the pulse on compare feature is supported by the timer
3173 * instance.
3174 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3175 * @param TIMx Timer instance
3176 * @retval Returned value can be one of the following values:
3177 * @arg @ref LL_TIM_PWPRSC_X1
3178 * @arg @ref LL_TIM_PWPRSC_X2
3179 * @arg @ref LL_TIM_PWPRSC_X4
3180 * @arg @ref LL_TIM_PWPRSC_X8
3181 * @arg @ref LL_TIM_PWPRSC_X16
3182 * @arg @ref LL_TIM_PWPRSC_X32
3183 * @arg @ref LL_TIM_PWPRSC_X64
3184 * @arg @ref LL_TIM_PWPRSC_X128
3185 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3186 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3187 {
3188 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3189 }
3190
3191 /**
3192 * @brief Set the pulse on compare pulse width duration.
3193 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3194 * whether or not the pulse on compare feature is supported by the timer
3195 * instance.
3196 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3197 * @param TIMx Timer instance
3198 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3199 * @retval None
3200 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3201 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3202 {
3203 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3204 }
3205
3206 /**
3207 * @brief Get the pulse on compare pulse width duration.
3208 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3209 * whether or not the pulse on compare feature is supported by the timer
3210 * instance.
3211 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3212 * @param TIMx Timer instance
3213 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3214 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3215 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3216 {
3217 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3218 }
3219
3220 /**
3221 * @}
3222 */
3223
3224 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3225 * @{
3226 */
3227 /**
3228 * @brief Configure input channel.
3229 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3230 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3231 * CCMR1 IC1F LL_TIM_IC_Config\n
3232 * CCMR1 CC2S LL_TIM_IC_Config\n
3233 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3234 * CCMR1 IC2F LL_TIM_IC_Config\n
3235 * CCMR2 CC3S LL_TIM_IC_Config\n
3236 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3237 * CCMR2 IC3F LL_TIM_IC_Config\n
3238 * CCMR2 CC4S LL_TIM_IC_Config\n
3239 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3240 * CCMR2 IC4F LL_TIM_IC_Config\n
3241 * CCER CC1P LL_TIM_IC_Config\n
3242 * CCER CC1NP LL_TIM_IC_Config\n
3243 * CCER CC2P LL_TIM_IC_Config\n
3244 * CCER CC2NP LL_TIM_IC_Config\n
3245 * CCER CC3P LL_TIM_IC_Config\n
3246 * CCER CC3NP LL_TIM_IC_Config\n
3247 * CCER CC4P LL_TIM_IC_Config\n
3248 * CCER CC4NP LL_TIM_IC_Config
3249 * @param TIMx Timer instance
3250 * @param Channel This parameter can be one of the following values:
3251 * @arg @ref LL_TIM_CHANNEL_CH1
3252 * @arg @ref LL_TIM_CHANNEL_CH2
3253 * @arg @ref LL_TIM_CHANNEL_CH3
3254 * @arg @ref LL_TIM_CHANNEL_CH4
3255 * @param Configuration This parameter must be a combination of all the following values:
3256 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3257 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3258 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3259 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3260 * @retval None
3261 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3262 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3263 {
3264 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3265 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3266 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3267 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3268 << SHIFT_TAB_ICxx[iChannel]);
3269 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3270 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3271 }
3272
3273 /**
3274 * @brief Set the active input.
3275 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3276 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3277 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3278 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3279 * @param TIMx Timer instance
3280 * @param Channel This parameter can be one of the following values:
3281 * @arg @ref LL_TIM_CHANNEL_CH1
3282 * @arg @ref LL_TIM_CHANNEL_CH2
3283 * @arg @ref LL_TIM_CHANNEL_CH3
3284 * @arg @ref LL_TIM_CHANNEL_CH4
3285 * @param ICActiveInput This parameter can be one of the following values:
3286 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3287 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3288 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3289 * @retval None
3290 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3291 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3292 {
3293 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3294 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3295 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3296 }
3297
3298 /**
3299 * @brief Get the current active input.
3300 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3301 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3302 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3303 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3304 * @param TIMx Timer instance
3305 * @param Channel This parameter can be one of the following values:
3306 * @arg @ref LL_TIM_CHANNEL_CH1
3307 * @arg @ref LL_TIM_CHANNEL_CH2
3308 * @arg @ref LL_TIM_CHANNEL_CH3
3309 * @arg @ref LL_TIM_CHANNEL_CH4
3310 * @retval Returned value can be one of the following values:
3311 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3312 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3313 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3314 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3315 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3316 {
3317 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3318 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3319 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3320 }
3321
3322 /**
3323 * @brief Set the prescaler of input channel.
3324 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3325 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3326 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3327 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3328 * @param TIMx Timer instance
3329 * @param Channel This parameter can be one of the following values:
3330 * @arg @ref LL_TIM_CHANNEL_CH1
3331 * @arg @ref LL_TIM_CHANNEL_CH2
3332 * @arg @ref LL_TIM_CHANNEL_CH3
3333 * @arg @ref LL_TIM_CHANNEL_CH4
3334 * @param ICPrescaler This parameter can be one of the following values:
3335 * @arg @ref LL_TIM_ICPSC_DIV1
3336 * @arg @ref LL_TIM_ICPSC_DIV2
3337 * @arg @ref LL_TIM_ICPSC_DIV4
3338 * @arg @ref LL_TIM_ICPSC_DIV8
3339 * @retval None
3340 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3341 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3342 {
3343 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3344 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3345 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3346 }
3347
3348 /**
3349 * @brief Get the current prescaler value acting on an input channel.
3350 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3351 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3352 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3353 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3354 * @param TIMx Timer instance
3355 * @param Channel This parameter can be one of the following values:
3356 * @arg @ref LL_TIM_CHANNEL_CH1
3357 * @arg @ref LL_TIM_CHANNEL_CH2
3358 * @arg @ref LL_TIM_CHANNEL_CH3
3359 * @arg @ref LL_TIM_CHANNEL_CH4
3360 * @retval Returned value can be one of the following values:
3361 * @arg @ref LL_TIM_ICPSC_DIV1
3362 * @arg @ref LL_TIM_ICPSC_DIV2
3363 * @arg @ref LL_TIM_ICPSC_DIV4
3364 * @arg @ref LL_TIM_ICPSC_DIV8
3365 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3366 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3367 {
3368 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3369 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3370 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3371 }
3372
3373 /**
3374 * @brief Set the input filter duration.
3375 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3376 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3377 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3378 * CCMR2 IC4F LL_TIM_IC_SetFilter
3379 * @param TIMx Timer instance
3380 * @param Channel This parameter can be one of the following values:
3381 * @arg @ref LL_TIM_CHANNEL_CH1
3382 * @arg @ref LL_TIM_CHANNEL_CH2
3383 * @arg @ref LL_TIM_CHANNEL_CH3
3384 * @arg @ref LL_TIM_CHANNEL_CH4
3385 * @param ICFilter This parameter can be one of the following values:
3386 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3387 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3388 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3389 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3390 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3391 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3392 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3393 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3394 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3395 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3396 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3397 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3398 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3399 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3400 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3401 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3402 * @retval None
3403 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3404 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3405 {
3406 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3407 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3408 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3409 }
3410
3411 /**
3412 * @brief Get the input filter duration.
3413 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3414 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3415 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3416 * CCMR2 IC4F LL_TIM_IC_GetFilter
3417 * @param TIMx Timer instance
3418 * @param Channel This parameter can be one of the following values:
3419 * @arg @ref LL_TIM_CHANNEL_CH1
3420 * @arg @ref LL_TIM_CHANNEL_CH2
3421 * @arg @ref LL_TIM_CHANNEL_CH3
3422 * @arg @ref LL_TIM_CHANNEL_CH4
3423 * @retval Returned value can be one of the following values:
3424 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3425 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3426 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3427 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3428 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3429 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3430 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3431 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3432 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3433 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3434 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3435 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3436 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3437 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3438 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3439 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3440 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3441 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3442 {
3443 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3444 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3445 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3446 }
3447
3448 /**
3449 * @brief Set the input channel polarity.
3450 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3451 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3452 * CCER CC2P LL_TIM_IC_SetPolarity\n
3453 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3454 * CCER CC3P LL_TIM_IC_SetPolarity\n
3455 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3456 * CCER CC4P LL_TIM_IC_SetPolarity\n
3457 * CCER CC4NP LL_TIM_IC_SetPolarity
3458 * @param TIMx Timer instance
3459 * @param Channel This parameter can be one of the following values:
3460 * @arg @ref LL_TIM_CHANNEL_CH1
3461 * @arg @ref LL_TIM_CHANNEL_CH2
3462 * @arg @ref LL_TIM_CHANNEL_CH3
3463 * @arg @ref LL_TIM_CHANNEL_CH4
3464 * @param ICPolarity This parameter can be one of the following values:
3465 * @arg @ref LL_TIM_IC_POLARITY_RISING
3466 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3467 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3468 * @retval None
3469 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3470 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3471 {
3472 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3473 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3474 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3475 }
3476
3477 /**
3478 * @brief Get the current input channel polarity.
3479 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3480 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3481 * CCER CC2P LL_TIM_IC_GetPolarity\n
3482 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3483 * CCER CC3P LL_TIM_IC_GetPolarity\n
3484 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3485 * CCER CC4P LL_TIM_IC_GetPolarity\n
3486 * CCER CC4NP LL_TIM_IC_GetPolarity
3487 * @param TIMx Timer instance
3488 * @param Channel This parameter can be one of the following values:
3489 * @arg @ref LL_TIM_CHANNEL_CH1
3490 * @arg @ref LL_TIM_CHANNEL_CH2
3491 * @arg @ref LL_TIM_CHANNEL_CH3
3492 * @arg @ref LL_TIM_CHANNEL_CH4
3493 * @retval Returned value can be one of the following values:
3494 * @arg @ref LL_TIM_IC_POLARITY_RISING
3495 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3496 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3497 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3498 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3499 {
3500 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3501 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3502 SHIFT_TAB_CCxP[iChannel]);
3503 }
3504
3505 /**
3506 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3507 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3508 * a timer instance provides an XOR input.
3509 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3510 * @param TIMx Timer instance
3511 * @retval None
3512 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3513 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3514 {
3515 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3516 }
3517
3518 /**
3519 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3520 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3521 * a timer instance provides an XOR input.
3522 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3523 * @param TIMx Timer instance
3524 * @retval None
3525 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3526 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3527 {
3528 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3529 }
3530
3531 /**
3532 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3533 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3534 * a timer instance provides an XOR input.
3535 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3536 * @param TIMx Timer instance
3537 * @retval State of bit (1 or 0).
3538 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3539 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3540 {
3541 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3542 }
3543
3544 /**
3545 * @brief Get captured value for input channel 1.
3546 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3547 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3548 * whether or not a timer instance supports a 32 bits counter.
3549 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3550 * input channel 1 is supported by a timer instance.
3551 * @note If dithering is activated, pay attention to the returned value interpretation.
3552 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3553 * @param TIMx Timer instance
3554 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3555 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3556 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3557 {
3558 return (uint32_t)(READ_REG(TIMx->CCR1));
3559 }
3560
3561 /**
3562 * @brief Get captured value for input channel 2.
3563 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3564 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3565 * whether or not a timer instance supports a 32 bits counter.
3566 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3567 * input channel 2 is supported by a timer instance.
3568 * @note If dithering is activated, pay attention to the returned value interpretation.
3569 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3570 * @param TIMx Timer instance
3571 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3572 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3573 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3574 {
3575 return (uint32_t)(READ_REG(TIMx->CCR2));
3576 }
3577
3578 /**
3579 * @brief Get captured value for input channel 3.
3580 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3581 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3582 * whether or not a timer instance supports a 32 bits counter.
3583 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3584 * input channel 3 is supported by a timer instance.
3585 * @note If dithering is activated, pay attention to the returned value interpretation.
3586 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3587 * @param TIMx Timer instance
3588 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3589 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3590 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3591 {
3592 return (uint32_t)(READ_REG(TIMx->CCR3));
3593 }
3594
3595 /**
3596 * @brief Get captured value for input channel 4.
3597 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3598 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3599 * whether or not a timer instance supports a 32 bits counter.
3600 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3601 * input channel 4 is supported by a timer instance.
3602 * @note If dithering is activated, pay attention to the returned value interpretation.
3603 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3604 * @param TIMx Timer instance
3605 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3606 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3607 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3608 {
3609 return (uint32_t)(READ_REG(TIMx->CCR4));
3610 }
3611
3612 /**
3613 * @}
3614 */
3615
3616 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3617 * @{
3618 */
3619 /**
3620 * @brief Enable external clock mode 2.
3621 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3622 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3623 * whether or not a timer instance supports external clock mode2.
3624 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3625 * @param TIMx Timer instance
3626 * @retval None
3627 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3628 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3629 {
3630 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3631 }
3632
3633 /**
3634 * @brief Disable external clock mode 2.
3635 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3636 * whether or not a timer instance supports external clock mode2.
3637 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3638 * @param TIMx Timer instance
3639 * @retval None
3640 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3641 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3642 {
3643 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3644 }
3645
3646 /**
3647 * @brief Indicate whether external clock mode 2 is enabled.
3648 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3649 * whether or not a timer instance supports external clock mode2.
3650 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3651 * @param TIMx Timer instance
3652 * @retval State of bit (1 or 0).
3653 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3654 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3655 {
3656 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3657 }
3658
3659 /**
3660 * @brief Set the clock source of the counter clock.
3661 * @note when selected clock source is external clock mode 1, the timer input
3662 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3663 * function. This timer input must be configured by calling
3664 * the @ref LL_TIM_IC_Config() function.
3665 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3666 * whether or not a timer instance supports external clock mode1.
3667 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3668 * whether or not a timer instance supports external clock mode2.
3669 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3670 * SMCR ECE LL_TIM_SetClockSource
3671 * @param TIMx Timer instance
3672 * @param ClockSource This parameter can be one of the following values:
3673 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3674 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3675 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3676 * @retval None
3677 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3678 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3679 {
3680 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3681 }
3682
3683 /**
3684 * @brief Set the encoder interface mode.
3685 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3686 * whether or not a timer instance supports the encoder mode.
3687 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3688 * @param TIMx Timer instance
3689 * @param EncoderMode This parameter can be one of the following values:
3690 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3691 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3692 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3693 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3694 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3695 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3696 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3697 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3698 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3699 * @retval None
3700 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3701 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3702 {
3703 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3704 }
3705
3706 /**
3707 * @}
3708 */
3709
3710 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3711 * @{
3712 */
3713 /**
3714 * @brief Set the trigger output (TRGO) used for timer synchronization .
3715 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3716 * whether or not a timer instance can operate as a master timer.
3717 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3718 * @param TIMx Timer instance
3719 * @param TimerSynchronization This parameter can be one of the following values:
3720 * @arg @ref LL_TIM_TRGO_RESET
3721 * @arg @ref LL_TIM_TRGO_ENABLE
3722 * @arg @ref LL_TIM_TRGO_UPDATE
3723 * @arg @ref LL_TIM_TRGO_CC1IF
3724 * @arg @ref LL_TIM_TRGO_OC1REF
3725 * @arg @ref LL_TIM_TRGO_OC2REF
3726 * @arg @ref LL_TIM_TRGO_OC3REF
3727 * @arg @ref LL_TIM_TRGO_OC4REF
3728 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3729 * @retval None
3730 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3731 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3732 {
3733 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3734 }
3735
3736 /**
3737 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3738 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3739 * whether or not a timer instance can be used for ADC synchronization.
3740 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3741 * @param TIMx Timer Instance
3742 * @param ADCSynchronization This parameter can be one of the following values:
3743 * @arg @ref LL_TIM_TRGO2_RESET
3744 * @arg @ref LL_TIM_TRGO2_ENABLE
3745 * @arg @ref LL_TIM_TRGO2_UPDATE
3746 * @arg @ref LL_TIM_TRGO2_CC1F
3747 * @arg @ref LL_TIM_TRGO2_OC1
3748 * @arg @ref LL_TIM_TRGO2_OC2
3749 * @arg @ref LL_TIM_TRGO2_OC3
3750 * @arg @ref LL_TIM_TRGO2_OC4
3751 * @arg @ref LL_TIM_TRGO2_OC5
3752 * @arg @ref LL_TIM_TRGO2_OC6
3753 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3754 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3755 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3756 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3757 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3758 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3759 * @retval None
3760 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3761 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3762 {
3763 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3764 }
3765
3766 /**
3767 * @brief Set the synchronization mode of a slave timer.
3768 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3769 * a timer instance can operate as a slave timer.
3770 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3771 * @param TIMx Timer instance
3772 * @param SlaveMode This parameter can be one of the following values:
3773 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3774 * @arg @ref LL_TIM_SLAVEMODE_RESET
3775 * @arg @ref LL_TIM_SLAVEMODE_GATED
3776 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3777 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3778 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3779 * @retval None
3780 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3781 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3782 {
3783 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3784 }
3785
3786 /**
3787 * @brief Set the selects the trigger input to be used to synchronize the counter.
3788 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3789 * a timer instance can operate as a slave timer.
3790 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3791 * @param TIMx Timer instance
3792 * @param TriggerInput This parameter can be one of the following values:
3793 * @arg @ref LL_TIM_TS_ITR0
3794 * @arg @ref LL_TIM_TS_ITR1
3795 * @arg @ref LL_TIM_TS_ITR2
3796 * @arg @ref LL_TIM_TS_ITR3
3797 * @arg @ref LL_TIM_TS_ITR4
3798 * @arg @ref LL_TIM_TS_ITR5
3799 * @arg @ref LL_TIM_TS_ITR6
3800 * @arg @ref LL_TIM_TS_ITR7
3801 * @arg @ref LL_TIM_TS_ITR8
3802 * @arg @ref LL_TIM_TS_ITR9
3803 * @arg @ref LL_TIM_TS_ITR10
3804 * @arg @ref LL_TIM_TS_ITR11
3805 * @arg @ref LL_TIM_TS_ITR12
3806 * @arg @ref LL_TIM_TS_ITR13
3807 * @arg @ref LL_TIM_TS_TI1F_ED
3808 * @arg @ref LL_TIM_TS_TI1FP1
3809 * @arg @ref LL_TIM_TS_TI2FP2
3810 * @arg @ref LL_TIM_TS_ETRF
3811 * @retval None
3812 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3813 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3814 {
3815 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3816 }
3817
3818 /**
3819 * @brief Enable the Master/Slave mode.
3820 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3821 * a timer instance can operate as a slave timer.
3822 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3823 * @param TIMx Timer instance
3824 * @retval None
3825 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3826 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3827 {
3828 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3829 }
3830
3831 /**
3832 * @brief Disable the Master/Slave mode.
3833 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3834 * a timer instance can operate as a slave timer.
3835 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3836 * @param TIMx Timer instance
3837 * @retval None
3838 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3839 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3840 {
3841 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3842 }
3843
3844 /**
3845 * @brief Indicates whether the Master/Slave mode is enabled.
3846 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3847 * a timer instance can operate as a slave timer.
3848 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3849 * @param TIMx Timer instance
3850 * @retval State of bit (1 or 0).
3851 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3852 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3853 {
3854 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3855 }
3856
3857 /**
3858 * @brief Configure the external trigger (ETR) input.
3859 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3860 * a timer instance provides an external trigger input.
3861 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3862 * SMCR ETPS LL_TIM_ConfigETR\n
3863 * SMCR ETF LL_TIM_ConfigETR
3864 * @param TIMx Timer instance
3865 * @param ETRPolarity This parameter can be one of the following values:
3866 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3867 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3868 * @param ETRPrescaler This parameter can be one of the following values:
3869 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3870 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3871 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3872 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3873 * @param ETRFilter This parameter can be one of the following values:
3874 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3875 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3876 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3877 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3878 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3879 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3880 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3881 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3882 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3883 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3884 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3885 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3886 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3887 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3888 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3889 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3890 * @retval None
3891 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3892 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3893 uint32_t ETRFilter)
3894 {
3895 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3896 }
3897
3898 /**
3899 * @brief Select the external trigger (ETR) input source.
3900 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3901 * not a timer instance supports ETR source selection.
3902 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3903 * @param TIMx Timer instance
3904 * @param ETRSource This parameter can be one of the following values:
3905 *
3906 * For TIM1, the parameter is one of the following values:
3907 *
3908 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3909 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
3910 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
3911 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
3912 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD1
3913 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD2
3914 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC2_AWD3
3915 *
3916 * For TIM2, the parameter is one of the following values:
3917 *
3918 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3919 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_HSYNC
3920 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LCD_HSYNC
3921 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA
3922 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB
3923 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GFXTIM_TE
3924 * @arg @ref LL_TIM_TIM2_ETRSOURCE_DCMIPP_VSYNC
3925 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LCD_VSYNC
3926 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
3927 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
3928 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR
3929 * @arg @ref LL_TIM_TIM2_ETRSOURCE_USB1_SOF
3930 * @arg @ref LL_TIM_TIM2_ETRSOURCE_USB2_SOF
3931 *
3932 * For TIM3, the parameter is one of the following values:
3933 *
3934 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3935 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_HSYNC
3936 * @arg @ref LL_TIM_TIM3_ETRSOURCE_LCD_HSYNC
3937 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GFXTIM_TE
3938 * @arg @ref LL_TIM_TIM3_ETRSOURCE_DCMIPP_VSYNC
3939 * @arg @ref LL_TIM_TIM3_ETRSOURCE_LCD_VSYNC
3940 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
3941 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
3942 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR
3943 *
3944 * For TIM4, the parameter is one of the following values:
3945 *
3946 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
3947 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_HSYNC
3948 * @arg @ref LL_TIM_TIM4_ETRSOURCE_LCD_HSYNC
3949 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GFXTIM_TE
3950 * @arg @ref LL_TIM_TIM4_ETRSOURCE_DCMIPP_VSYNC
3951 * @arg @ref LL_TIM_TIM4_ETRSOURCE_LCD_VSYNC
3952 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
3953 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
3954 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
3955 *
3956 * For TIM5, the parameter is one of the following values:
3957 *
3958 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
3959 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
3960 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
3961 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_HSYNC
3962 * @arg @ref LL_TIM_TIM5_ETRSOURCE_LCD_HSYNC
3963 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GFXTIM_TE
3964 * @arg @ref LL_TIM_TIM5_ETRSOURCE_DCMIPP_VSYNC
3965 * @arg @ref LL_TIM_TIM5_ETRSOURCE_LCD_VSYNC
3966 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
3967 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
3968 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
3969 * @arg @ref LL_TIM_TIM5_ETRSOURCE_USB1_SOF
3970 * @arg @ref LL_TIM_TIM5_ETRSOURCE_USB2_SOF
3971 *
3972 * For TIM8, the parameter is one of the following values:
3973 *
3974 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
3975 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
3976 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
3977 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
3978 * @retval None
3979 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3980 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3981 {
3982 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3983 }
3984
3985 /**
3986 * @brief Enable SMS preload.
3987 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3988 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3989 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
3990 * @param TIMx Timer instance
3991 * @retval None
3992 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)3993 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
3994 {
3995 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3996 }
3997
3998 /**
3999 * @brief Disable SMS preload.
4000 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4001 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4002 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
4003 * @param TIMx Timer instance
4004 * @retval None
4005 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)4006 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
4007 {
4008 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4009 }
4010
4011 /**
4012 * @brief Indicate whether SMS preload is enabled.
4013 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4014 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4015 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
4016 * @param TIMx Timer instance
4017 * @retval State of bit (1 or 0).
4018 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)4019 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
4020 {
4021 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4022 }
4023
4024 /**
4025 * @brief Set the preload source of SMS.
4026 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4027 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4028 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4029 * @param TIMx Timer instance
4030 * @param PreloadSource This parameter can be one of the following values:
4031 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4032 * @arg @ref LL_TIM_SMSPS_INDEX
4033 * @retval None
4034 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4035 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4036 {
4037 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4038 }
4039
4040 /**
4041 * @brief Get the preload source of SMS.
4042 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4043 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4044 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4045 * @param TIMx Timer instance
4046 * @retval Returned value can be one of the following values:
4047 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4048 * @arg @ref LL_TIM_SMSPS_INDEX
4049 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)4050 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
4051 {
4052 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4053 }
4054
4055
4056 /**
4057 * @brief Enable ADC synchronization.
4058 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
4059 * whether or not a timer instance supports ADC synchronization.
4060 * @rmtoll CR2 ADSYNC LL_TIM_EnableADCSynchronization
4061 * @param TIMx Timer instance
4062 * @retval None
4063 */
LL_TIM_EnableADCSynchronization(TIM_TypeDef * TIMx)4064 __STATIC_INLINE void LL_TIM_EnableADCSynchronization(TIM_TypeDef *TIMx)
4065 {
4066 SET_BIT(TIMx->CR2, TIM_CR2_ADSYNC);
4067 }
4068
4069 /**
4070 * @brief Enable ADC synchronization.
4071 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
4072 * whether or not a timer instance supports ADC synchronization.
4073 * @rmtoll CR2 ADSYNC LL_TIM_DisableADCSynchronization
4074 * @param TIMx Timer instance
4075 * @retval None
4076 */
LL_TIM_DisableADCSynchronization(TIM_TypeDef * TIMx)4077 __STATIC_INLINE void LL_TIM_DisableADCSynchronization(TIM_TypeDef *TIMx)
4078 {
4079 CLEAR_BIT(TIMx->CR2, TIM_CR2_ADSYNC);
4080 }
4081
4082 /**
4083 * @brief Indicate whether ADC sycnhronization is enabled.
4084 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
4085 * whether or not a timer instance supports ADC synchronization.
4086 * @rmtoll CR2 ADSYNC LL_TIM_IsEnabledADCSynchronization
4087 * @param TIMx Timer instance
4088 * @retval State of bit (1 or 0).
4089 */
LL_TIM_IsEnabledADCSynchronization(const TIM_TypeDef * TIMx)4090 __STATIC_INLINE uint32_t LL_TIM_IsEnabledADCSynchronization(const TIM_TypeDef *TIMx)
4091 {
4092 return ((READ_BIT(TIMx->CR2, TIM_CR2_ADSYNC) == (TIM_CR2_ADSYNC)) ? 1UL : 0UL);
4093 }
4094
4095 /**
4096 * @}
4097 */
4098
4099 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4100 * @{
4101 */
4102 /**
4103 * @brief Enable the break function.
4104 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4105 * a timer instance provides a break input.
4106 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4107 * @param TIMx Timer instance
4108 * @retval None
4109 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4110 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4111 {
4112 __IO uint32_t tmpreg;
4113 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4114 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4115 tmpreg = READ_REG(TIMx->BDTR);
4116 (void)(tmpreg);
4117 }
4118
4119 /**
4120 * @brief Disable the break function.
4121 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4122 * @param TIMx Timer instance
4123 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4124 * a timer instance provides a break input.
4125 * @retval None
4126 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4127 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4128 {
4129 __IO uint32_t tmpreg;
4130 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4131 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4132 tmpreg = READ_REG(TIMx->BDTR);
4133 (void)(tmpreg);
4134 }
4135
4136 /**
4137 * @brief Configure the break input.
4138 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4139 * a timer instance provides a break input.
4140 * @note Bidirectional mode is only supported by advanced timer instances.
4141 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4142 * a timer instance is an advanced-control timer.
4143 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4144 * in input mode and in open drain output mode. Any active Break event will
4145 * assert a low logic level on the Break input to indicate an internal break
4146 * event to external devices.
4147 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4148 * LL_TIM_BREAK_AFMODE_INPUT.
4149 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4150 * BDTR BKF LL_TIM_ConfigBRK\n
4151 * BDTR BKBID LL_TIM_ConfigBRK
4152 * @param TIMx Timer instance
4153 * @param BreakPolarity This parameter can be one of the following values:
4154 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4155 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4156 * @param BreakFilter This parameter can be one of the following values:
4157 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4158 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4159 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4160 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4161 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4162 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4163 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4164 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4165 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4166 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4167 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4168 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4169 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4170 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4171 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4172 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4173 * @param BreakAFMode This parameter can be one of the following values:
4174 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4175 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4176 * @retval None
4177 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4178 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4179 uint32_t BreakAFMode)
4180 {
4181 __IO uint32_t tmpreg;
4182 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4183 /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
4184 tmpreg = READ_REG(TIMx->BDTR);
4185 (void)(tmpreg);
4186 }
4187
4188 /**
4189 * @brief Disarm the break input (when it operates in bidirectional mode).
4190 * @note The break input can be disarmed only when it is configured in
4191 * bidirectional mode and when when MOE is reset.
4192 * @note Purpose is to be able to have the input voltage back to high-state,
4193 * whatever the time constant on the output .
4194 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4195 * @param TIMx Timer instance
4196 * @retval None
4197 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4198 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4199 {
4200 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4201 }
4202
4203 /**
4204 * @brief Enable the break 2 function.
4205 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4206 * a timer instance provides a second break input.
4207 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4208 * @param TIMx Timer instance
4209 * @retval None
4210 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4211 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4212 {
4213 __IO uint32_t tmpreg;
4214 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4215 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4216 tmpreg = READ_REG(TIMx->BDTR);
4217 (void)(tmpreg);
4218 }
4219
4220 /**
4221 * @brief Disable the break 2 function.
4222 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4223 * a timer instance provides a second break input.
4224 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4225 * @param TIMx Timer instance
4226 * @retval None
4227 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4228 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4229 {
4230 __IO uint32_t tmpreg;
4231 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4232 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
4233 tmpreg = READ_REG(TIMx->BDTR);
4234 (void)(tmpreg);
4235 }
4236
4237 /**
4238 * @brief Configure the break 2 input.
4239 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4240 * a timer instance provides a second break input.
4241 * @note Bidirectional mode is only supported by advanced timer instances.
4242 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4243 * a timer instance is an advanced-control timer.
4244 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4245 * in input mode and in open drain output mode. Any active Break event will
4246 * assert a low logic level on the Break 2 input to indicate an internal break
4247 * event to external devices.
4248 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4249 * LL_TIM_BREAK2_AFMODE_INPUT.
4250 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4251 * BDTR BK2F LL_TIM_ConfigBRK2\n
4252 * BDTR BK2BID LL_TIM_ConfigBRK2
4253 * @param TIMx Timer instance
4254 * @param Break2Polarity This parameter can be one of the following values:
4255 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4256 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4257 * @param Break2Filter This parameter can be one of the following values:
4258 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4259 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4260 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4261 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4262 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4263 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4264 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4265 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4266 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4267 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4268 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4269 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4270 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4271 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4272 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4273 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4274 * @param Break2AFMode This parameter can be one of the following values:
4275 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4276 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4277 * @retval None
4278 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4279 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4280 uint32_t Break2AFMode)
4281 {
4282 __IO uint32_t tmpreg;
4283 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4284 /* Note: Any write operation to BK2P bit takes a delay of 1 APB clock cycle to become effective. */
4285 tmpreg = READ_REG(TIMx->BDTR);
4286 (void)(tmpreg);
4287 }
4288
4289 /**
4290 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4291 * @note The break 2 input can be disarmed only when it is configured in
4292 * bidirectional mode and when when MOE is reset.
4293 * @note Purpose is to be able to have the input voltage back to high-state,
4294 * whatever the time constant on the output.
4295 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4296 * @param TIMx Timer instance
4297 * @retval None
4298 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4299 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4300 {
4301 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4302 }
4303
4304 /**
4305 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4306 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4307 * a timer instance provides a break input.
4308 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4309 * BDTR OSSR LL_TIM_SetOffStates
4310 * @param TIMx Timer instance
4311 * @param OffStateIdle This parameter can be one of the following values:
4312 * @arg @ref LL_TIM_OSSI_DISABLE
4313 * @arg @ref LL_TIM_OSSI_ENABLE
4314 * @param OffStateRun This parameter can be one of the following values:
4315 * @arg @ref LL_TIM_OSSR_DISABLE
4316 * @arg @ref LL_TIM_OSSR_ENABLE
4317 * @retval None
4318 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4319 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4320 {
4321 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4322 }
4323
4324 /**
4325 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4326 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4327 * a timer instance provides a break input.
4328 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4329 * @param TIMx Timer instance
4330 * @retval None
4331 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4332 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4333 {
4334 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4335 }
4336
4337 /**
4338 * @brief Disable automatic output (MOE can be set only by software).
4339 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4340 * a timer instance provides a break input.
4341 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4342 * @param TIMx Timer instance
4343 * @retval None
4344 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4345 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4346 {
4347 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4348 }
4349
4350 /**
4351 * @brief Indicate whether automatic output is enabled.
4352 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4353 * a timer instance provides a break input.
4354 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4355 * @param TIMx Timer instance
4356 * @retval State of bit (1 or 0).
4357 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4358 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4359 {
4360 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4361 }
4362
4363 /**
4364 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4365 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4366 * software and is reset in case of break or break2 event
4367 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4368 * a timer instance provides a break input.
4369 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4370 * @param TIMx Timer instance
4371 * @retval None
4372 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4373 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4374 {
4375 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4376 }
4377
4378 /**
4379 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4380 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4381 * software and is reset in case of break or break2 event.
4382 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4383 * a timer instance provides a break input.
4384 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4385 * @param TIMx Timer instance
4386 * @retval None
4387 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4388 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4389 {
4390 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4391 }
4392
4393 /**
4394 * @brief Indicates whether outputs are enabled.
4395 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4396 * a timer instance provides a break input.
4397 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4398 * @param TIMx Timer instance
4399 * @retval State of bit (1 or 0).
4400 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4401 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4402 {
4403 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4404 }
4405
4406 /**
4407 * @brief Enable the signals connected to the designated timer break input.
4408 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4409 * or not a timer instance allows for break input selection.
4410 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4411 * AF1 BKCMP8E LL_TIM_EnableBreakInputSource\n
4412 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4413 * AF2 BK2CMP8E LL_TIM_EnableBreakInputSource\n
4414 * @param TIMx Timer instance
4415 * @param BreakInput This parameter can be one of the following values:
4416 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4417 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4418 * @param Source This parameter can be one of the following values:
4419 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4420 * @arg @ref LL_TIM_BKIN_SOURCE_MDF1
4421 * @retval None
4422 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4423 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4424 {
4425 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4426 SET_BIT(*pReg, Source);
4427 }
4428
4429 /**
4430 * @brief Disable the signals connected to the designated timer break input.
4431 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4432 * or not a timer instance allows for break input selection.
4433 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4434 * AF1 BKCMP8E LL_TIM_DisableBreakInputSource\n
4435 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4436 * AF2 BK2CMP8E LL_TIM_DisableBreakInputSource\n
4437 * @param TIMx Timer instance
4438 * @param BreakInput This parameter can be one of the following values:
4439 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4440 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4441 * @param Source This parameter can be one of the following values:
4442 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4443 * @arg @ref LL_TIM_BKIN_SOURCE_MDF1
4444 * @retval None
4445 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4446 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4447 {
4448 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4449 CLEAR_BIT(*pReg, Source);
4450 }
4451
4452 /**
4453 * @brief Set the polarity of the break signal for the timer break input.
4454 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4455 * or not a timer instance allows for break input selection.
4456 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4457 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity
4458 * @param TIMx Timer instance
4459 * @param BreakInput This parameter can be one of the following values:
4460 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4461 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4462 * @param Source This parameter can be one of the following values:
4463 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4464 * @param Polarity This parameter can be one of the following values:
4465 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4466 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4467 * @retval None
4468 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4469 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4470 uint32_t Polarity)
4471 {
4472 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4473 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4474 }
4475 /**
4476 * @brief Enable asymmetrical deadtime.
4477 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4478 * a timer instance provides asymmetrical deadtime.
4479 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4480 * @param TIMx Timer instance
4481 * @retval None
4482 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4483 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4484 {
4485 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4486 }
4487
4488 /**
4489 * @brief Disable asymmetrical dead-time.
4490 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4491 * a timer instance provides asymmetrical deadtime.
4492 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4493 * @param TIMx Timer instance
4494 * @retval None
4495 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4496 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4497 {
4498 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4499 }
4500
4501 /**
4502 * @brief Indicates whether asymmetrical deadtime is activated.
4503 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4504 * a timer instance provides asymmetrical deadtime.
4505 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4506 * @param TIMx Timer instance
4507 * @retval State of bit (1 or 0).
4508 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4509 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4510 {
4511 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4512 }
4513
4514 /**
4515 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4516 * rising edge of OCxN signals).
4517 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4518 * asymmetrical dead-time insertion feature is supported by a timer instance.
4519 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4520 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4521 * (LOCK bits in TIMx_BDTR register).
4522 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4523 * @param TIMx Timer instance
4524 * @param DeadTime between Min_Data=0 and Max_Data=255
4525 * @retval None
4526 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4527 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4528 {
4529 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4530 }
4531
4532 /**
4533 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4534 * the rising edge of OCxN signals).
4535 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4536 * asymmetrical dead-time insertion feature is supported by a timer instance.
4537 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4538 * (LOCK bits in TIMx_BDTR register).
4539 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4540 * @param TIMx Timer instance
4541 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4542 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4543 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4544 {
4545 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4546 }
4547
4548 /**
4549 * @brief Enable deadtime preload.
4550 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4551 * a timer instance provides deadtime preload.
4552 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4553 * @param TIMx Timer instance
4554 * @retval None
4555 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4556 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4557 {
4558 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4559 }
4560
4561 /**
4562 * @brief Disable dead-time preload.
4563 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4564 * a timer instance provides deadtime preload.
4565 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4566 * @param TIMx Timer instance
4567 * @retval None
4568 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4569 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4570 {
4571 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4572 }
4573
4574 /**
4575 * @brief Indicates whether deadtime preload is activated.
4576 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4577 * a timer instance provides deadtime preload.
4578 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4579 * @param TIMx Timer instance
4580 * @retval State of bit (1 or 0).
4581 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4582 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4583 {
4584 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4585 }
4586
4587 /**
4588 * @}
4589 */
4590
4591 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4592 * @{
4593 */
4594 /**
4595 * @brief Configures the timer DMA burst feature.
4596 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4597 * not a timer instance supports the DMA burst mode.
4598 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4599 * DCR DBA LL_TIM_ConfigDMABurst
4600 * @param TIMx Timer instance
4601 * @param DMABurstBaseAddress This parameter can be one of the following values:
4602 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4603 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4604 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4605 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4606 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4607 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4608 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4609 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4610 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4611 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4612 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4613 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4614 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4615 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4616 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4617 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4618 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4619 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4620 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4621 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4622 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4623 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4624 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4625 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4626 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4627 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4628 * @param DMABurstLength This parameter can be one of the following values:
4629 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4630 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4631 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4632 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4633 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4634 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4635 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4636 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4637 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4638 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4639 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4640 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4641 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4642 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4643 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4644 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4645 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4646 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4647 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4648 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4649 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4650 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4651 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4652 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4653 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4654 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4655 * @param DMABurstSource This parameter can be one of the following values:
4656 * @arg @ref LL_TIM_DMA_UPDATE
4657 * @arg @ref LL_TIM_DMA_CC1
4658 * @arg @ref LL_TIM_DMA_CC2
4659 * @arg @ref LL_TIM_DMA_CC3
4660 * @arg @ref LL_TIM_DMA_CC4
4661 * @arg @ref LL_TIM_DMA_COM
4662 * @arg @ref LL_TIM_DMA_TRIGGER
4663 * @retval None
4664 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4665 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4666 uint32_t DMABurstSource)
4667 {
4668 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4669 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4670 }
4671
4672 /**
4673 * @}
4674 */
4675
4676 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4677 * @{
4678 */
4679
4680 /**
4681 * @brief Enable encoder index.
4682 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4683 * a timer instance provides an index input.
4684 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4685 * @param TIMx Timer instance
4686 * @retval None
4687 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4688 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4689 {
4690 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4691 }
4692
4693 /**
4694 * @brief Disable encoder index.
4695 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4696 * a timer instance provides an index input.
4697 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4698 * @param TIMx Timer instance
4699 * @retval None
4700 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4701 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4702 {
4703 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4704 }
4705
4706 /**
4707 * @brief Indicate whether encoder index is enabled.
4708 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4709 * a timer instance provides an index input.
4710 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4711 * @param TIMx Timer instance
4712 * @retval State of bit (1 or 0).
4713 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4714 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4715 {
4716 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4717 }
4718
4719 /**
4720 * @brief Set index direction
4721 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4722 * a timer instance provides an index input.
4723 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4724 * @param TIMx Timer instance
4725 * @param IndexDirection This parameter can be one of the following values:
4726 * @arg @ref LL_TIM_INDEX_UP_DOWN
4727 * @arg @ref LL_TIM_INDEX_UP
4728 * @arg @ref LL_TIM_INDEX_DOWN
4729 * @retval None
4730 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4731 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4732 {
4733 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4734 }
4735
4736 /**
4737 * @brief Get actual index direction
4738 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4739 * a timer instance provides an index input.
4740 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4741 * @param TIMx Timer instance
4742 * @retval Returned value can be one of the following values:
4743 * @arg @ref LL_TIM_INDEX_UP_DOWN
4744 * @arg @ref LL_TIM_INDEX_UP
4745 * @arg @ref LL_TIM_INDEX_DOWN
4746 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4747 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4748 {
4749 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4750 }
4751
4752 /**
4753 * @brief Set index blanking
4754 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4755 * a timer instance provides an index input.
4756 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4757 * @param TIMx Timer instance
4758 * @param Indexblanking This parameter can be one of the following values:
4759 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4760 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4761 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4762 * @retval None
4763 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4764 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4765 {
4766 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4767 }
4768
4769 /**
4770 * @brief Get actual index blanking
4771 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4772 * a timer instance provides an index input.
4773 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4774 * @param TIMx Timer instance
4775 * @retval Returned value can be one of the following values:
4776 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4777 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4778 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4779 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4780 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4781 {
4782 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4783 }
4784
4785
4786 /**
4787 * @brief Enable first index.
4788 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4789 * a timer instance provides an index input.
4790 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4791 * @param TIMx Timer instance
4792 * @retval None
4793 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4794 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4795 {
4796 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4797 }
4798
4799 /**
4800 * @brief Disable first index.
4801 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4802 * a timer instance provides an index input.
4803 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4804 * @param TIMx Timer instance
4805 * @retval None
4806 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4807 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4808 {
4809 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4810 }
4811
4812 /**
4813 * @brief Indicates whether first index is enabled.
4814 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4815 * a timer instance provides an index input.
4816 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4817 * @param TIMx Timer instance
4818 * @retval State of bit (1 or 0).
4819 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4820 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4821 {
4822 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4823 }
4824
4825 /**
4826 * @brief Set index positioning
4827 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4828 * a timer instance provides an index input.
4829 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4830 * @param TIMx Timer instance
4831 * @param IndexPositionning This parameter can be one of the following values:
4832 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4833 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4834 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4835 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4836 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4837 * @arg @ref LL_TIM_INDEX_POSITION_UP
4838 * @retval None
4839 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4840 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4841 {
4842 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4843 }
4844
4845 /**
4846 * @brief Get actual index positioning
4847 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4848 * a timer instance provides an index input.
4849 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4850 * @param TIMx Timer instance
4851 * @retval Returned value can be one of the following values:
4852 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4853 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4854 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4855 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4856 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4857 * @arg @ref LL_TIM_INDEX_POSITION_UP
4858 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4859 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4860 {
4861 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
4862 }
4863
4864 /**
4865 * @brief Configure encoder index.
4866 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4867 * a timer instance provides an index input.
4868 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
4869 * ECR IBLK LL_TIM_ConfigIDX\n
4870 * ECR FIDX LL_TIM_ConfigIDX\n
4871 * ECR IPOS LL_TIM_ConfigIDX
4872 * @param TIMx Timer instance
4873 * @param Configuration This parameter must be a combination of all the following values:
4874 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
4875 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
4876 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
4877 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
4878 * @retval None
4879 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)4880 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
4881 {
4882 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
4883 }
4884
4885 /**
4886 * @}
4887 */
4888
4889 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4890 * @{
4891 */
4892 /**
4893 * @brief Remap TIM inputs (input channel, internal/external triggers).
4894 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4895 * a some timer inputs can be remapped.
4896 * @rmtoll TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4897 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
4898 * TIM9_TISEL TI1SEL LL_TIM_SetRemap\n
4899 * TIM10_TISEL TI1SEL LL_TIM_SetRemap\n
4900 * TIM11_TISEL TI1SEL LL_TIM_SetRemap\n
4901 * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n
4902 * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n
4903 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
4904 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
4905 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4906 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
4907 *
4908 * @param TIMx Timer instance
4909 * @param Remap Remap param depends on the TIMx. Description available only
4910 * in CHM version of the User Manual (not in .pdf).
4911 * Otherwise see Reference Manual description of TISEL registers.
4912 *
4913 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4914 *
4915 * TIM3: one of the following values:
4916 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
4917 * @arg @ref LL_TIM_TIM3_TI1_RMP_ETH1_PPS
4918 * @arg @ref LL_TIM_TIM3_TI1_RMP_FDCAN_RTP
4919 * @arg @ref LL_TIM_TIM3_TI1_RMP_FDCAN_TMP
4920 * @arg @ref LL_TIM_TIM3_TI1_RMP_FDCAN_SOC
4921 *
4922 * TIM5: one of the following values:
4923 * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO
4924 * @arg @ref LL_TIM_TIM5_TI1_RMP_FDCAN_RTP
4925 * @arg @ref LL_TIM_TIM5_TI1_RMP_FDCAN_TMP
4926 *
4927 * TIM9: one of the following values:
4928 * @arg @ref LL_TIM_TIM9_TI1_RMP_GPIO
4929 * @arg @ref LL_TIM_TIM9_TI1_RMP_MCO1
4930 * @arg @ref LL_TIM_TIM9_TI1_RMP_MCO2
4931 *
4932 * TIM10: one of the following values:
4933 * @arg @ref LL_TIM_TIM10_TI1_RMP_GPIO
4934 * @arg @ref LL_TIM_TIM10_TI1_RMP_I3C1_IBIACK
4935 *
4936 * TIM11: one of the following values:
4937 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
4938 * @arg @ref LL_TIM_TIM11_TI1_RMP_I3C2_IBIACK
4939 *
4940 * TIM12: one of the following values:
4941 * @arg @ref LL_TIM_TIM12_TI1_RMP_GPIO
4942 * @arg @ref LL_TIM_TIM12_TI1_RMP_SPDIF_FS
4943 * @arg @ref LL_TIM_TIM12_TI1_RMP_HSI_1024
4944 * @arg @ref LL_TIM_TIM12_TI1_RMP_MSI_128
4945 * @arg @ref LL_TIM_TIM12_TI1_RMP_MCO1
4946 * @arg @ref LL_TIM_TIM12_TI1_RMP_MCO2
4947 *
4948 * TIM13: one of the following values:
4949 * @arg @ref LL_TIM_TIM13_TI1_RMP_GPIO
4950 * @arg @ref LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK
4951 *
4952 * TIM14: one of the following values:
4953 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
4954 * @arg @ref LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK
4955 *
4956 * TIM15: any combination of TI1_RMP and TI2_RMP where
4957 *
4958 * . . TI1_RMP can be one of the following values
4959 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
4960 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM2_CH1
4961 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM3_CH1
4962 * @arg @ref LL_TIM_TIM15_TI1_RMP_TIM4_CH1
4963 * @arg @ref LL_TIM_TIM15_TI1_RMP_MCO1
4964 * @arg @ref LL_TIM_TIM15_TI1_RMP_MCO2
4965 *
4966 * . . TI2_RMP can be one of the following values
4967 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
4968 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM2_CH2
4969 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM3_CH2
4970 * @arg @ref LL_TIM_TIM15_TI2_RMP_TIM4_CH2
4971 *
4972 * TIM16: one of the following values:
4973 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
4974 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
4975 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
4976 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WKUP
4977 *
4978 * TIM17: one of the following values:
4979 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
4980 * @arg @ref LL_TIM_TIM17_TI1_RMP_SPDIF_FS
4981 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_1024
4982 *
4983 * @retval None
4984 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4985 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4986 {
4987 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4988 }
4989
4990 /**
4991 * @}
4992 */
4993
4994 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4995 * @{
4996 */
4997 /**
4998 * @brief Clear the update interrupt flag (UIF).
4999 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5000 * @param TIMx Timer instance
5001 * @retval None
5002 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5003 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5004 {
5005 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5006 }
5007
5008 /**
5009 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5010 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5011 * @param TIMx Timer instance
5012 * @retval State of bit (1 or 0).
5013 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)5014 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
5015 {
5016 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5017 }
5018
5019 /**
5020 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5021 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5022 * @param TIMx Timer instance
5023 * @retval None
5024 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5025 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5026 {
5027 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5028 }
5029
5030 /**
5031 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5032 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5033 * @param TIMx Timer instance
5034 * @retval State of bit (1 or 0).
5035 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)5036 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
5037 {
5038 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5039 }
5040
5041 /**
5042 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5043 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5044 * @param TIMx Timer instance
5045 * @retval None
5046 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5047 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5048 {
5049 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5050 }
5051
5052 /**
5053 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5054 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5055 * @param TIMx Timer instance
5056 * @retval State of bit (1 or 0).
5057 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)5058 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
5059 {
5060 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5061 }
5062
5063 /**
5064 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5065 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5066 * @param TIMx Timer instance
5067 * @retval None
5068 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5069 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5070 {
5071 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5072 }
5073
5074 /**
5075 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5076 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5077 * @param TIMx Timer instance
5078 * @retval State of bit (1 or 0).
5079 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)5080 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
5081 {
5082 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5083 }
5084
5085 /**
5086 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5087 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5088 * @param TIMx Timer instance
5089 * @retval None
5090 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5091 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5092 {
5093 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5094 }
5095
5096 /**
5097 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5098 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5099 * @param TIMx Timer instance
5100 * @retval State of bit (1 or 0).
5101 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)5102 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
5103 {
5104 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5105 }
5106
5107 /**
5108 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5109 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5110 * @param TIMx Timer instance
5111 * @retval None
5112 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5113 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5114 {
5115 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5116 }
5117
5118 /**
5119 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5120 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5121 * @param TIMx Timer instance
5122 * @retval State of bit (1 or 0).
5123 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)5124 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
5125 {
5126 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5127 }
5128
5129 /**
5130 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5131 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5132 * @param TIMx Timer instance
5133 * @retval None
5134 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5135 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5136 {
5137 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5138 }
5139
5140 /**
5141 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5142 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5143 * @param TIMx Timer instance
5144 * @retval State of bit (1 or 0).
5145 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)5146 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
5147 {
5148 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5149 }
5150
5151 /**
5152 * @brief Clear the commutation interrupt flag (COMIF).
5153 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5154 * @param TIMx Timer instance
5155 * @retval None
5156 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5157 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5158 {
5159 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5160 }
5161
5162 /**
5163 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5164 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5165 * @param TIMx Timer instance
5166 * @retval State of bit (1 or 0).
5167 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5168 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5169 {
5170 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5171 }
5172
5173 /**
5174 * @brief Clear the trigger interrupt flag (TIF).
5175 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5176 * @param TIMx Timer instance
5177 * @retval None
5178 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5179 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5180 {
5181 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5182 }
5183
5184 /**
5185 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5186 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5187 * @param TIMx Timer instance
5188 * @retval State of bit (1 or 0).
5189 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5190 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5191 {
5192 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5193 }
5194
5195 /**
5196 * @brief Clear the break interrupt flag (BIF).
5197 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5198 * @param TIMx Timer instance
5199 * @retval None
5200 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5201 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5202 {
5203 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5204 }
5205
5206 /**
5207 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5208 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5209 * @param TIMx Timer instance
5210 * @retval State of bit (1 or 0).
5211 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5212 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5213 {
5214 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5215 }
5216
5217 /**
5218 * @brief Clear the break 2 interrupt flag (B2IF).
5219 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5220 * @param TIMx Timer instance
5221 * @retval None
5222 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5223 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5224 {
5225 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5226 }
5227
5228 /**
5229 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5230 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5231 * @param TIMx Timer instance
5232 * @retval State of bit (1 or 0).
5233 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5234 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5235 {
5236 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5237 }
5238
5239 /**
5240 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5241 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5242 * @param TIMx Timer instance
5243 * @retval None
5244 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5245 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5246 {
5247 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5248 }
5249
5250 /**
5251 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5252 * (Capture/Compare 1 interrupt is pending).
5253 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5254 * @param TIMx Timer instance
5255 * @retval State of bit (1 or 0).
5256 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5257 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5258 {
5259 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5260 }
5261
5262 /**
5263 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5264 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5265 * @param TIMx Timer instance
5266 * @retval None
5267 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5268 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5269 {
5270 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5271 }
5272
5273 /**
5274 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5275 * (Capture/Compare 2 over-capture interrupt is pending).
5276 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5277 * @param TIMx Timer instance
5278 * @retval State of bit (1 or 0).
5279 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5280 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5281 {
5282 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5283 }
5284
5285 /**
5286 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5287 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5288 * @param TIMx Timer instance
5289 * @retval None
5290 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5291 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5292 {
5293 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5294 }
5295
5296 /**
5297 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5298 * (Capture/Compare 3 over-capture interrupt is pending).
5299 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5300 * @param TIMx Timer instance
5301 * @retval State of bit (1 or 0).
5302 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5303 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5304 {
5305 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5306 }
5307
5308 /**
5309 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5310 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5311 * @param TIMx Timer instance
5312 * @retval None
5313 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5314 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5315 {
5316 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5317 }
5318
5319 /**
5320 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5321 * (Capture/Compare 4 over-capture interrupt is pending).
5322 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5323 * @param TIMx Timer instance
5324 * @retval State of bit (1 or 0).
5325 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5326 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5327 {
5328 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5329 }
5330
5331 /**
5332 * @brief Clear the system break interrupt flag (SBIF).
5333 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5334 * @param TIMx Timer instance
5335 * @retval None
5336 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5337 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5338 {
5339 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5340 }
5341
5342 /**
5343 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5344 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5345 * @param TIMx Timer instance
5346 * @retval State of bit (1 or 0).
5347 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5348 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5349 {
5350 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5351 }
5352
5353 /**
5354 * @brief Clear the transition error interrupt flag (TERRF).
5355 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5356 * a timer instance provides encoder error management.
5357 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5358 * @param TIMx Timer instance
5359 * @retval None
5360 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5361 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5362 {
5363 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5364 }
5365
5366 /**
5367 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5368 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5369 * a timer instance provides encoder error management.
5370 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5371 * @param TIMx Timer instance
5372 * @retval State of bit (1 or 0).
5373 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5374 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5375 {
5376 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5377 }
5378
5379 /**
5380 * @brief Clear the index error interrupt flag (IERRF).
5381 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5382 * a timer instance provides encoder error management.
5383 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5384 * @param TIMx Timer instance
5385 * @retval None
5386 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5387 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5388 {
5389 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5390 }
5391
5392 /**
5393 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5394 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5395 * a timer instance provides encoder error management.
5396 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5397 * @param TIMx Timer instance
5398 * @retval State of bit (1 or 0).
5399 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5400 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5401 {
5402 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5403 }
5404
5405 /**
5406 * @brief Clear the direction change interrupt flag (DIRF).
5407 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5408 * a timer instance provides encoder interrupt management.
5409 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5410 * @param TIMx Timer instance
5411 * @retval None
5412 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5413 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5414 {
5415 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5416 }
5417
5418 /**
5419 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5420 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5421 * a timer instance provides encoder interrupt management.
5422 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5423 * @param TIMx Timer instance
5424 * @retval State of bit (1 or 0).
5425 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5426 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5427 {
5428 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5429 }
5430
5431 /**
5432 * @brief Clear the index interrupt flag (IDXF).
5433 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5434 * a timer instance provides encoder interrupt management.
5435 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5436 * @param TIMx Timer instance
5437 * @retval None
5438 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5439 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5440 {
5441 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5442 }
5443
5444 /**
5445 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5446 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5447 * a timer instance provides encoder interrupt management.
5448 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5449 * @param TIMx Timer instance
5450 * @retval State of bit (1 or 0).
5451 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5452 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5453 {
5454 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5455 }
5456 /**
5457 * @}
5458 */
5459
5460 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5461 * @{
5462 */
5463 /**
5464 * @brief Enable update interrupt (UIE).
5465 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5466 * @param TIMx Timer instance
5467 * @retval None
5468 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5469 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5470 {
5471 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5472 }
5473
5474 /**
5475 * @brief Disable update interrupt (UIE).
5476 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5477 * @param TIMx Timer instance
5478 * @retval None
5479 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5480 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5481 {
5482 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5483 }
5484
5485 /**
5486 * @brief Indicates whether the update interrupt (UIE) is enabled.
5487 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5488 * @param TIMx Timer instance
5489 * @retval State of bit (1 or 0).
5490 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5491 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5492 {
5493 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5494 }
5495
5496 /**
5497 * @brief Enable capture/compare 1 interrupt (CC1IE).
5498 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5499 * @param TIMx Timer instance
5500 * @retval None
5501 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5502 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5503 {
5504 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5505 }
5506
5507 /**
5508 * @brief Disable capture/compare 1 interrupt (CC1IE).
5509 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5510 * @param TIMx Timer instance
5511 * @retval None
5512 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5513 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5514 {
5515 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5516 }
5517
5518 /**
5519 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5520 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5521 * @param TIMx Timer instance
5522 * @retval State of bit (1 or 0).
5523 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5524 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5525 {
5526 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5527 }
5528
5529 /**
5530 * @brief Enable capture/compare 2 interrupt (CC2IE).
5531 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5532 * @param TIMx Timer instance
5533 * @retval None
5534 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5535 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5536 {
5537 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5538 }
5539
5540 /**
5541 * @brief Disable capture/compare 2 interrupt (CC2IE).
5542 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5543 * @param TIMx Timer instance
5544 * @retval None
5545 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5546 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5547 {
5548 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5549 }
5550
5551 /**
5552 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5553 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5554 * @param TIMx Timer instance
5555 * @retval State of bit (1 or 0).
5556 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5557 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5558 {
5559 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5560 }
5561
5562 /**
5563 * @brief Enable capture/compare 3 interrupt (CC3IE).
5564 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5565 * @param TIMx Timer instance
5566 * @retval None
5567 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5568 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5569 {
5570 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5571 }
5572
5573 /**
5574 * @brief Disable capture/compare 3 interrupt (CC3IE).
5575 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5576 * @param TIMx Timer instance
5577 * @retval None
5578 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5579 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5580 {
5581 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5582 }
5583
5584 /**
5585 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5586 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5587 * @param TIMx Timer instance
5588 * @retval State of bit (1 or 0).
5589 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5590 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5591 {
5592 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5593 }
5594
5595 /**
5596 * @brief Enable capture/compare 4 interrupt (CC4IE).
5597 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5598 * @param TIMx Timer instance
5599 * @retval None
5600 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5601 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5602 {
5603 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5604 }
5605
5606 /**
5607 * @brief Disable capture/compare 4 interrupt (CC4IE).
5608 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5609 * @param TIMx Timer instance
5610 * @retval None
5611 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5612 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5613 {
5614 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5615 }
5616
5617 /**
5618 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5619 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5620 * @param TIMx Timer instance
5621 * @retval State of bit (1 or 0).
5622 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5623 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5624 {
5625 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5626 }
5627
5628 /**
5629 * @brief Enable commutation interrupt (COMIE).
5630 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5631 * @param TIMx Timer instance
5632 * @retval None
5633 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5634 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5635 {
5636 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5637 }
5638
5639 /**
5640 * @brief Disable commutation interrupt (COMIE).
5641 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5642 * @param TIMx Timer instance
5643 * @retval None
5644 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5645 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5646 {
5647 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5648 }
5649
5650 /**
5651 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5652 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5653 * @param TIMx Timer instance
5654 * @retval State of bit (1 or 0).
5655 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5656 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5657 {
5658 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5659 }
5660
5661 /**
5662 * @brief Enable trigger interrupt (TIE).
5663 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5664 * @param TIMx Timer instance
5665 * @retval None
5666 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5667 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5668 {
5669 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5670 }
5671
5672 /**
5673 * @brief Disable trigger interrupt (TIE).
5674 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5675 * @param TIMx Timer instance
5676 * @retval None
5677 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5678 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5679 {
5680 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5681 }
5682
5683 /**
5684 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5685 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5686 * @param TIMx Timer instance
5687 * @retval State of bit (1 or 0).
5688 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5689 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5690 {
5691 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5692 }
5693
5694 /**
5695 * @brief Enable break interrupt (BIE).
5696 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5697 * @param TIMx Timer instance
5698 * @retval None
5699 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5700 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5701 {
5702 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5703 }
5704
5705 /**
5706 * @brief Disable break interrupt (BIE).
5707 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5708 * @param TIMx Timer instance
5709 * @retval None
5710 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5711 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5712 {
5713 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5714 }
5715
5716 /**
5717 * @brief Indicates whether the break interrupt (BIE) is enabled.
5718 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5719 * @param TIMx Timer instance
5720 * @retval State of bit (1 or 0).
5721 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5722 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5723 {
5724 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5725 }
5726
5727 /**
5728 * @brief Enable transition error interrupt (TERRIE).
5729 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5730 * a timer instance provides encoder error management.
5731 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5732 * @param TIMx Timer instance
5733 * @retval None
5734 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5735 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5736 {
5737 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5738 }
5739
5740 /**
5741 * @brief Disable transition error interrupt (TERRIE).
5742 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5743 * a timer instance provides encoder error management.
5744 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5745 * @param TIMx Timer instance
5746 * @retval None
5747 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5748 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5749 {
5750 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5751 }
5752
5753 /**
5754 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5755 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5756 * a timer instance provides encoder error management.
5757 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5758 * @param TIMx Timer instance
5759 * @retval State of bit (1 or 0).
5760 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5761 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5762 {
5763 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5764 }
5765
5766 /**
5767 * @brief Enable index error interrupt (IERRIE).
5768 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5769 * a timer instance provides encoder error management.
5770 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5771 * @param TIMx Timer instance
5772 * @retval None
5773 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5774 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5775 {
5776 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5777 }
5778
5779 /**
5780 * @brief Disable index error interrupt (IERRIE).
5781 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5782 * a timer instance provides encoder error management.
5783 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
5784 * @param TIMx Timer instance
5785 * @retval None
5786 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)5787 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
5788 {
5789 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5790 }
5791
5792 /**
5793 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
5794 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5795 * a timer instance provides encoder error management.
5796 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
5797 * @param TIMx Timer instance
5798 * @retval State of bit (1 or 0).
5799 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)5800 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
5801 {
5802 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
5803 }
5804
5805 /**
5806 * @brief Enable direction change interrupt (DIRIE).
5807 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5808 * a timer instance provides encoder interrupt management.
5809 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
5810 * @param TIMx Timer instance
5811 * @retval None
5812 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)5813 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
5814 {
5815 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5816 }
5817
5818 /**
5819 * @brief Disable direction change interrupt (DIRIE).
5820 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5821 * a timer instance provides encoder interrupt management.
5822 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
5823 * @param TIMx Timer instance
5824 * @retval None
5825 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)5826 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
5827 {
5828 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5829 }
5830
5831 /**
5832 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
5833 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5834 * a timer instance provides encoder interrupt management.
5835 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
5836 * @param TIMx Timer instance
5837 * @retval State of bit (1 or 0).
5838 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)5839 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
5840 {
5841 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
5842 }
5843
5844 /**
5845 * @brief Enable index interrupt (IDXIE).
5846 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5847 * a timer instance provides encoder interrupt management.
5848 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
5849 * @param TIMx Timer instance
5850 * @retval None
5851 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)5852 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
5853 {
5854 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5855 }
5856
5857 /**
5858 * @brief Disable index interrupt (IDXIE).
5859 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5860 * a timer instance provides encoder interrupt management.
5861 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
5862 * @param TIMx Timer instance
5863 * @retval None
5864 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)5865 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
5866 {
5867 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5868 }
5869
5870 /**
5871 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
5872 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5873 * a timer instance provides encoder interrupt management.
5874 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
5875 * @param TIMx Timer instance
5876 * @retval State of bit (1 or 0).
5877 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)5878 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
5879 {
5880 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
5881 }
5882
5883 /**
5884 * @}
5885 */
5886
5887 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
5888 * @{
5889 */
5890 /**
5891 * @brief Enable update DMA request (UDE).
5892 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
5893 * @param TIMx Timer instance
5894 * @retval None
5895 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)5896 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5897 {
5898 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
5899 }
5900
5901 /**
5902 * @brief Disable update DMA request (UDE).
5903 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
5904 * @param TIMx Timer instance
5905 * @retval None
5906 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)5907 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5908 {
5909 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
5910 }
5911
5912 /**
5913 * @brief Indicates whether the update DMA request (UDE) is enabled.
5914 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
5915 * @param TIMx Timer instance
5916 * @retval State of bit (1 or 0).
5917 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)5918 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
5919 {
5920 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
5921 }
5922
5923 /**
5924 * @brief Enable capture/compare 1 DMA request (CC1DE).
5925 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
5926 * @param TIMx Timer instance
5927 * @retval None
5928 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)5929 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
5930 {
5931 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5932 }
5933
5934 /**
5935 * @brief Disable capture/compare 1 DMA request (CC1DE).
5936 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
5937 * @param TIMx Timer instance
5938 * @retval None
5939 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)5940 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
5941 {
5942 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5943 }
5944
5945 /**
5946 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
5947 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
5948 * @param TIMx Timer instance
5949 * @retval State of bit (1 or 0).
5950 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)5951 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
5952 {
5953 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
5954 }
5955
5956 /**
5957 * @brief Enable capture/compare 2 DMA request (CC2DE).
5958 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
5959 * @param TIMx Timer instance
5960 * @retval None
5961 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)5962 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
5963 {
5964 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5965 }
5966
5967 /**
5968 * @brief Disable capture/compare 2 DMA request (CC2DE).
5969 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
5970 * @param TIMx Timer instance
5971 * @retval None
5972 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)5973 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
5974 {
5975 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5976 }
5977
5978 /**
5979 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
5980 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
5981 * @param TIMx Timer instance
5982 * @retval State of bit (1 or 0).
5983 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)5984 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
5985 {
5986 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
5987 }
5988
5989 /**
5990 * @brief Enable capture/compare 3 DMA request (CC3DE).
5991 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
5992 * @param TIMx Timer instance
5993 * @retval None
5994 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)5995 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
5996 {
5997 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5998 }
5999
6000 /**
6001 * @brief Disable capture/compare 3 DMA request (CC3DE).
6002 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6003 * @param TIMx Timer instance
6004 * @retval None
6005 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6006 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6007 {
6008 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6009 }
6010
6011 /**
6012 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6013 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6014 * @param TIMx Timer instance
6015 * @retval State of bit (1 or 0).
6016 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)6017 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
6018 {
6019 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6020 }
6021
6022 /**
6023 * @brief Enable capture/compare 4 DMA request (CC4DE).
6024 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6025 * @param TIMx Timer instance
6026 * @retval None
6027 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6028 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6029 {
6030 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6031 }
6032
6033 /**
6034 * @brief Disable capture/compare 4 DMA request (CC4DE).
6035 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6036 * @param TIMx Timer instance
6037 * @retval None
6038 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6039 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6040 {
6041 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6042 }
6043
6044 /**
6045 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6046 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6047 * @param TIMx Timer instance
6048 * @retval State of bit (1 or 0).
6049 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)6050 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
6051 {
6052 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6053 }
6054
6055 /**
6056 * @brief Enable commutation DMA request (COMDE).
6057 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6058 * @param TIMx Timer instance
6059 * @retval None
6060 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6061 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6062 {
6063 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6064 }
6065
6066 /**
6067 * @brief Disable commutation DMA request (COMDE).
6068 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6069 * @param TIMx Timer instance
6070 * @retval None
6071 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6072 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6073 {
6074 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6075 }
6076
6077 /**
6078 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6079 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6080 * @param TIMx Timer instance
6081 * @retval State of bit (1 or 0).
6082 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)6083 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
6084 {
6085 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6086 }
6087
6088 /**
6089 * @brief Enable trigger interrupt (TDE).
6090 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6091 * @param TIMx Timer instance
6092 * @retval None
6093 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6094 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6095 {
6096 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6097 }
6098
6099 /**
6100 * @brief Disable trigger interrupt (TDE).
6101 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6102 * @param TIMx Timer instance
6103 * @retval None
6104 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6105 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6106 {
6107 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6108 }
6109
6110 /**
6111 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6112 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6113 * @param TIMx Timer instance
6114 * @retval State of bit (1 or 0).
6115 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)6116 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
6117 {
6118 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6119 }
6120
6121 /**
6122 * @}
6123 */
6124
6125 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6126 * @{
6127 */
6128 /**
6129 * @brief Generate an update event.
6130 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6131 * @param TIMx Timer instance
6132 * @retval None
6133 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6134 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6135 {
6136 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6137 }
6138
6139 /**
6140 * @brief Generate Capture/Compare 1 event.
6141 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6142 * @param TIMx Timer instance
6143 * @retval None
6144 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6145 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6146 {
6147 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6148 }
6149
6150 /**
6151 * @brief Generate Capture/Compare 2 event.
6152 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6153 * @param TIMx Timer instance
6154 * @retval None
6155 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6156 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6157 {
6158 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6159 }
6160
6161 /**
6162 * @brief Generate Capture/Compare 3 event.
6163 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6164 * @param TIMx Timer instance
6165 * @retval None
6166 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6167 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6168 {
6169 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6170 }
6171
6172 /**
6173 * @brief Generate Capture/Compare 4 event.
6174 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6175 * @param TIMx Timer instance
6176 * @retval None
6177 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6178 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6179 {
6180 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6181 }
6182
6183 /**
6184 * @brief Generate commutation event.
6185 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6186 * @param TIMx Timer instance
6187 * @retval None
6188 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6189 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6190 {
6191 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6192 }
6193
6194 /**
6195 * @brief Generate trigger event.
6196 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6197 * @param TIMx Timer instance
6198 * @retval None
6199 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6200 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6201 {
6202 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6203 }
6204
6205 /**
6206 * @brief Generate break event.
6207 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6208 * @param TIMx Timer instance
6209 * @retval None
6210 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6211 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6212 {
6213 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6214 }
6215
6216 /**
6217 * @brief Generate break 2 event.
6218 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6219 * @param TIMx Timer instance
6220 * @retval None
6221 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6222 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6223 {
6224 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6225 }
6226
6227 /**
6228 * @}
6229 */
6230
6231 #if defined(USE_FULL_LL_DRIVER)
6232 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6233 * @{
6234 */
6235
6236 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6237 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6238 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6239 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6240 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6241 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6242 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6243 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6244 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6245 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6246 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6247 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6248 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6249 /**
6250 * @}
6251 */
6252 #endif /* USE_FULL_LL_DRIVER */
6253
6254 /**
6255 * @}
6256 */
6257
6258 /**
6259 * @}
6260 */
6261
6262 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 */
6263
6264 /**
6265 * @}
6266 */
6267
6268 #ifdef __cplusplus
6269 }
6270 #endif
6271
6272 #endif /* __STM32N6xx_LL_TIM_H */
6273
