1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2017 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL SYSTEM driver contains a set of generic APIs that can be
24 used by user:
25 (+) Some of the FLASH features need to be handled in the SYSTEM file.
26 (+) Access to DBGCMU registers
27 (+) Access to SYSCFG registers
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef __STM32H7xx_LL_SYSTEM_H
35 #define __STM32H7xx_LL_SYSTEM_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32h7xx.h"
43
44 /** @addtogroup STM32H7xx_LL_Driver
45 * @{
46 */
47
48 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
50 /** @defgroup SYSTEM_LL SYSTEM
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
59 * @{
60 */
61 /** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status
62 * @{
63 */
64 #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U
65 #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U
66 #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U
67 #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U
68 #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U
69 #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U
70 #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U
71 #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U
72 /**
73 * @}
74 */
75
76 /** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status
77 * @{
78 */
79 #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U
80 #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U
81 #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U
82 #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U
83 #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U
84 #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U
85 #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U
86 #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U
87 /**
88 * @}
89 */
90 /**
91 * @}
92 */
93
94 /* Private macros ------------------------------------------------------------*/
95
96 /* Exported types ------------------------------------------------------------*/
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
99 * @{
100 */
101
102 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
103 * @{
104 */
105 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
106 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
107 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
108 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
109 #if defined(I2C5)
110 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */
111 #endif /*I2C5*/
112 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
113 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
114 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
115 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
116 /**
117 * @}
118 */
119
120 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control
121 * @{
122 */
123 #if defined(SYSCFG_PMCR_BOOSTEN)
124 #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */
125 #endif /*SYSCFG_PMCR_BOOSTEN*/
126 #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */
127 #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */
128 #define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */
129 #define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */
130 /**
131 * @}
132 */
133
134 #if defined(SYSCFG_PMCR_EPIS_SEL)
135 /** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection
136 * @{
137 */
138 #define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */
139 #define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */
140 /**
141 * @}
142 */
143 #endif /* SYSCFG_PMCR_EPIS_SEL */
144
145 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
146 * @{
147 */
148 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
149 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
150 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
151 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
152 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
153 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
154 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
155 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
156 #if defined(GPIOI)
157 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
158 #endif /*GPIOI*/
159 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
160 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
161 /**
162 * @}
163 */
164
165 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
166 * @{
167 */
168 #define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
169 #define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
170 #define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
171 #define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
172 #define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
173 #define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
174 #define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
175 #define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
176 #define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
177 #define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
178 #define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
179 #define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
180 #define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
181 #define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
182 #define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
183 #define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
184 /**
185 * @}
186 */
187
188 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
189 * @{
190 */
191 #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal
192 with Break Input of TIM1/8/15/16/17 and HRTIM */
193
194 #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal
195 with Break Input of TIM1/8/15/16/17 and HRTIM */
196
197 #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal
198 with Break Input of TIM1/8/15/16/17 and HRTIM */
199
200 #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal
201 with Break Input of TIM1/8/15/16/17 and HRTIM */
202
203 #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal
204 with Break Input of TIM1/8/15/16/17 and HRTIM */
205
206 #if defined(SYSCFG_CFGR_SRAM3L)
207 #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal
208 with Break Input of TIM1/8/15/16/17 and HRTIM */
209 #endif /*SYSCFG_CFGR_SRAM3L*/
210
211 #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal
212 with Break Input of TIM1/8/15/16/17 and HRTIM */
213
214 #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal
215 with Break Input of TIM1/8/15/16/17 and HRTIM */
216
217 #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal
218 with Break Input of TIM1/8/15/16/17 and HRTIM */
219
220 #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal
221 with Break Input of TIM1/8/15/16/17 and HRTIM */
222
223 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection
224 with TIM1/8/15/16/17 and HRTIM Break Input
225 and also the PVDE and PLS bits of the Power Control Interface */
226 #if defined(DUAL_CORE)
227 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal
228 with Break Input of TIM1/8/15/16/17 and HRTIM */
229 #endif /* DUAL_CORE */
230 /**
231 * @}
232 */
233
234 /** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection
235 * @{
236 */
237 #define LL_SYSCFG_CELL_CODE 0U
238 #define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS
239 /**
240 * @}
241 */
242
243 /** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes
244 * @{
245 */
246 #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U
247 #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M
248 /**
249 * @}
250 */
251
252 #if defined (DUAL_CORE)
253 /** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes
254 * @{
255 */
256 #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U
257 #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M
258 /**
259 * @}
260 */
261 #endif /* DUAL_CORE */
262
263 /** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration
264 * @{
265 */
266 #define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U
267 #define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U
268 #define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U
269 #define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U
270 /**
271 * @}
272 */
273 #ifdef SYSCFG_UR17_TCM_AXI_CFG
274 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
275 * @{
276 */
277 #define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U
278 #define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U
279 #define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U
280 #define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U
281 /**
282 * @}
283 */
284 #endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */
285 #if defined(SYSCFG_PKGR_PKG)
286 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package
287 * @{
288 */
289 #if (STM32H7_DEV_ID == 0x450UL)
290 #define LL_SYSCFG_LQFP100_PACKAGE 0U
291 #define LL_SYSCFG_TQFP144_PACKAGE 2U
292 #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U
293 #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U
294 #elif (STM32H7_DEV_ID == 0x483UL)
295 #define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U
296 #define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U
297 #define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U
298 #define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U
299 #define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U
300 #define LL_SYSCFG_LQFP144_PACKAGE 5U
301 #define LL_SYSCFG_UFBGA144_PACKAGE 6U
302 #define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U
303 #define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U
304 #define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U
305 #define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U
306 #endif /* STM32H7_DEV_ID == 0x450UL */
307 /**
308 * @}
309 */
310 #endif /* SYSCFG_PKGR_PKG */
311
312 /** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level
313 * @{
314 */
315 #define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U
316 #define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0
317 #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1
318 #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH
319
320 /**
321 * @}
322 */
323
324 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
325 * @{
326 */
327 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
328 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
329 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
330 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
331 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
332 /**
333 * @}
334 */
335
336 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
337 * @{
338 */
339 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */
340 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */
341 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */
342 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */
343 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */
344 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */
345 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */
346 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */
347 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */
348 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */
349 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
350 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
351 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
352 #if defined(I2C5)
353 #define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */
354 #endif /*I2C5*/
355 /**
356 * @}
357 */
358
359
360 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
361 * @{
362 */
363 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN)
364 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */
365 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
366 #if defined(TIM23)
367 #define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */
368 #endif /*TIM23*/
369 #if defined(TIM24)
370 #define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */
371 #endif /*TIM24*/
372 /**
373 * @}
374 */
375
376 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
377 * @{
378 */
379 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */
380 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */
381 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */
382 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */
383 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */
384 #if defined(HRTIM1)
385 #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */
386 #endif /*HRTIM1*/
387 /**
388 * @}
389 */
390
391 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
392 * @{
393 */
394 #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */
395 /**
396 * @}
397 */
398
399 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
400 * @{
401 */
402 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */
403 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */
404 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */
405 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */
406 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */
407 #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */
408 #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */
409 /**
410 * @}
411 */
412
413 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
414 * @{
415 */
416 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
417 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
418 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
419 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
420 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
421 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
422 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
423 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
424 /**
425 * @}
426 */
427
428 /**
429 * @}
430 */
431
432 /* Exported macro ------------------------------------------------------------*/
433
434 /* Exported functions --------------------------------------------------------*/
435 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
436 * @{
437 */
438
439 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
440 * @{
441 */
442
443 #if defined(SYSCFG_PMCR_EPIS_SEL)
444 /**
445 * @brief Select Ethernet PHY interface
446 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface
447 * @param Interface This parameter can be one of the following values:
448 * @arg @ref LL_SYSCFG_ETH_MII
449 * @arg @ref LL_SYSCFG_ETH_RMII
450 * @retval None
451 */
LL_SYSCFG_SetPHYInterface(uint32_t Interface)452 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
453 {
454 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);
455 }
456
457 /**
458 * @brief Get Ethernet PHY interface
459 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface
460 * @retval Returned value can be one of the following values:
461 * @arg @ref LL_SYSCFG_ETH_MII
462 * @arg @ref LL_SYSCFG_ETH_RMII
463 */
LL_SYSCFG_GetPHYInterface(void)464 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
465 {
466 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));
467 }
468
469 #endif /* SYSCFG_PMCR_EPIS_SEL */
470 /**
471 * @brief Open an Analog Switch
472 * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch
473 * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch
474 * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch
475 * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch
476 * @param AnalogSwitch This parameter can be one of the following values:
477 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
478 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
479 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
480 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
481 * @retval None
482 */
LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)483 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)
484 {
485 SET_BIT(SYSCFG->PMCR, AnalogSwitch);
486 }
487
488 /**
489 * @brief Close an Analog Switch
490 * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch
491 * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch
492 * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch
493 * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch
494 * @param AnalogSwitch This parameter can be one of the following values:
495 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch
496 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch
497 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch
498 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch
499 * @retval None
500 */
LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)501 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)
502 {
503 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);
504 }
505 #ifdef SYSCFG_PMCR_BOOSTEN
506 /**
507 * @brief Enable the Analog booster to reduce the total harmonic distortion
508 * of the analog switch when the supply voltage is lower than 2.7 V
509 * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster
510 * @note Activating the booster allows to guaranty the analog switch AC performance
511 * when the supply voltage is below 2.7 V: in this case, the analog switch
512 * performance is the same on the full voltage range
513 * @retval None
514 */
LL_SYSCFG_EnableAnalogBooster(void)515 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
516 {
517 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
518 }
519
520 /**
521 * @brief Disable the Analog booster
522 * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster
523 * @note Activating the booster allows to guaranty the analog switch AC performance
524 * when the supply voltage is below 2.7 V: in this case, the analog switch
525 * performance is the same on the full voltage range
526 * @retval None
527 */
LL_SYSCFG_DisableAnalogBooster(void)528 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
529 {
530 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
531 }
532 #endif /*SYSCFG_PMCR_BOOSTEN*/
533 /**
534 * @brief Enable the I2C fast mode plus driving capability.
535 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
536 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus
537 * @param ConfigFastModePlus This parameter can be a combination of the following values:
538 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
539 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
540 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
541 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
542 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
543 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
544 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
545 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
546 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
547 *
548 * (*) value not defined in all devices
549 * @retval None
550 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)551 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
552 {
553 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);
554 }
555
556 /**
557 * @brief Disable the I2C fast mode plus driving capability.
558 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
559 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus
560 * @param ConfigFastModePlus This parameter can be a combination of the following values:
561 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
562 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
563 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
564 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
565 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
566 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
567 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
568 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
569 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
570 *
571 * (*) value not defined in all devices
572 * @retval None
573 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)574 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
575 {
576 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);
577 }
578
579 /**
580 * @brief Configure source input for the EXTI external interrupt.
581 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
582 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
583 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
584 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
585 * @param Port This parameter can be one of the following values:
586 * @arg @ref LL_SYSCFG_EXTI_PORTA
587 * @arg @ref LL_SYSCFG_EXTI_PORTB
588 * @arg @ref LL_SYSCFG_EXTI_PORTC
589 * @arg @ref LL_SYSCFG_EXTI_PORTD
590 * @arg @ref LL_SYSCFG_EXTI_PORTE
591 * @arg @ref LL_SYSCFG_EXTI_PORTF
592 * @arg @ref LL_SYSCFG_EXTI_PORTG
593 * @arg @ref LL_SYSCFG_EXTI_PORTH
594 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
595 * @arg @ref LL_SYSCFG_EXTI_PORTJ
596 * @arg @ref LL_SYSCFG_EXTI_PORTK
597 *
598 * (*) value not defined in all devices
599 * @param Line This parameter can be one of the following values:
600 * @arg @ref LL_SYSCFG_EXTI_LINE0
601 * @arg @ref LL_SYSCFG_EXTI_LINE1
602 * @arg @ref LL_SYSCFG_EXTI_LINE2
603 * @arg @ref LL_SYSCFG_EXTI_LINE3
604 * @arg @ref LL_SYSCFG_EXTI_LINE4
605 * @arg @ref LL_SYSCFG_EXTI_LINE5
606 * @arg @ref LL_SYSCFG_EXTI_LINE6
607 * @arg @ref LL_SYSCFG_EXTI_LINE7
608 * @arg @ref LL_SYSCFG_EXTI_LINE8
609 * @arg @ref LL_SYSCFG_EXTI_LINE9
610 * @arg @ref LL_SYSCFG_EXTI_LINE10
611 * @arg @ref LL_SYSCFG_EXTI_LINE11
612 * @arg @ref LL_SYSCFG_EXTI_LINE12
613 * @arg @ref LL_SYSCFG_EXTI_LINE13
614 * @arg @ref LL_SYSCFG_EXTI_LINE14
615 * @arg @ref LL_SYSCFG_EXTI_LINE15
616 * @retval None
617 */
LL_SYSCFG_SetEXTISource(uint32_t Port,uint32_t Line)618 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
619 {
620 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));
621 }
622
623 /**
624 * @brief Get the configured defined for specific EXTI Line
625 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
626 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
627 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
628 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
629 * @param Line This parameter can be one of the following values:
630 * @arg @ref LL_SYSCFG_EXTI_LINE0
631 * @arg @ref LL_SYSCFG_EXTI_LINE1
632 * @arg @ref LL_SYSCFG_EXTI_LINE2
633 * @arg @ref LL_SYSCFG_EXTI_LINE3
634 * @arg @ref LL_SYSCFG_EXTI_LINE4
635 * @arg @ref LL_SYSCFG_EXTI_LINE5
636 * @arg @ref LL_SYSCFG_EXTI_LINE6
637 * @arg @ref LL_SYSCFG_EXTI_LINE7
638 * @arg @ref LL_SYSCFG_EXTI_LINE8
639 * @arg @ref LL_SYSCFG_EXTI_LINE9
640 * @arg @ref LL_SYSCFG_EXTI_LINE10
641 * @arg @ref LL_SYSCFG_EXTI_LINE11
642 * @arg @ref LL_SYSCFG_EXTI_LINE12
643 * @arg @ref LL_SYSCFG_EXTI_LINE13
644 * @arg @ref LL_SYSCFG_EXTI_LINE14
645 * @arg @ref LL_SYSCFG_EXTI_LINE15
646 * @retval Returned value can be one of the following values:
647 * @arg @ref LL_SYSCFG_EXTI_PORTA
648 * @arg @ref LL_SYSCFG_EXTI_PORTB
649 * @arg @ref LL_SYSCFG_EXTI_PORTC
650 * @arg @ref LL_SYSCFG_EXTI_PORTD
651 * @arg @ref LL_SYSCFG_EXTI_PORTE
652 * @arg @ref LL_SYSCFG_EXTI_PORTF
653 * @arg @ref LL_SYSCFG_EXTI_PORTG
654 * @arg @ref LL_SYSCFG_EXTI_PORTH
655 * @arg @ref LL_SYSCFG_EXTI_PORTI (*)
656 * @arg @ref LL_SYSCFG_EXTI_PORTJ
657 * @arg @ref LL_SYSCFG_EXTI_PORTK
658 * (*) value not defined in all devices
659 */
LL_SYSCFG_GetEXTISource(uint32_t Line)660 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
661 {
662 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));
663 }
664
665 /**
666 * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs
667 * @note this feature is available on STM32H7 rev.B and above
668 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n
669 * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n
670 * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n
671 * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n
672 * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n
673 * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n
674 * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n
675 * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n
676 * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n
677 * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n
678 * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n
679 * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs
680 * @param Break This parameter can be a combination of the following values:
681 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
682 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
683 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
684 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
685 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
686 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
687 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
688 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
689 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
690 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
691 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
692 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
693 * @retval None
694 * (*) value not defined in all devices
695 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)696 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
697 {
698 #if defined(DUAL_CORE)
699 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
700 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
701 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break);
702 #elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
703 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
704 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
705 SYSCFG_CFGR_PVDL, Break);
706 #elif defined(SYSCFG_CFGR_AXISRAML)
707 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
708 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\
709 Break);
710 #else
711 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\
712 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \
713 SYSCFG_CFGR_PVDL, Break);
714 #endif /* DUAL_CORE */
715 }
716
717 /**
718 * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs
719 * @note this feature is available on STM32H7 rev.B and above
720 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n
721 * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n
722 * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n
723 * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n
724 * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n
725 * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n
726 * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n
727 * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n
728 * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n
729 * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n
730 * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n
731 * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs
732 * @retval Returned value can be can be a combination of the following values:
733 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC
734 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC
735 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC
736 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC
737 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC
738 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*)
739 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC
740 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC
741 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP
742 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC
743 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
744 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)
745 * (*) value not defined in all devices
746 */
LL_SYSCFG_GetTIMBreakInputs(void)747 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
748 {
749 #if defined(DUAL_CORE)
750 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
751 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
752 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
753 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L));
754 #elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L)
755 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
756 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \
757 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
758 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
759 #elif defined (SYSCFG_CFGR_AXISRAML)
760 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \
761 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \
762 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \
763 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
764 #else
765 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \
766 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL ));
767 #endif /* DUAL_CORE */
768 }
769
770 /**
771 * @brief Enable the Compensation Cell
772 * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell
773 * @note The I/O compensation cell can be used only when the device supply
774 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
775 * @retval None
776 */
LL_SYSCFG_EnableCompensationCell(void)777 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
778 {
779 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
780 }
781
782 /**
783 * @brief Disable the Compensation Cell
784 * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell
785 * @note The I/O compensation cell can be used only when the device supply
786 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
787 * @retval None
788 */
LL_SYSCFG_DisableCompensationCell(void)789 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
790 {
791 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
792 }
793
794 /**
795 * @brief Check if the Compensation Cell is enabled
796 * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell
797 * @retval State of bit (1 or 0).
798 */
LL_SYSCFG_IsEnabledCompensationCell(void)799 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)
800 {
801 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);
802 }
803
804 /**
805 * @brief Get Compensation Cell ready Flag
806 * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR
807 * @retval State of bit (1 or 0).
808 */
LL_SYSCFG_IsActiveFlag_CMPCR(void)809 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
810 {
811 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);
812 }
813
814 /**
815 * @brief Enable the I/O speed optimization when the product voltage is low.
816 * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize
817 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
818 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
819 * might be destructive.
820 * @retval None
821 */
LL_SYSCFG_EnableIOSpeedOptimization(void)822 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)
823 {
824 #if defined(SYSCFG_CCCSR_HSLV)
825 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
826 #else
827 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
828 #endif /* SYSCFG_CCCSR_HSLV */
829 }
830
831 #if defined(SYSCFG_CCCSR_HSLV1)
832 /**
833 * @brief Enable the I/O speed optimization when the product voltage is low.
834 * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize
835 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
836 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
837 * might be destructive.
838 * @retval None
839 */
LL_SYSCFG_EnableIOSpeedOptimization1(void)840 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)
841 {
842 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
843 }
844
845 /**
846 * @brief Enable the I/O speed optimization when the product voltage is low.
847 * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize
848 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
849 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
850 * might be destructive.
851 * @retval None
852 */
LL_SYSCFG_EnableIOSpeedOptimization2(void)853 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)
854 {
855 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
856 }
857
858 /**
859 * @brief Enable the I/O speed optimization when the product voltage is low.
860 * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize
861 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
862 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
863 * might be destructive.
864 * @retval None
865 */
LL_SYSCFG_EnableIOSpeedOptimization3(void)866 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)
867 {
868 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
869 }
870 #endif /*SYSCFG_CCCSR_HSLV1*/
871
872
873 /**
874 * @brief To Disable optimize the I/O speed when the product voltage is low.
875 * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize
876 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
877 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
878 * might be destructive.
879 * @retval None
880 */
LL_SYSCFG_DisableIOSpeedOptimization(void)881 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)
882 {
883 #if defined(SYSCFG_CCCSR_HSLV)
884 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
885 #else
886 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);
887 #endif /* SYSCFG_CCCSR_HSLV */
888 }
889
890 #if defined(SYSCFG_CCCSR_HSLV1)
891 /**
892 * @brief To Disable optimize the I/O speed when the product voltage is low.
893 * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize
894 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
895 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
896 * might be destructive.
897 * @retval None
898 */
LL_SYSCFG_DisableIOSpeedOptimization1(void)899 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)
900 {
901 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);
902 }
903
904 /**
905 * @brief To Disable optimize the I/O speed when the product voltage is low.
906 * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize
907 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
908 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
909 * might be destructive.
910 * @retval None
911 */
LL_SYSCFG_DisableIOSpeedOptimization2(void)912 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)
913 {
914 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);
915 }
916
917 /**
918 * @brief To Disable optimize the I/O speed when the product voltage is low.
919 * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize
920 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the
921 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V
922 * might be destructive.
923 * @retval None
924 */
LL_SYSCFG_DisableIOSpeedOptimization3(void)925 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)
926 {
927 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);
928 }
929 #endif /*SYSCFG_CCCSR_HSLV1*/
930
931 /**
932 * @brief Check if the I/O speed optimization is enabled
933 * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization
934 * @retval State of bit (1 or 0).
935 */
LL_SYSCFG_IsEnabledIOSpeedOptimization(void)936 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)
937 {
938 #if defined(SYSCFG_CCCSR_HSLV)
939 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);
940 #else
941 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);
942 #endif /*SYSCFG_CCCSR_HSLV*/
943 }
944
945 #if defined(SYSCFG_CCCSR_HSLV1)
946 /**
947 * @brief Check if the I/O speed optimization is enabled
948 * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization
949 * @retval State of bit (1 or 0).
950 */
LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)951 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)
952 {
953 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);
954 }
955
956 /**
957 * @brief Check if the I/O speed optimization is enabled
958 * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization
959 * @retval State of bit (1 or 0).
960 */
LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)961 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)
962 {
963 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);
964 }
965
966 /**
967 * @brief Check if the I/O speed optimization is enabled
968 * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization
969 * @retval State of bit (1 or 0).
970 */
LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)971 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)
972 {
973 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);
974 }
975 #endif /*SYSCFG_CCCSR_HSLV1*/
976
977 /**
978 * @brief Set the code selection for the I/O Compensation cell
979 * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode
980 * @param CompCode: Selects the code to be applied for the I/O compensation cell
981 * This parameter can be one of the following values:
982 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
983 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
984 * @retval None
985 */
LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)986 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)
987 {
988 SET_BIT(SYSCFG->CCCSR, CompCode);
989 }
990
991 /**
992 * @brief Get the code selected for the I/O Compensation cell
993 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
994 * @retval Returned value can be one of the following values:
995 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
996 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
997 */
LL_SYSCFG_GetCellCompensationCode(void)998 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)
999 {
1000 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));
1001 }
1002
1003 #ifdef SYSCFG_CCCSR_CS_MMC
1004
1005 /**
1006 * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail
1007 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode
1008 * @retval Returned value can be one of the following values:
1009 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1010 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1011 */
LL_SYSCFG_MMCGetCellCompensationCode(void)1012 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)
1013 {
1014 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));
1015 }
1016 #endif /*SYSCFG_CCCSR_CS_MMC*/
1017
1018 /**
1019 * @brief Get I/O compensation cell value for PMOS transistors
1020 * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue
1021 * @retval Returned value is the I/O compensation cell value for PMOS transistors
1022 */
LL_SYSCFG_GetPMOSCompensationValue(void)1023 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)
1024 {
1025 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));
1026 }
1027
1028 /**
1029 * @brief Get I/O compensation cell value for NMOS transistors
1030 * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue
1031 * @retval Returned value is the I/O compensation cell value for NMOS transistors
1032 */
LL_SYSCFG_GetNMOSCompensationValue(void)1033 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)
1034 {
1035 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));
1036 }
1037
1038 /**
1039 * @brief Set I/O compensation cell code for PMOS transistors
1040 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1041 * @param PMOSCode PMOS compensation code
1042 * This code is applied to the I/O compensation cell when the CS bit of the
1043 * SYSCFG_CMPCR is set
1044 * @retval None
1045 */
LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)1046 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)
1047 {
1048 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);
1049 }
1050
1051 /**
1052 * @brief Get I/O compensation cell code for PMOS transistors
1053 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1054 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1055 */
LL_SYSCFG_GetPMOSCompensationCode(void)1056 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)
1057 {
1058 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));
1059 }
1060
1061 #ifdef SYSCFG_CCCR_PCC_MMC
1062
1063 /**
1064 * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1065 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode
1066 * @param PMOSCode PMOS compensation code
1067 * This code is applied to the I/O compensation cell when the CS bit of the
1068 * SYSCFG_CMPCR is set
1069 * @retval None
1070 */
LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)1071 __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)
1072 {
1073 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);
1074 }
1075
1076 /**
1077 * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail
1078 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode
1079 * @retval Returned value is the I/O compensation cell code for PMOS transistors
1080 */
LL_SYSCFG_MMCGetPMOSCompensationCode(void)1081 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)
1082 {
1083 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));
1084 }
1085 #endif /* SYSCFG_CCCR_PCC_MMC */
1086
1087 /**
1088 * @brief Set I/O compensation cell code for NMOS transistors
1089 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1090 * @param NMOSCode NMOS compensation code
1091 * This code is applied to the I/O compensation cell when the CS bit of the
1092 * SYSCFG_CMPCR is set
1093 * @retval None
1094 */
LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)1095 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)
1096 {
1097 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);
1098 }
1099
1100 /**
1101 * @brief Get I/O compensation cell code for NMOS transistors
1102 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1103 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1104 */
LL_SYSCFG_GetNMOSCompensationCode(void)1105 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)
1106 {
1107 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));
1108 }
1109
1110 #ifdef SYSCFG_CCCR_NCC_MMC
1111
1112 /**
1113 * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1114 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode
1115 * @param NMOSCode: NMOS compensation code
1116 * This code is applied to the I/O compensation cell when the CS bit of the
1117 * SYSCFG_CMPCR is set
1118 * @retval None
1119 */
LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)1120 __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)
1121 {
1122 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);
1123 }
1124
1125 /**
1126 * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.
1127 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode
1128 * @retval Returned value is the I/O compensation cell code for NMOS transistors
1129 */
LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)1130 __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)
1131 {
1132 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));
1133 }
1134 #endif /*SYSCFG_CCCR_NCC_MMC*/
1135
1136 #ifdef SYSCFG_PKGR_PKG
1137 /**
1138 * @brief Get the device package
1139 * @rmtoll PKGR PKG LL_SYSCFG_GetPackage
1140 * @retval Returned value can be one of the following values:
1141 * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*)
1142 * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*)
1143 * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*)
1144 * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*)
1145 * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*)
1146 * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*)
1147 * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**)
1148 * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**)
1149 * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**)
1150 * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**)
1151 * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**)
1152 * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**)
1153 * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**)
1154 * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**)
1155 * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**)
1156 *
1157 * (*) : For stm32h74xxx and stm32h75xxx family lines.
1158 * (**): For stm32h72xxx and stm32h73xxx family lines.
1159 */
LL_SYSCFG_GetPackage(void)1160 __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)
1161 {
1162 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));
1163 }
1164 #endif /*SYSCFG_PKGR_PKG*/
1165
1166 #ifdef SYSCFG_UR0_RDP
1167 /**
1168 * @brief Get the Flash memory protection level
1169 * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel
1170 * @retval Returned value can be one of the following values:
1171 * 0xAA : RDP level 0
1172 * 0xCC : RDP level 2
1173 * Any other value : RDP level 1
1174 */
LL_SYSCFG_GetFLashProtectionLevel(void)1175 __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)
1176 {
1177 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));
1178 }
1179 #ifdef SYSCFG_UR0_BKS
1180 /**
1181 * @brief Indicate if the Flash memory bank addresses are inverted or not
1182 * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped
1183 * @retval State of bit (1 or 0).
1184 */
LL_SYSCFG_IsFLashBankAddressesSwaped(void)1185 __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)
1186 {
1187 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);
1188 }
1189 #endif /*SYSCFG_UR0_BKS*/
1190
1191 /**
1192 * @brief Get the BOR Threshold Reset Level
1193 * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel
1194 * @retval Returned value can be one of the following values:
1195 * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL
1196 * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL
1197 * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL
1198 * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL
1199 */
LL_SYSCFG_GetBrownoutResetLevel(void)1200 __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)
1201 {
1202 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));
1203 }
1204 /**
1205 * @brief BootCM7 address 0 configuration
1206 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0
1207 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0
1208 * @retval None
1209 */
LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)1210 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)
1211 {
1212 /* Configure CM7 BOOT ADD0 */
1213 #if defined(DUAL_CORE)
1214 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));
1215 #else
1216 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));
1217 #endif /*DUAL_CORE*/
1218
1219 }
1220
1221 /**
1222 * @brief Get BootCM7 address 0
1223 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0
1224 * @retval Returned the CM7 Boot Address0
1225 */
LL_SYSCFG_GetCM7BootAddress0(void)1226 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)
1227 {
1228 /* Get CM7 BOOT ADD0 */
1229 #if defined(DUAL_CORE)
1230 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);
1231 #else
1232 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);
1233 #endif /*DUAL_CORE*/
1234 }
1235
1236 /**
1237 * @brief BootCM7 address 1 configuration
1238 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1
1239 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1
1240 * @retval None
1241 */
LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)1242 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)
1243 {
1244 /* Configure CM7 BOOT ADD1 */
1245 #if defined(DUAL_CORE)
1246 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);
1247 #else
1248 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);
1249 #endif /*DUAL_CORE*/
1250 }
1251
1252 /**
1253 * @brief Get BootCM7 address 1
1254 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1
1255 * @retval Returned the CM7 Boot Address0
1256 */
LL_SYSCFG_GetCM7BootAddress1(void)1257 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)
1258 {
1259 /* Get CM7 BOOT ADD0 */
1260 #if defined(DUAL_CORE)
1261 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));
1262 #else
1263 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));
1264 #endif /* DUAL_CORE */
1265 }
1266
1267 #if defined(DUAL_CORE)
1268 /**
1269 * @brief BootCM4 address 0 configuration
1270 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0
1271 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0
1272 * @retval None
1273 */
LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)1274 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)
1275 {
1276 /* Configure CM4 BOOT ADD0 */
1277 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));
1278 }
1279
1280 /**
1281 * @brief Get BootCM4 address 0
1282 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0
1283 * @retval Returned the CM4 Boot Address0
1284 */
LL_SYSCFG_GetCM4BootAddress0(void)1285 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)
1286 {
1287 /* Get CM4 BOOT ADD0 */
1288 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);
1289 }
1290
1291 /**
1292 * @brief BootCM4 address 1 configuration
1293 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1
1294 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1
1295 * @retval None
1296 */
LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)1297 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)
1298 {
1299 /* Configure CM4 BOOT ADD1 */
1300 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);
1301 }
1302
1303 /**
1304 * @brief Get BootCM4 address 1
1305 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1
1306 * @retval Returned the CM4 Boot Address0
1307 */
LL_SYSCFG_GetCM4BootAddress1(void)1308 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)
1309 {
1310 /* Get CM4 BOOT ADD0 */
1311 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));
1312 }
1313 #endif /*DUAL_CORE*/
1314
1315 /**
1316 * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase
1317 * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable
1318 * @retval State of bit (1 or 0).
1319 */
LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)1320 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)
1321 {
1322 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);
1323 }
1324
1325 /**
1326 * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase
1327 * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable
1328 * @retval State of bit (1 or 0).
1329 */
LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)1330 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)
1331 {
1332 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);
1333 }
1334
1335 /**
1336 * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected
1337 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected
1338 * @retval State of bit (1 or 0).
1339 */
LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)1340 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)
1341 {
1342 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1343 }
1344
1345 /**
1346 * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected
1347 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected
1348 * @retval State of bit (1 or 0).
1349 */
LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)1350 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)
1351 {
1352 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1353 }
1354
1355 /**
1356 * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected
1357 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected
1358 * @retval State of bit (1 or 0).
1359 */
LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)1360 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)
1361 {
1362 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1363 }
1364
1365 /**
1366 * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected
1367 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected
1368 * @retval State of bit (1 or 0).
1369 */
LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)1370 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)
1371 {
1372 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1373 }
1374
1375 /**
1376 * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected
1377 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected
1378 * @retval State of bit (1 or 0).
1379 */
LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)1380 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)
1381 {
1382 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1383 }
1384
1385 /**
1386 * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected
1387 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected
1388 * @retval State of bit (1 or 0).
1389 */
LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)1390 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)
1391 {
1392 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1393 }
1394
1395 /**
1396 * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected
1397 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected
1398 * @retval State of bit (1 or 0).
1399 */
LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)1400 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)
1401 {
1402 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1403 }
1404
1405 /**
1406 * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected
1407 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected
1408 * @retval State of bit (1 or 0).
1409 */
LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)1410 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)
1411 {
1412 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Get the protected area start address for Flash bank 1
1417 * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress
1418 * @retval Returned the protected area start address for Flash bank 1
1419 */
LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)1420 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)
1421 {
1422 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));
1423 }
1424
1425 /**
1426 * @brief Get the protected area end address for Flash bank 1
1427 * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress
1428 * @retval Returned the protected area end address for Flash bank 1
1429 */
LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)1430 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)
1431 {
1432 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));
1433 }
1434
1435 /**
1436 * @brief Get the secured area start address for Flash bank 1
1437 * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress
1438 * @retval Returned the secured area start address for Flash bank 1
1439 */
LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)1440 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)
1441 {
1442 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));
1443 }
1444
1445 /**
1446 * @brief Get the secured area end address for Flash bank 1
1447 * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress
1448 * @retval Returned the secured area end address for Flash bank 1
1449 */
LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)1450 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)
1451 {
1452 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));
1453 }
1454
1455 #ifdef SYSCFG_UR8_MEPAD_BANK2
1456 /**
1457 * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase
1458 * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable
1459 * @retval State of bit (1 or 0).
1460 */
LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)1461 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)
1462 {
1463 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);
1464 }
1465
1466 /**
1467 * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase
1468 * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable
1469 * @retval State of bit (1 or 0).
1470 */
LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)1471 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)
1472 {
1473 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);
1474 }
1475 #endif /*SYSCFG_UR8_MEPAD_BANK2*/
1476
1477 #ifdef SYSCFG_UR9_WRPN_BANK2
1478 /**
1479 * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected
1480 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected
1481 * @retval State of bit (1 or 0).
1482 */
LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)1483 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)
1484 {
1485 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);
1486 }
1487
1488 /**
1489 * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected
1490 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected
1491 * @retval State of bit (1 or 0).
1492 */
LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)1493 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)
1494 {
1495 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);
1496 }
1497
1498 /**
1499 * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected
1500 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected
1501 * @retval State of bit (1 or 0).
1502 */
LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)1503 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)
1504 {
1505 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);
1506 }
1507
1508 /**
1509 * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected
1510 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected
1511 * @retval State of bit (1 or 0).
1512 */
LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)1513 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)
1514 {
1515 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);
1516 }
1517
1518 /**
1519 * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected
1520 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected
1521 * @retval State of bit (1 or 0).
1522 */
LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)1523 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)
1524 {
1525 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);
1526 }
1527
1528 /**
1529 * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected
1530 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected
1531 * @retval State of bit (1 or 0).
1532 */
LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)1533 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)
1534 {
1535 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);
1536 }
1537
1538 /**
1539 * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected
1540 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected
1541 * @retval State of bit (1 or 0).
1542 */
LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)1543 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)
1544 {
1545 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);
1546 }
1547
1548 /**
1549 * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected
1550 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected
1551 * @retval State of bit (1 or 0).
1552 */
LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)1553 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)
1554 {
1555 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);
1556 }
1557
1558 /**
1559 * @brief Get the protected area start address for Flash bank 2
1560 * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress
1561 * @retval Returned the protected area start address for Flash bank 2
1562 */
LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)1563 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)
1564 {
1565 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));
1566 }
1567 #endif /*SYSCFG_UR9_WRPN_BANK2*/
1568
1569 #ifdef SYSCFG_UR10_PAEND_BANK2
1570 /**
1571 * @brief Get the protected area end address for Flash bank 2
1572 * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress
1573 * @retval Returned the protected area end address for Flash bank 2
1574 */
LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)1575 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)
1576 {
1577 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));
1578 }
1579
1580 /**
1581 * @brief Get the secured area start address for Flash bank 2
1582 * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress
1583 * @retval Returned the secured area start address for Flash bank 2
1584 */
LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)1585 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)
1586 {
1587 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));
1588 }
1589 #endif /*SYSCFG_UR10_PAEND_BANK2*/
1590
1591 #ifdef SYSCFG_UR11_SAEND_BANK2
1592 /**
1593 * @brief Get the secured area end address for Flash bank 2
1594 * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress
1595 * @retval Returned the secured area end address for Flash bank 2
1596 */
LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)1597 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)
1598 {
1599 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));
1600 }
1601 #endif /*SYSCFG_UR11_SAEND_BANK2*/
1602
1603 /**
1604 * @brief Get the Independent Watchdog 1 control mode (Software or Hardware)
1605 * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode
1606 * @retval Returned value can be one of the following values:
1607 * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE
1608 * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE
1609 */
LL_SYSCFG_GetIWDG1ControlMode(void)1610 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)
1611 {
1612 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));
1613 }
1614
1615 #if defined (DUAL_CORE)
1616 /**
1617 * @brief Get the Independent Watchdog 2 control mode (Software or Hardware)
1618 * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode
1619 * @retval Returned value can be one of the following values:
1620 * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE
1621 * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE
1622 */
LL_SYSCFG_GetIWDG2ControlMode(void)1623 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)
1624 {
1625 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));
1626 }
1627 #endif /* DUAL_CORE */
1628
1629 /**
1630 * @brief Indicates the Secure mode status
1631 * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled
1632 * @retval State of bit (1 or 0).
1633 */
LL_SYSCFG_IsSecureModeEnabled(void)1634 __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)
1635 {
1636 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);
1637 }
1638
1639 /**
1640 * @brief Indicates if a reset is generated when D1 domain enters DStandby mode
1641 * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset
1642 * @retval State of bit (1 or 0).
1643 */
LL_SYSCFG_IsD1StandbyGenerateReset(void)1644 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)
1645 {
1646 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);
1647 }
1648
1649 /**
1650 * @brief Get the secured DTCM RAM size
1651 * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize
1652 * @retval Returned value can be one of the following values:
1653 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB
1654 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB
1655 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB
1656 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB
1657 */
LL_SYSCFG_GetSecuredDTCMSize(void)1658 __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)
1659 {
1660 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));
1661 }
1662
1663 /**
1664 * @brief Indicates if a reset is generated when D1 domain enters DStop mode
1665 * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset
1666 * @retval State of bit (1 or 0).
1667 */
LL_SYSCFG_IsD1StopGenerateReset(void)1668 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)
1669 {
1670 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);
1671 }
1672
1673 #if defined (DUAL_CORE)
1674 /**
1675 * @brief Indicates if a reset is generated when D2 domain enters DStandby mode
1676 * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset
1677 * @retval State of bit (1 or 0).
1678 */
LL_SYSCFG_IsD2StandbyGenerateReset(void)1679 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)
1680 {
1681 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);
1682 }
1683
1684 /**
1685 * @brief Indicates if a reset is generated when D2 domain enters DStop mode
1686 * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset
1687 * @retval State of bit (1 or 0).
1688 */
LL_SYSCFG_IsD2StopGenerateReset(void)1689 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)
1690 {
1691 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);
1692 }
1693 #endif /* DUAL_CORE */
1694
1695 /**
1696 * @brief Indicates if the independent watchdog is frozen in Standby mode
1697 * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode
1698 * @retval State of bit (1 or 0).
1699 */
LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)1700 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)
1701 {
1702 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);
1703 }
1704
1705 /**
1706 * @brief Indicates if the independent watchdog is frozen in Stop mode
1707 * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode
1708 * @retval State of bit (1 or 0).
1709 */
LL_SYSCFG_IsIWDGFrozenInStopMode(void)1710 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)
1711 {
1712 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);
1713 }
1714
1715 /**
1716 * @brief Indicates if the device private key is programmed
1717 * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed
1718 * @retval State of bit (1 or 0).
1719 */
LL_SYSCFG_IsPrivateKeyProgrammed(void)1720 __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)
1721 {
1722 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);
1723 }
1724
1725 /**
1726 * @brief Indicates if the Product is working on the full voltage range or not
1727 * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV
1728 * @note When the IOHSLV option bit is set the Product is working below 2.7 V.
1729 * When the IOHSLV option bit is reset the Product is working on the
1730 * full voltage range.
1731 * @retval State of bit (1 or 0).
1732 */
LL_SYSCFG_IsActiveFlag_IOHSLV(void)1733 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)
1734 {
1735 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);
1736 }
1737
1738 #ifdef SYSCFG_UR17_TCM_AXI_CFG
1739 /**
1740 * @brief Get the size of ITCM-RAM and AXI-SRAM
1741 * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size
1742 * @retval Returned value can be one of the following values:
1743 * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB
1744 * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB
1745 * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB
1746 * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB
1747 */
LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)1748 __STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void)
1749 {
1750 return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG));
1751 }
1752 #endif /*SYSCFG_UR17_TCM_AXI_CFG*/
1753
1754 #ifdef SYSCFG_UR18_CPU_FREQ_BOOST
1755 /**
1756 * @brief Indicates if the CPU maximum frequency boost is enabled
1757 * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled
1758 * @retval State of bit (1 or 0).
1759 */
LL_SYSCFG_IsCpuFreqBoostEnabled(void)1760 __STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void)
1761 {
1762 return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL);
1763 }
1764 #endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/
1765
1766 #endif /*SYSCFG_UR0_RDP*/
1767
1768 /**
1769 * @}
1770 */
1771
1772 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1773 * @{
1774 */
1775
1776 /**
1777 * @brief Return the device identifier
1778 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1779 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1780 */
LL_DBGMCU_GetDeviceID(void)1781 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1782 {
1783 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1784 }
1785
1786 /**
1787 * @brief Return the device revision identifier
1788 * @note This field indicates the revision of the device.
1789 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
1790 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1791 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1792 */
LL_DBGMCU_GetRevisionID(void)1793 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1794 {
1795 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1796 }
1797
1798 /**
1799 * @brief Enable D1 Domain/CDomain debug during SLEEP mode
1800 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode
1801 * @retval None
1802 */
LL_DBGMCU_EnableD1DebugInSleepMode(void)1803 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)
1804 {
1805 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1806 }
1807
1808 /**
1809 * @brief Disable D1 Domain/CDomain debug during SLEEP mode
1810 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode
1811 * @retval None
1812 */
LL_DBGMCU_DisableD1DebugInSleepMode(void)1813 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)
1814 {
1815 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
1816 }
1817
1818 /**
1819 * @brief Enable D1 Domain/CDomain debug during STOP mode
1820 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode
1821 * @retval None
1822 */
LL_DBGMCU_EnableD1DebugInStopMode(void)1823 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)
1824 {
1825 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1826 }
1827
1828 /**
1829 * @brief Disable D1 Domain/CDomain debug during STOP mode
1830 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode
1831 * @retval None
1832 */
LL_DBGMCU_DisableD1DebugInStopMode(void)1833 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)
1834 {
1835 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
1836 }
1837
1838 /**
1839 * @brief Enable D1 Domain/CDomain debug during STANDBY mode
1840 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode
1841 * @retval None
1842 */
LL_DBGMCU_EnableD1DebugInStandbyMode(void)1843 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)
1844 {
1845 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1846 }
1847
1848 /**
1849 * @brief Disable D1 Domain/CDomain debug during STANDBY mode
1850 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode
1851 * @retval None
1852 */
LL_DBGMCU_DisableD1DebugInStandbyMode(void)1853 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)
1854 {
1855 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
1856 }
1857
1858 #if defined (DUAL_CORE)
1859 /**
1860 * @brief Enable D2 Domain debug during SLEEP mode
1861 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode
1862 * @retval None
1863 */
LL_DBGMCU_EnableD2DebugInSleepMode(void)1864 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)
1865 {
1866 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1867 }
1868
1869 /**
1870 * @brief Disable D2 Domain debug during SLEEP mode
1871 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode
1872 * @retval None
1873 */
LL_DBGMCU_DisableD2DebugInSleepMode(void)1874 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)
1875 {
1876 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
1877 }
1878
1879 /**
1880 * @brief Enable D2 Domain debug during STOP mode
1881 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode
1882 * @retval None
1883 */
LL_DBGMCU_EnableD2DebugInStopMode(void)1884 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)
1885 {
1886 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1887 }
1888
1889 /**
1890 * @brief Disable D2 Domain debug during STOP mode
1891 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode
1892 * @retval None
1893 */
LL_DBGMCU_DisableD2DebugInStopMode(void)1894 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)
1895 {
1896 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
1897 }
1898
1899 /**
1900 * @brief Enable D2 Domain debug during STANDBY mode
1901 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode
1902 * @retval None
1903 */
LL_DBGMCU_EnableD2DebugInStandbyMode(void)1904 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)
1905 {
1906 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1907 }
1908
1909 /**
1910 * @brief Disable D2 Domain debug during STANDBY mode
1911 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode
1912 * @retval None
1913 */
LL_DBGMCU_DisableD2DebugInStandbyMode(void)1914 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)
1915 {
1916 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1917 }
1918 #endif /* DUAL_CORE */
1919
1920
1921 #if defined(DBGMCU_CR_DBG_STOPD3)
1922 /**
1923 * @brief Enable D3 Domain/SRDomain debug during STOP mode
1924 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode
1925 * @retval None
1926 */
LL_DBGMCU_EnableD3DebugInStopMode(void)1927 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)
1928 {
1929 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1930 }
1931
1932 /**
1933 * @brief Disable D3 Domain/SRDomain debug during STOP mode
1934 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode
1935 * @retval None
1936 */
LL_DBGMCU_DisableD3DebugInStopMode(void)1937 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)
1938 {
1939 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1940 }
1941 #endif /*DBGMCU_CR_DBG_STOPD3*/
1942
1943 #if defined(DBGMCU_CR_DBG_STANDBYD3)
1944 /**
1945 * @brief Enable D3 Domain/SRDomain debug during STANDBY mode
1946 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode
1947 * @retval None
1948 */
LL_DBGMCU_EnableD3DebugInStandbyMode(void)1949 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)
1950 {
1951 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1952 }
1953
1954 /**
1955 * @brief Disable D3 Domain/SRDomain debug during STANDBY mode
1956 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode
1957 * @retval None
1958 */
LL_DBGMCU_DisableD3DebugInStandbyMode(void)1959 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)
1960 {
1961 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1962 }
1963 #endif /*DBGMCU_CR_DBG_STANDBYD3*/
1964
1965 /**
1966 * @brief Enable the trace port clock
1967 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock
1968 * @retval None
1969 */
LL_DBGMCU_EnableTracePortClock(void)1970 __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)
1971 {
1972 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1973 }
1974
1975 /**
1976 * @brief Disable the trace port clock
1977 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock
1978 * @retval None
1979 */
LL_DBGMCU_DisableTracePortClock(void)1980 __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)
1981 {
1982 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);
1983 }
1984
1985 /**
1986 * @brief Enable the Domain1/CDomain debug clock enable
1987 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock
1988 * @retval None
1989 */
LL_DBGMCU_EnableD1DebugClock(void)1990 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)
1991 {
1992 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
1993 }
1994
1995 /**
1996 * @brief Disable the Domain1/CDomain debug clock enable
1997 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock
1998 * @retval None
1999 */
LL_DBGMCU_DisableD1DebugClock(void)2000 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)
2001 {
2002 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);
2003 }
2004
2005 /**
2006 * @brief Enable the Domain3/SRDomain debug clock enable
2007 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock
2008 * @retval None
2009 */
LL_DBGMCU_EnableD3DebugClock(void)2010 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)
2011 {
2012 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2013 }
2014
2015 /**
2016 * @brief Disable the Domain3/SRDomain debug clock enable
2017 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock
2018 * @retval None
2019 */
LL_DBGMCU_DisableD3DebugClock(void)2020 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)
2021 {
2022 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);
2023 }
2024
2025 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U
2026 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN
2027 /**
2028 * @brief Set the direction of the bi-directional trigger pin TRGIO
2029 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n
2030 * @param PinDirection This parameter can be one of the following values:
2031 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
2032 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
2033 * @retval None
2034 */
LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)2035 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)
2036 {
2037 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);
2038 }
2039
2040 /**
2041 * @brief Get the direction of the bi-directional trigger pin TRGIO
2042 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n
2043 * @retval Returned value can be one of the following values:
2044 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION
2045 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION
2046 */
LL_DBGMCU_GetExternalTriggerPinDirection(void)2047 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)
2048 {
2049 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));
2050 }
2051
2052 /**
2053 * @brief Freeze APB1 group1 peripherals
2054 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2055 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2056 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2057 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2058 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2059 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2060 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2061 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2062 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2063 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2064 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2065 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2066 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2067 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*)
2068 * @param Periphs This parameter can be a combination of the following values:
2069 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
2070 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
2071 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
2072 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
2073 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
2074 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
2075 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
2076 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
2077 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
2078 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
2079 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
2080 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
2081 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
2082 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
2083 *
2084 * (*) value not defined in all devices
2085 * @retval None
2086 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)2087 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
2088 {
2089 SET_BIT(DBGMCU->APB1LFZ1, Periphs);
2090 }
2091
2092 /**
2093 * @brief Unfreeze APB1 peripherals (group1 peripherals)
2094 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2095 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2096 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2097 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2098 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2099 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2100 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2101 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2102 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2103 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2104 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2105 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2106 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2107 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n
2108 * @param Periphs This parameter can be a combination of the following values:
2109 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
2110 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
2111 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
2112 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
2113 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
2114 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
2115 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
2116 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
2117 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
2118 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
2119 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
2120 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
2121 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
2122 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*)
2123 *
2124 * (*) value not defined in all devices
2125 * @retval None
2126 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)2127 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
2128 {
2129 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
2130 }
2131
2132 #ifdef DBGMCU_APB1HFZ1_DBG_FDCAN
2133 /**
2134 * @brief Freeze APB1 group2 peripherals
2135 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2136 * @param Periphs This parameter can be a combination of the following values:
2137 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2138 * @retval None
2139 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)2140 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2141 {
2142 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2143 }
2144
2145 /**
2146 * @brief Unfreeze APB1 group2 peripherals
2147 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2148 * @param Periphs This parameter can be a combination of the following values:
2149 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
2150 * @retval None
2151 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)2152 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2153 {
2154 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2155 }
2156 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/
2157
2158 #if defined(TIM23) || defined(TIM24)
2159 /**
2160 * @brief Freeze APB1 group2 peripherals
2161 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2162 * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n
2163 * @param Periphs This parameter can be a combination of the following values:
2164 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
2165 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
2166 * @retval None
2167 */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)2168 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
2169 {
2170 SET_BIT(DBGMCU->APB1HFZ1, Periphs);
2171 }
2172
2173 /**
2174 * @brief Unfreeze APB1 group2 peripherals
2175 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2176 DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
2177 * @param Periphs This parameter can be a combination of the following values:
2178 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP
2179 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP
2180 * @retval None
2181 */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)2182 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
2183 {
2184 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
2185 }
2186 #endif /* TIM23 || TIM24 */
2187
2188 /**
2189 * @brief Freeze APB2 peripherals
2190 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2191 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2192 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2193 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2194 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2195 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2196 * @param Periphs This parameter can be a combination of the following values:
2197 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2198 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2199 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2200 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2201 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2202 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
2203 *
2204 * (*) value not defined in all devices
2205 * @retval None
2206 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)2207 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
2208 {
2209 SET_BIT(DBGMCU->APB2FZ1, Periphs);
2210 }
2211
2212 /**
2213 * @brief Unfreeze APB2 peripherals
2214 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2215 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2216 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2217 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n
2218 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph
2219 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph
2220 * @param Periphs This parameter can be a combination of the following values:
2221 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
2222 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
2223 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
2224 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
2225 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
2226 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*)
2227 *
2228 * (*) value not defined in all devices
2229 * @retval None
2230 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)2231 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
2232 {
2233 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);
2234 }
2235
2236 /**
2237 * @brief Freeze APB3 peripherals
2238 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n
2239 * @param Periphs This parameter can be a combination of the following values:
2240 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2241 * @retval None
2242 */
LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)2243 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
2244 {
2245 SET_BIT(DBGMCU->APB3FZ1, Periphs);
2246 }
2247
2248 /**
2249 * @brief Unfreeze APB3 peripherals
2250 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n
2251 * @param Periphs This parameter can be a combination of the following values:
2252 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP
2253 * @retval None
2254 */
LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)2255 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
2256 {
2257 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);
2258 }
2259
2260 /**
2261 * @brief Freeze APB4 peripherals
2262 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2263 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2264 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2265 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2266 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2267 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2268 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2269 * @param Periphs This parameter can be a combination of the following values:
2270 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2271 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2272 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2273 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
2274 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
2275 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2276 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2277 *
2278 * (*) value not defined in all devices
2279 * @retval None
2280 */
LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)2281 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
2282 {
2283 SET_BIT(DBGMCU->APB4FZ1, Periphs);
2284 }
2285
2286 /**
2287 * @brief Unfreeze APB4 peripherals
2288 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2289 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2290 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2291 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2292 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2293 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2294 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n
2295 * @param Periphs This parameter can be a combination of the following values:
2296 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
2297 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
2298 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
2299 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*)
2300 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*)
2301 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
2302 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP
2303 *
2304 * (*) value not defined in all devices
2305 * @retval None
2306 */
LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)2307 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
2308 {
2309 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);
2310 }
2311 /**
2312 * @}
2313 */
2314
2315 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
2316 * @{
2317 */
2318
2319 /**
2320 * @brief Set FLASH Latency
2321 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
2322 * @param Latency This parameter can be one of the following values:
2323 * @arg @ref LL_FLASH_LATENCY_0
2324 * @arg @ref LL_FLASH_LATENCY_1
2325 * @arg @ref LL_FLASH_LATENCY_2
2326 * @arg @ref LL_FLASH_LATENCY_3
2327 * @arg @ref LL_FLASH_LATENCY_4
2328 * @arg @ref LL_FLASH_LATENCY_5
2329 * @arg @ref LL_FLASH_LATENCY_6
2330 * @arg @ref LL_FLASH_LATENCY_7
2331 * @retval None
2332 */
LL_FLASH_SetLatency(uint32_t Latency)2333 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2334 {
2335 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2336 }
2337
2338 /**
2339 * @brief Get FLASH Latency
2340 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
2341 * @retval Returned value can be one of the following values:
2342 * @arg @ref LL_FLASH_LATENCY_0
2343 * @arg @ref LL_FLASH_LATENCY_1
2344 * @arg @ref LL_FLASH_LATENCY_2
2345 * @arg @ref LL_FLASH_LATENCY_3
2346 * @arg @ref LL_FLASH_LATENCY_4
2347 * @arg @ref LL_FLASH_LATENCY_5
2348 * @arg @ref LL_FLASH_LATENCY_6
2349 * @arg @ref LL_FLASH_LATENCY_7
2350 */
LL_FLASH_GetLatency(void)2351 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2352 {
2353 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2354 }
2355
2356 /**
2357 * @}
2358 */
2359
2360 #if defined(DUAL_CORE)
2361 /** @defgroup SYSTEM_LL_EF_ART ART
2362 * @{
2363 */
2364
2365 /**
2366 * @brief Enable the Cortex-M4 ART cache.
2367 * @rmtoll ART_CTR EN LL_ART_Enable
2368 * @retval None
2369 */
LL_ART_Enable(void)2370 __STATIC_INLINE void LL_ART_Enable(void)
2371 {
2372 SET_BIT(ART->CTR, ART_CTR_EN);
2373 }
2374
2375 /**
2376 * @brief Disable the Cortex-M4 ART cache.
2377 * @rmtoll ART_CTR EN LL_ART_Disable
2378 * @retval None
2379 */
LL_ART_Disable(void)2380 __STATIC_INLINE void LL_ART_Disable(void)
2381 {
2382 CLEAR_BIT(ART->CTR, ART_CTR_EN);
2383 }
2384
2385 /**
2386 * @brief Check if the Cortex-M4 ART cache is enabled
2387 * @rmtoll ART_CTR EN LL_ART_IsEnabled
2388 * @retval State of bit (1 or 0).
2389 */
LL_ART_IsEnabled(void)2390 __STATIC_INLINE uint32_t LL_ART_IsEnabled(void)
2391 {
2392 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);
2393 }
2394
2395 /**
2396 * @brief Set the Cortex-M4 ART cache Base Address.
2397 * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress
2398 * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)
2399 from which the ART accelerator loads code to the cache.
2400 * @retval None
2401 */
LL_ART_SetBaseAddress(uint32_t BaseAddress)2402 __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)
2403 {
2404 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));
2405 }
2406
2407 /**
2408 * @brief Get the Cortex-M4 ART cache Base Address.
2409 * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress
2410 * @retval the Base address of 1 Mbyte address page (cacheable page)
2411 from which the ART accelerator loads code to the cache
2412 */
LL_ART_GetBaseAddress(void)2413 __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
2414 {
2415 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);
2416 }
2417 #endif /* DUAL_CORE */
2418
2419 /**
2420 * @}
2421 */
2422
2423 /**
2424 * @}
2425 */
2426
2427 /**
2428 * @}
2429 */
2430
2431 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
2432
2433 /**
2434 * @}
2435 */
2436
2437 #ifdef __cplusplus
2438 }
2439 #endif
2440
2441 #endif /* __STM32H7xx_LL_SYSTEM_H */
2442
2443
