1 /**
2   ******************************************************************************
3   * @file    stm32u5xx_ll_system.h
4   * @author  MCD Application Team
5   * @brief   Header file of SYSTEM LL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2021 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   @verbatim
18   ==============================================================================
19                      ##### How to use this driver #####
20   ==============================================================================
21     [..]
22     The LL SYSTEM driver contains a set of generic APIs that can be
23     used by user:
24       (+) Some of the FLASH features need to be handled in the SYSTEM file.
25       (+) Access to DBGCMU registers
26       (+) Access to SYSCFG registers
27       (+) Access to VREFBUF registers
28   @endverbatim
29   ******************************************************************************
30   */
31 
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef STM32U5xx_LL_SYSTEM_H
34 #define STM32U5xx_LL_SYSTEM_H
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32u5xx.h"
42 
43 /** @addtogroup STM32U5xx_LL_Driver
44   * @{
45   */
46 
47 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
48 
49 /** @defgroup SYSTEM_LL SYSTEM
50   * @{
51   */
52 
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55 
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58   * @{
59   */
60 
61 /**
62   * @brief Power-down in Run mode Flash key
63   */
64 #define LL_FLASH_PDKEY1_1                 0x04152637U /*!< Flash Bank1 power down key1 */
65 #define LL_FLASH_PDKEY1_2                 0xFAFBFCFDU /*!< Flash Bank1 power down key2: used with FLASH_PDKEY1
66                                                        to unlock the RUN_PD bit in FLASH_ACR */
67 
68 #define LL_FLASH_PDKEY2_1                 0x40516273U /*!< Flash Bank2 power down key1 */
69 #define LL_FLASH_PDKEY2_2                 0xAFBFCFDFU /*!< Flash Bank2 power down key2: used with FLASH_PDKEY2_1
70                                                        to unlock the RUN_PD bit in FLASH_ACR */
71 /**
72   * @}
73   */
74 
75 /** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
76   * @{
77   */
78 #define LL_SYSCFG_VDD_CELL_CODE                  0U               /*VDD I/Os code from the cell
79                                                                    (available in the SYSCFG_CCVR)*/
80 #define LL_SYSCFG_VDD_REGISTER_CODE              SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation
81                                                                    cell code register (SYSCFG_CCCR)*/
82 /**
83   * @}
84   */
85 
86 /** @defgroup SYSTEM_LL_EC_CS2 SYSCFG VddIO2 compensation cell Code selection
87   * @{
88   */
89 #define LL_SYSCFG_VDDIO2_CELL_CODE                0U               /*VDDIO2 I/Os code from the cell
90                                                                     (available in the SYSCFG_CCVR)*/
91 #define LL_SYSCFG_VDDIO2_REGISTER_CODE            SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation
92                                                                     cell code register (SYSCFG_CCCR)*/
93 /**
94   * @}
95   */
96 
97 #if defined(SYSCFG_CCCSR_CS3)
98 /** @defgroup SYSTEM_LL_EC_CS3 SYSCFG VddHSPI compensation cell Code selection
99   * @{
100   */
101 #define LL_SYSCFG_VDDHSPI_CELL_CODE                0U               /*VDD HSPI I/Os code from the cell
102                                                                     (available in the SYSCFG_CCVR)*/
103 #define LL_SYSCFG_VDDHSPI_REGISTER_CODE            SYSCFG_CCCSR_CS3 /*VDD HSPI I/Os code from the SYSCFG compensation
104                                                                     cell code register (SYSCFG_CCCR)*/
105 /**
106   * @}
107   */
108 #endif /* SYSCFG_CCCSR_CS3 */
109 
110 /** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS
111   * @{
112   */
113 #define LL_SYSCFG_MEMORIES_ERASE_ON_GOING         0U               /*Memory erase on going*/
114 #define LL_SYSCFG_MEMORIES_ERASE_ENDED            SYSCFG_MESR_MCLR /*Memory erase done */
115 /**
116   * @}
117   */
118 
119 /* Private macros ------------------------------------------------------------*/
120 
121 /* Exported types ------------------------------------------------------------*/
122 /* Exported constants --------------------------------------------------------*/
123 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
124   * @{
125   */
126 
127 /** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SYSCFG FASTMODEPLUS
128   * @{
129   */
130 #define LL_SYSCFG_FASTMODEPLUS_PB6     SYSCFG_CFGR1_PB6_FMP  /*!< Enable Fast Mode Plus on PB6 */
131 #define LL_SYSCFG_FASTMODEPLUS_PB7     SYSCFG_CFGR1_PB7_FMP  /*!< Enable Fast Mode Plus on PB7 */
132 #define LL_SYSCFG_FASTMODEPLUS_PB8     SYSCFG_CFGR1_PB8_FMP  /*!< Enable Fast Mode Plus on PB8 */
133 #define LL_SYSCFG_FASTMODEPLUS_PB9     SYSCFG_CFGR1_PB9_FMP  /*!< Enable Fast Mode Plus on PB9 */
134 /**
135   * @}
136   */
137 
138 #if defined(SYSCFG_CFGR1_ENDCAP)
139 /** @defgroup SYSTEM_LL_DECOUPLING_CAPACITANCE SYSCFG DECOUPLING CAPACITANCE
140   * @{
141   */
142 #define LL_SYSCFG_HSPI_CAPACITANCE_OFF       0x00000000U            /*!< Decoupling with no capacitance value on HSPI supply */
143 #define LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3   SYSCFG_CFGR1_ENDCAP_0  /*!< Decoupling with 1/3 of capacitance value on HSPI supply */
144 #define LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3   SYSCFG_CFGR1_ENDCAP_1  /*!< Decoupling with 2/3 of capacitance value on HSPI supply */
145 #define LL_SYSCFG_HSPI_CAPACITANCE_FULL      SYSCFG_CFGR1_ENDCAP    /*!< Decoupling with full capacitance value on HSPI supply */
146 /**
147   * @}
148   */
149 #endif /* SYSCFG_CFGR1_ENDCAP */
150 
151 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
152   * @{
153   */
154 #define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal
155                                                                    with Break Input of TIM1/8/15/16/17 */
156 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection
157                                                                    with TIM1/8/15/16/17 Break Input and also the PVDE
158                                                                    and PLS bits of the Power Control Interface */
159 #define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK   SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM ECC double error signal
160                                                                    with Break Input of TIM1/8/15/16/17 */
161 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM33
162                                                                    with Break Input of TIM1/15/16/17 */
163 /**
164   * @}
165   */
166 
167 #if defined(SYSCFG_OTGHSPHYCR_CLKSEL)
168 /** @defgroup SYSTEM_LL_OTG_PHY_CLOCK_FREQUENCY SYSCFG OTG High-speed (HS) PHY reference clock frequency selection
169   * @{
170   */
171 #define LL_SYSCFG_OTGHSPHY_CLK_16MHZ    (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1)    /*!< Reference clock freqeuncy is 16 Mhz */
172 #define LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ  (SYSCFG_OTGHSPHYCR_CLKSEL_3)                                 /*!< Reference clock freqeuncy is 19.2 Mhz */
173 #define LL_SYSCFG_OTGHSPHY_CLK_20MHZ    (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3)    /*!< Reference clock freqeuncy is 20 Mhz */
174 #define LL_SYSCFG_OTGHSPHY_CLK_24MHZ    (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3)    /*!< Reference clock freqeuncy is 24 Mhz */
175 #define LL_SYSCFG_OTGHSPHY_CLK_26MHZ    (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | \
176                                          SYSCFG_OTGHSPHYCR_CLKSEL_3)                                 /*!< Reference clock freqeuncy is 26 Mhz */
177 #define LL_SYSCFG_OTGHSPHY_CLK_32MHZ    (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | \
178                                          SYSCFG_OTGHSPHYCR_CLKSEL_3)                                 /*!< Reference clock freqeuncy is 32 Mhz */
179 /**
180   * @}
181   */
182 #endif /* SYSCFG_OTGHSPHYCR_CLKSEL */
183 
184 #if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)
185 /** @defgroup SYSTEM_LL_OTG_PHYTUNER_DISCONNECT_THRESTHOLD SYSCFG OTG High-speed (HS) PHYTUNER disconnnect threshold
186   * @{
187   */
188 #define LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT  SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1  /*!< +5.9% (recommended value) */
189 #define LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT    SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0  /*!< 0% (default value) */
190 /**
191   * @}
192   */
193 #endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */
194 
195 #if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)
196 /** @defgroup SYSTEM_LL_OTG_SQUELSH SYSCFG OTG High-speed (HS) PHY Squelch threshold adjustment
197   * @{
198   */
199 #define LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT  0x00000000U                                                            /*!< +15% (recommended value) */
200 #define LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT   (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1)  /*!< 0% (default value) */
201 /**
202   * @}
203   */
204 #endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */
205 
206 #if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)
207 /** @defgroup SYSTEM_LL_OTG_TRANSMITTER_PREEMPHASIS_CURRENT SYSCFG OTG High-speed (HS) transmitter preemphasis current control
208   * @{
209   */
210 #define LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED  0x00000000U                                 /*!< HS transmitter preemphasis circuit disabled */
211 #define LL_SYSCFG_OTGHSPHY_PREEMP_1X        SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0     /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */
212 #define LL_SYSCFG_OTGHSPHY_PREEMP_2X        SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1     /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */
213 #define LL_SYSCFG_OTGHSPHY_PREEMP_3X       (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | \
214                                             SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1)    /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */
215 /**
216   * @}
217   */
218 #endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */
219 
220 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items
221   * @{
222   */
223 #define LL_SYSCFG_MPU_NSEC        SYSCFG_CNSLCKR_LOCKNSMPU                    /*!< Non-secure MPU lock (privileged secure or non-secure only) */
224 #define LL_SYSCFG_VTOR_NSEC       SYSCFG_CNSLCKR_LOCKNSVTOR                   /*!< Non-secure VTOR lock (privileged secure or non-secure only) */
225 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
226 #define LL_SYSCFG_SAU             (SYSCFG_CSLCKR_LOCKSAU << 16U)              /*!< SAU lock (privileged secure code only) */
227 #define LL_SYSCFG_MPU_SEC         (SYSCFG_CSLCKR_LOCKSMPU << 16U)             /*!< Secure MPU lock (privileged secure code only) */
228 #define LL_SYSCFG_VTOR_AIRCR_SEC  (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U)         /*!< VTOR_S and AIRCR lock (privileged secure code only) */
229 #define LL_SYSCFG_LOCK_ALL        (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC | LL_SYSCFG_SAU | LL_SYSCFG_MPU_SEC | \
230                                    LL_SYSCFG_VTOR_AIRCR_SEC)                  /*!< All */
231 #else
232 #define LL_SYSCFG_LOCK_ALL        (LL_SYSCFG_MPU_NSEC | LL_SYSCFG_VTOR_NSEC)  /*!< All (privileged secure or non-secure only) */
233 #endif /* __ARM_FEATURE_CMSE */
234 /**
235   * @}
236   */
237 
238 /** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
239   * @note Only available when system implements security (TZEN=1)
240   * @{
241   */
242 #define LL_SYSCFG_CLOCK_SEC                SYSCFG_SECCFGR_SYSCFGSEC  /*!< SYSCFG clock configuration secure-only access */
243 #define LL_SYSCFG_CLOCK_NSEC               0U                        /*!< SYSCFG clock configuration secure/non-secure access */
244 #define LL_SYSCFG_CLASSB_SEC               SYSCFG_SECCFGR_CLASSBSEC  /*!< Class B configuration secure-only access */
245 #define LL_SYSCFG_CLASSB_NSEC              0U                        /*!< Class B configuration secure/non-secure access */
246 #define LL_SYSCFG_FPU_SEC                  SYSCFG_SECCFGR_FPUSEC     /*!< FPU configuration secure-only access */
247 #define LL_SYSCFG_FPU_NSEC                 0U                        /*!< FPU configuration secure/non-secure access */
248 /**
249   * @}
250   */
251 
252 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
253   * @{
254   */
255 #define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
256 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
257 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
258 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
259 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
260 /**
261   * @}
262   */
263 
264 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
265   * @{
266   */
267 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
268 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
269 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
270 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
271 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
272 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
273 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
274 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
275 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
276 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
277 /**
278   * @}
279   */
280 
281 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
282   * @{
283   */
284 #define LL_DBGMCU_APB1_GRP2_I2C4_STOP      DBGMCU_APB1FZR2_DBG_I2C4_STOP   /*!< The I2C4 SMBus timeout is frozen*/
285 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
286 #define LL_DBGMCU_APB1_GRP2_I2C5_STOP      DBGMCU_APB1FZR2_DBG_I2C5_STOP   /*!< The I2C5 SMBus timeout is frozen*/
287 #define LL_DBGMCU_APB1_GRP2_I2C6_STOP      DBGMCU_APB1FZR2_DBG_I2C6_STOP   /*!< The I2C6 SMBus timeout is frozen*/
288 /**
289   * @}
290   */
291 
292 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
293   * @{
294   */
295 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZR_DBG_TIM1_STOP    /*!< The counter clock of TIM1 is stopped when the core is halted*/
296 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZR_DBG_TIM8_STOP    /*!< The counter clock of TIM8 is stopped when the core is halted*/
297 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZR_DBG_TIM15_STOP   /*!< The counter clock of TIM15 is stopped when the core is halted*/
298 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZR_DBG_TIM16_STOP   /*!< The counter clock of TIM16 is stopped when the core is halted*/
299 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZR_DBG_TIM17_STOP   /*!< The counter clock of TIM17 is stopped when the core is halted*/
300 /**
301   * @}
302   */
303 
304 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP
305   * @{
306   */
307 #define LL_DBGMCU_APB3_GRP1_I2C3_STOP      DBGMCU_APB3FZR_DBG_I2C3_STOP    /*!< The counter clock of I2C3 is stopped when the core is halted*/
308 #define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP    DBGMCU_APB3FZR_DBG_LPTIM1_STOP  /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
309 #define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP    DBGMCU_APB3FZR_DBG_LPTIM3_STOP  /*!< The counter clock of LPTIM3 is stopped when the core is halted*/
310 #define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP    DBGMCU_APB3FZR_DBG_LPTIM4_STOP  /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
311 #define LL_DBGMCU_APB3_GRP1_RTC_STOP       DBGMCU_APB3FZR_DBG_RTC_STOP     /*!< The counter clock of RTC is stopped when the core is halted*/
312 /**
313   * @}
314   */
315 
316 /** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP
317   * @{
318   */
319 #define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP    DBGMCU_AHB1FZR_DBG_GPDMA0_STOP    /*!< The counter clock of GPDMA0 is stopped when the core is halted*/
320 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP    DBGMCU_AHB1FZR_DBG_GPDMA1_STOP    /*!< The counter clock of GPDMA1 is stopped when the core is halted*/
321 #define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP    DBGMCU_AHB1FZR_DBG_GPDMA2_STOP    /*!< The counter clock of GPDMA2 is stopped when the core is halted*/
322 #define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP    DBGMCU_AHB1FZR_DBG_GPDMA3_STOP    /*!< The counter clock of GPDMA3 is stopped when the core is halted*/
323 #define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP    DBGMCU_AHB1FZR_DBG_GPDMA4_STOP    /*!< The counter clock of GPDMA4 is stopped when the core is halted*/
324 #define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP    DBGMCU_AHB1FZR_DBG_GPDMA5_STOP    /*!< The counter clock of GPDMA5 is stopped when the core is halted*/
325 #define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP    DBGMCU_AHB1FZR_DBG_GPDMA6_STOP    /*!< The counter clock of GPDMA6 is stopped when the core is halted*/
326 #define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP    DBGMCU_AHB1FZR_DBG_GPDMA7_STOP    /*!< The counter clock of GPDMA7 is stopped when the core is halted*/
327 #define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP    DBGMCU_AHB1FZR_DBG_GPDMA8_STOP    /*!< The counter clock of GPDMA8 is stopped when the core is halted*/
328 #define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP    DBGMCU_AHB1FZR_DBG_GPDMA9_STOP    /*!< The counter clock of GPDMA9 is stopped when the core is halted*/
329 #define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP   DBGMCU_AHB1FZR_DBG_GPDMA10_STOP   /*!< The counter clock of GPDMA10 is stopped when the core is halted*/
330 #define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP   DBGMCU_AHB1FZR_DBG_GPDMA11_STOP   /*!< The counter clock of GPDMA11 is stopped when the core is halted*/
331 #define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP   DBGMCU_AHB1FZR_DBG_GPDMA12_STOP   /*!< The counter clock of GPDMA12 is stopped when the core is halted*/
332 #define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP   DBGMCU_AHB1FZR_DBG_GPDMA13_STOP   /*!< The counter clock of GPDMA13 is stopped when the core is halted*/
333 #define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP   DBGMCU_AHB1FZR_DBG_GPDMA14_STOP   /*!< The counter clock of GPDMA14 is stopped when the core is halted*/
334 #define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP   DBGMCU_AHB1FZR_DBG_GPDMA15_STOP   /*!< The counter clock of GPDMA15 is stopped when the core is halted*/
335 /**
336   * @}
337   */
338 
339 /** @defgroup SYSTEM_LL_EC_AHB3_GRP1_STOP_IP DBGMCU AHB3 GRP1 STOP IP
340   * @{
341   */
342 #define LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP    DBGMCU_AHB3FZR_DBG_LPDMA0_STOP    /*!< The counter clock of LPDMA0 is stopped when the core is halted*/
343 #define LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP    DBGMCU_AHB3FZR_DBG_LPDMA1_STOP    /*!< The counter clock of LPDMA1 is stopped when the core is halted*/
344 #define LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP    DBGMCU_AHB3FZR_DBG_LPDMA2_STOP    /*!< The counter clock of LPDMA2 is stopped when the core is halted*/
345 #define LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP    DBGMCU_AHB3FZR_DBG_LPDMA3_STOP    /*!< The counter clock of LPDMA3 is stopped when the core is halted*/
346 /**
347   * @}
348   */
349 
350 #if defined(VREFBUF)
351 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
352   * @{
353   */
354 #define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000)                   /*!< Voltage reference scale 0 (VREF_OUT1) */
355 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS_0                        /*!< Voltage reference scale 1 (VREF_OUT2) */
356 #define LL_VREFBUF_VOLTAGE_SCALE2          VREFBUF_CSR_VRS_1                        /*!< Voltage reference scale 2 (VREF_OUT3) */
357 #define LL_VREFBUF_VOLTAGE_SCALE3          (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1)  /*!< Voltage reference scale 3 (VREF_OUT4) */
358 /**
359   * @}
360   */
361 #endif /* VREFBUF */
362 
363 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
364   * @{
365   */
366 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH zero wait state */
367 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH one wait state */
368 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH two wait states */
369 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH three wait states */
370 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH four wait states */
371 #define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait states */
372 #define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
373 #define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven wait states */
374 #define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight wait states */
375 #define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
376 #define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS  /*!< FLASH ten wait states */
377 #define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS  /*!< FLASH eleven wait states */
378 #define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS  /*!< FLASH twelve wait states */
379 #define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS  /*!< FLASH thirteen wait states */
380 #define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS  /*!< FLASH fourteen wait states */
381 #define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS  /*!< FLASH fifteen wait states */
382 /**
383   * @}
384   */
385 
386 /**
387   * @}
388   */
389 
390 /* Exported macro ------------------------------------------------------------*/
391 
392 /* Exported functions --------------------------------------------------------*/
393 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
394   * @{
395   */
396 
397 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
398   * @{
399   */
400 
401 /**
402   * @brief  Enable I/O analog switches supplied by VDD.
403   * @rmtoll SYSCFG_CFGR1 ANASWVDD      LL_SYSCFG_EnableAnalogSwitchVdd
404   * @retval None
405   */
LL_SYSCFG_EnableAnalogSwitchVdd(void)406 __STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void)
407 {
408   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
409 }
410 
411 /**
412   * @brief  Disable I/O analog switches supplied by VDD.
413   * @note   I/O analog switches are supplied by VDDA or booster
414   *         when booster in on.
415   *         Dedicated voltage booster (supplied by VDD) is the recommended
416   *         configuration with low VDDA voltage operation.
417   * @rmtoll SYSCFG_CFGR1 ANASWVDD      LL_SYSCFG_DisableAnalogSwitchVdd
418   * @retval None
419   */
LL_SYSCFG_DisableAnalogSwitchVdd(void)420 __STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void)
421 {
422   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
423 }
424 
425 /**
426   * @brief  Enable I/O analog switch voltage booster.
427   * @note   When voltage booster is enabled, I/O analog switches are supplied
428   *         by a dedicated voltage booster, from VDD power domain. This is
429   *         the recommended configuration with low VDDA voltage operation.
430   * @note   The I/O analog switch voltage booster is relevant for peripherals
431   *         using I/O in analog input: ADC, COMP, OPAMP.
432   *         However, COMP and OPAMP inputs have a high impedance and
433   *         voltage booster do not impact performance significantly.
434   *         Therefore, the voltage booster is mainly intended for
435   *         usage with ADC.
436   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
437   * @retval None
438   */
LL_SYSCFG_EnableAnalogBooster(void)439 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
440 {
441   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
442 }
443 
444 /**
445   * @brief  Disable I/O analog switch voltage booster.
446   * @note   When voltage booster is enabled, I/O analog switches are supplied
447   *         by a dedicated voltage booster, from VDD power domain. This is
448   *         the recommended configuration with low VDDA voltage operation.
449   * @note   The I/O analog switch voltage booster is relevant for peripherals
450   *         using I/O in analog input: ADC, COMP, OPAMP.
451   *         However, COMP and OPAMP inputs have a high impedance and
452   *         voltage booster do not impact performance significantly.
453   *         Therefore, the voltage booster is mainly intended for
454   *         usage with ADC.
455   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
456   * @retval None
457   */
LL_SYSCFG_DisableAnalogBooster(void)458 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
459 {
460   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
461 }
462 
463 /**
464   * @brief  Enable the fast mode plus driving capability.
465   * @rmtoll SYSCFG_CFGR1 PBx_FMP   LL_SYSCFG_EnableFastModePlus
466   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
467   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6
468   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7
469   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8
470   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9
471   * @retval None
472   */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)473 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
474 {
475   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
476 }
477 
478 /**
479   * @brief  Disable the fast mode plus driving capability.
480   * @rmtoll SYSCFG_CFGR1 PBx_FMP   LL_SYSCFG_DisableFastModePlus
481   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
482   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6
483   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7
484   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8
485   *         @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9
486   * @retval None
487   */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)488 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
489 {
490   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
491 }
492 
493 #if defined(SYSCFG_CFGR1_ENDCAP)
494 /**
495   * @brief  Set decoupling capacitance on HSPI supply.
496   * @rmtoll SYSCFG_CFGR1   ENDCAP   LL_SYSCFG_SetHSPIDecouplingCapacitance
497   * @param  Capacitance This parameter can be one of the following values:
498   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF
499   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3
500   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3
501   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL
502   * @retval None
503   */
LL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance)504 __STATIC_INLINE void LL_SYSCFG_SetHSPIDecouplingCapacitance(uint32_t Capacitance)
505 {
506   MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP, Capacitance);
507 }
508 
509 /**
510   * @brief  Get decoupling capacitance on HSPI supply.
511   * @rmtoll SYSCFG_CFGR1   ENDCAP   LL_SYSCFG_GetHSPIDecouplingCapacitance
512   * @retval Returned value can be one of the following values:
513   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_OFF
514   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_1_DIV_3
515   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_2_DIV_3
516   *         @arg @ref LL_SYSCFG_HSPI_CAPACITANCE_FULL
517   */
LL_SYSCFG_GetHSPIDecouplingCapacitance(void)518 __STATIC_INLINE uint32_t LL_SYSCFG_GetHSPIDecouplingCapacitance(void)
519 {
520   return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ENDCAP));
521 }
522 #endif /* SYSCFG_CFGR1_ENDCAP */
523 
524 #if defined(SYSCFG_CFGR1_SRAMCACHED)
525 /**
526   * @brief  Enable the cachability of internal SRAMs by DCACHE2.
527   * @rmtoll SYSCFG_CFGR1   SRAMCACHED   LL_SYSCFG_EnableSRAMsCachability
528   * @retval None
529   */
LL_SYSCFG_EnableSRAMsCachability(void)530 __STATIC_INLINE void LL_SYSCFG_EnableSRAMsCachability(void)
531 {
532   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED);
533 }
534 
535 /**
536   * @brief  Disable the cachability of internal SRAMs by DCACHE2.
537   * @rmtoll SYSCFG_CFGR1   SRAMCACHED   LL_SYSCFG_DisableSRAMsCachability
538   * @retval None
539   */
LL_SYSCFG_DisableSRAMsCachability(void)540 __STATIC_INLINE void LL_SYSCFG_DisableSRAMsCachability(void)
541 {
542   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED);
543 }
544 
545 /**
546   * @brief  Check if internal SRAMs cachability by DCACHE2 is enabled or disabled.
547   * @rmtoll SYSCFG_CFGR1   SRAMCACHED   LL_SYSCFG_IsEnabledSRAMsCachability
548   * @retval State of bit (1 or 0).
549   */
LL_SYSCFG_IsEnabledSRAMsCachability(void)550 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledSRAMsCachability(void)
551 {
552   return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED) == SYSCFG_CFGR1_SRAMCACHED) ? 1UL : 0UL);
553 }
554 #endif /* SYSCFG_CFGR1_SRAMCACHED */
555 
556 /** @defgroup SYSTEM_LL_EF_SYSCFG_FPU_IT_MANAGEMENT FPU interrupt management
557   * @{
558   */
559 
560 /**
561   * @brief  Enable Floating Point Unit Invalid operation Interrupt.
562   * @rmtoll SYSCFG_FPUIMR FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
563   * @retval None
564   */
LL_SYSCFG_EnableIT_FPU_IOC(void)565 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
566 {
567   SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
568 }
569 
570 /**
571   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt.
572   * @rmtoll SYSCFG_FPUIMR FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
573   * @retval None
574   */
LL_SYSCFG_EnableIT_FPU_DZC(void)575 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
576 {
577   SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
578 }
579 
580 /**
581   * @brief  Enable Floating Point Unit Underflow Interrupt.
582   * @rmtoll SYSCFG_FPUIMR FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
583   * @retval None
584   */
LL_SYSCFG_EnableIT_FPU_UFC(void)585 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
586 {
587   SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
588 }
589 
590 /**
591   * @brief  Enable Floating Point Unit Overflow Interrupt.
592   * @rmtoll SYSCFG_FPUIMR FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
593   * @retval None
594   */
LL_SYSCFG_EnableIT_FPU_OFC(void)595 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
596 {
597   SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
598 }
599 
600 /**
601   * @brief  Enable Floating Point Unit Input denormal Interrupt.
602   * @rmtoll SYSCFG_FPUIMR FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
603   * @retval None
604   */
LL_SYSCFG_EnableIT_FPU_IDC(void)605 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
606 {
607   SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
608 }
609 
610 /**
611   * @brief  Enable Floating Point Unit Inexact Interrupt.
612   * @rmtoll SYSCFG_FPUIMR FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
613   * @retval None
614   */
LL_SYSCFG_EnableIT_FPU_IXC(void)615 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
616 {
617   SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
618 }
619 
620 /**
621   * @brief  Disable Floating Point Unit Invalid operation Interrupt.
622   * @rmtoll SYSCFG_FPUIMR FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
623   * @retval None
624   */
LL_SYSCFG_DisableIT_FPU_IOC(void)625 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
626 {
627   CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0);
628 }
629 
630 /**
631   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt.
632   * @rmtoll SYSCFG_FPUIMR FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
633   * @retval None
634   */
LL_SYSCFG_DisableIT_FPU_DZC(void)635 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
636 {
637   CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1);
638 }
639 
640 /**
641   * @brief  Disable Floating Point Unit Underflow Interrupt.
642   * @rmtoll SYSCFG_FPUIMR FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
643   * @retval None
644   */
LL_SYSCFG_DisableIT_FPU_UFC(void)645 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
646 {
647   CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2);
648 }
649 
650 /**
651   * @brief  Disable Floating Point Unit Overflow Interrupt.
652   * @rmtoll SYSCFG_FPUIMR FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
653   * @retval None
654   */
LL_SYSCFG_DisableIT_FPU_OFC(void)655 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
656 {
657   CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3);
658 }
659 
660 /**
661   * @brief  Disable Floating Point Unit Input denormal Interrupt.
662   * @rmtoll SYSCFG_FPUIMR FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
663   * @retval None
664   */
LL_SYSCFG_DisableIT_FPU_IDC(void)665 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
666 {
667   CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4);
668 }
669 
670 /**
671   * @brief  Disable Floating Point Unit Inexact Interrupt.
672   * @rmtoll SYSCFG_FPUIMR FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
673   * @retval None
674   */
LL_SYSCFG_DisableIT_FPU_IXC(void)675 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
676 {
677   CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5);
678 }
679 
680 /**
681   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
682   * @rmtoll SYSCFG_FPUIMR FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
683   * @retval State of bit (1 or 0).
684   */
LL_SYSCFG_IsEnabledIT_FPU_IOC(void)685 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
686 {
687   return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
688 }
689 
690 /**
691   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
692   * @rmtoll SYSCFG_FPUIMR FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
693   * @retval State of bit (1 or 0).
694   */
LL_SYSCFG_IsEnabledIT_FPU_DZC(void)695 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
696 {
697   return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
698 }
699 
700 /**
701   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
702   * @rmtoll SYSCFG_FPUIMR FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
703   * @retval State of bit (1 or 0).
704   */
LL_SYSCFG_IsEnabledIT_FPU_UFC(void)705 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
706 {
707   return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
708 }
709 
710 /**
711   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
712   * @rmtoll SYSCFG_FPUIMR FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
713   * @retval State of bit (1 or 0).
714   */
LL_SYSCFG_IsEnabledIT_FPU_OFC(void)715 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
716 {
717   return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
718 }
719 
720 /**
721   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
722   * @rmtoll SYSCFG_FPUIMR FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
723   * @retval State of bit (1 or 0).
724   */
LL_SYSCFG_IsEnabledIT_FPU_IDC(void)725 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
726 {
727   return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
728 }
729 
730 /**
731   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
732   * @rmtoll SYSCFG_FPUIMR FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
733   * @retval State of bit (1 or 0).
734   */
LL_SYSCFG_IsEnabledIT_FPU_IXC(void)735 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
736 {
737   return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
738 }
739 
740 /**
741   * @}
742   */
743 
744 /** @defgroup SYSTEM_LL_EF_SYSCFG_CPU_LOCK CPU secure/non-secure lock
745   * @{
746   */
747 
748 /**
749   * @brief  Lock the secure or non-secure VTOR registers.
750   * @rmtoll CSLCKR/CNSLCKR   LOCKSVTAIRCR/LOCKNSVTOR   LL_SYSCFG_LockVTOR
751   * @retval None
752   */
LL_SYSCFG_LockVTOR(void)753 __STATIC_INLINE void LL_SYSCFG_LockVTOR(void)
754 {
755 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
756   SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR);
757 #else
758   SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR);
759 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
760 }
761 
762 /**
763   * @brief  Check the lock state of secure or non-secure VTOR registers.
764   * @rmtoll CSLCKR/CNSLCKR   LOCKSVTAIRCR/LOCKNSVTOR   LL_SYSCFG_IsLockedVTOR
765   * @retval None
766   */
LL_SYSCFG_IsLockedVTOR(void)767 __STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR(void)
768 {
769 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
770   return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSVTAIRCR) == SYSCFG_CSLCKR_LOCKSVTAIRCR) ? 1UL : 0UL);
771 #else
772   return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL);
773 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
774 }
775 
776 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
777 /**
778   * @brief  Lock the non-secure VTOR registers.
779   * @rmtoll CNSLCKR   LOCKNSVTOR   LL_SYSCFG_LockVTOR_NS
780   * @retval None
781   */
LL_SYSCFG_LockVTOR_NS(void)782 __STATIC_INLINE void LL_SYSCFG_LockVTOR_NS(void)
783 {
784   SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR);
785 }
786 
787 /**
788   * @brief  Check the lock state of non-secure VTOR registers.
789   * @rmtoll CNSLCKR   LOCKNSVTOR   LL_SYSCFG_IsLockedVTOR_NS
790   * @retval None
791   */
LL_SYSCFG_IsLockedVTOR_NS(void)792 __STATIC_INLINE uint32_t LL_SYSCFG_IsLockedVTOR_NS(void)
793 {
794   return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSVTOR) == SYSCFG_CNSLCKR_LOCKNSVTOR) ? 1UL : 0UL);
795 }
796 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
797 
798 /**
799   * @brief  Lock the secure or non-secure MPU registers.
800   * @rmtoll CSLCKR/CNSLCKR   LOCKNSMPU/LOCKSMPU   LL_SYSCFG_LockMPU
801   * @retval None
802   */
LL_SYSCFG_LockMPU(void)803 __STATIC_INLINE void LL_SYSCFG_LockMPU(void)
804 {
805 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
806   SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU);
807 #else
808   SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU);
809 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
810 }
811 
812 /**
813   * @brief  Check the lock state of secure or non-secure MPU registers.
814   * @rmtoll CSLCKR/CNSLCKR   LOCKNSMPU/LOCKSMPU   LL_SYSCFG_IsLockedMPU
815   * @retval None
816   */
LL_SYSCFG_IsLockedMPU(void)817 __STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU(void)
818 {
819 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
820   return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSMPU) == SYSCFG_CSLCKR_LOCKSMPU) ? 1UL : 0UL);
821 #else
822   return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL);
823 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
824 }
825 
826 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
827 /**
828   * @brief  Lock the non-secure MPU registers.
829   * @rmtoll CNSLCKR   LOCKNSMPU   LL_SYSCFG_LockMPU_NS
830   * @retval None
831   */
LL_SYSCFG_LockMPU_NS(void)832 __STATIC_INLINE void LL_SYSCFG_LockMPU_NS(void)
833 {
834   SET_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU);
835 }
836 
837 /**
838   * @brief  Check the lock state of non-secure MPU registers.
839   * @rmtoll CNSLCKR   LOCKNSMPU   LL_SYSCFG_IsLockedMPU_NS
840   * @retval None
841   */
LL_SYSCFG_IsLockedMPU_NS(void)842 __STATIC_INLINE uint32_t LL_SYSCFG_IsLockedMPU_NS(void)
843 {
844   return ((READ_BIT(SYSCFG->CNSLCKR, SYSCFG_CNSLCKR_LOCKNSMPU) == SYSCFG_CNSLCKR_LOCKNSMPU) ? 1UL : 0UL);
845 }
846 
847 /**
848   * @brief  Lock the secure SAU registers.
849   * @rmtoll CSLCKR   LOCKSAU   LL_SYSCFG_LockSAU
850   * @retval None
851   */
LL_SYSCFG_LockSAU(void)852 __STATIC_INLINE void LL_SYSCFG_LockSAU(void)
853 {
854   SET_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU);
855 }
856 
857 /**
858   * @brief  Check the lock state of secure SAU registers.
859   * @rmtoll CSLCKR   LOCKSAU   LL_SYSCFG_IsLockedSAU
860   * @retval None
861   */
LL_SYSCFG_IsLockedSAU(void)862 __STATIC_INLINE uint32_t LL_SYSCFG_IsLockedSAU(void)
863 {
864   return ((READ_BIT(SYSCFG->CSLCKR, SYSCFG_CSLCKR_LOCKSAU) == SYSCFG_CSLCKR_LOCKSAU) ? 1UL : 0UL);
865 }
866 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
867 
868 /**
869   * @brief  Lock the secure or non-secure CPU registers.
870   * @rmtoll CSLCKR/CNSLCKR   LOCKSVTAIRCR/LOCKNSVTOR   LL_SYSCFG_LockConfig
871   * @param  Item Item(s) to set lock on.
872   *         This parameter can be a combination of:
873   *         @arg @ref LL_SYSCFG_MPU_NSEC
874   *         @arg @ref LL_SYSCFG_VTOR_NSEC
875   *         @arg @ref LL_SYSCFG_SAU
876   *         @arg @ref LL_SYSCFG_MPU_SEC
877   *         @arg @ref LL_SYSCFG_VTOR_AIRCR_SEC
878   *         @arg @ref LL_SYSCFG_LOCK_ALL
879   * @retval None
880   */
LL_SYSCFG_LockConfig(uint32_t Item)881 __STATIC_INLINE void LL_SYSCFG_LockConfig(uint32_t Item)
882 {
883 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
884   MODIFY_REG(SYSCFG->CSLCKR, (SYSCFG_CSLCKR_LOCKSVTAIRCR | SYSCFG_CSLCKR_LOCKSMPU | SYSCFG_CSLCKR_LOCKSAU), Item);
885 #else
886   MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item);
887 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
888 }
889 
890 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
891 /**
892   * @brief  Lock the non-secure CPU registers.
893   * @rmtoll CSLCKR/CNSLCKR   LOCKSVTAIRCR/LOCKNSVTOR   LL_SYSCFG_LockConfig_NS
894   * @param  Item Item(s) to set lock on.
895   *         This parameter can be a combination of:
896   *         @arg @ref LL_SYSCFG_MPU_NSEC
897   *         @arg @ref LL_SYSCFG_VTOR_NSEC
898   *         @arg @ref LL_SYSCFG_LOCK_ALL
899   * @retval None
900   */
LL_SYSCFG_LockConfig_NS(uint32_t Item)901 __STATIC_INLINE void LL_SYSCFG_LockConfig_NS(uint32_t Item)
902 {
903   MODIFY_REG(SYSCFG->CNSLCKR, (SYSCFG_CNSLCKR_LOCKNSVTOR | SYSCFG_CNSLCKR_LOCKNSMPU), Item);
904 }
905 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
906 
907 /**
908   * @}
909   */
910 
911 /** @defgroup SYSTEM_LL_EF_SYSCFG_TIMER_BREAK Timer break inputs
912   * @{
913   */
914 
915 /**
916   * @brief  Set connections to TIM1/8/15/16/17 Break inputs.
917   * @rmtoll SYSCFG_CFGR2 CLL          LL_SYSCFG_SetTIMBreakInputs\n
918   *         SYSCFG_CFGR2 SPL          LL_SYSCFG_SetTIMBreakInputs\n
919   *         SYSCFG_CFGR2 PVDL         LL_SYSCFG_SetTIMBreakInputs\n
920   *         SYSCFG_CFGR2 ECCL         LL_SYSCFG_SetTIMBreakInputs
921   * @param  Break This parameter can be a combination of the following values:
922   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
923   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
924   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
925   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
926   * @retval None
927   */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)928 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
929 {
930   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
931 }
932 
933 /**
934   * @brief  Get connections to TIM1/8/15/16/17 Break inputs.
935   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
936   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
937   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
938   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
939   * @retval Returned value can be can be a combination of the following values:
940   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
941   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
942   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK
943   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
944   */
LL_SYSCFG_GetTIMBreakInputs(void)945 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
946 {
947   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | \
948                              SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
949 }
950 
951 /**
952   * @}
953   */
954 
955 /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
956   * @{
957   */
958 
959 /**
960   * @brief  Clear Status of End of Erase for ICACHE and PKA RAMs
961   * @rmtoll MESR   IPMEE    LL_SYSCFG_ClearEraseEndStatus
962   * @retval None
963   */
LL_SYSCFG_ClearEraseEndStatus(void)964 __STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void)
965 {
966   SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE);
967 }
968 
969 /**
970   * @brief  Get Status of End of Erase for ICACHE and PKA RAMs
971   * @rmtoll MESR   IPMEE    LL_SYSCFG_GetEraseEndStatus
972   * @retval Returned value can be one of the following values:
973   *   @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
974   *   @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
975   */
LL_SYSCFG_GetEraseEndStatus(void)976 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void)
977 {
978   return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE));
979 }
980 
981 /**
982   * @brief  Clear Status of End of Erase after reset  for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
983   * @rmtoll MESR   MCLR    LL_SYSCFG_ClearEraseAfterResetStatus
984   * @retval None
985   */
LL_SYSCFG_ClearEraseAfterResetStatus(void)986 __STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void)
987 {
988   SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR);
989 }
990 
991 /**
992   * @brief  Get Status of End of Erase after reset  for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams
993   * @rmtoll MESR   MCLR    LL_SYSCFG_GetEraseAfterResetStatus
994   * @retval Returned value can be one of the following values:
995   *   @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done
996   *   @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended
997   */
LL_SYSCFG_GetEraseAfterResetStatus(void)998 __STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void)
999 {
1000   return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR));
1001 }
1002 
1003 /**
1004   * @}
1005   */
1006 
1007 /** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG Compensation cell
1008   * @{
1009   */
1010 
1011 /**
1012   * @brief  Get the compensation cell value of the GPIO PMOS transistor supplied by VDD.
1013   * @rmtoll CCVR    PCV1   LL_SYSCFG_GetPMOSVddCompensationValue
1014   * @retval Returned value is the PMOS compensation cell
1015   */
LL_SYSCFG_GetPMOSVddCompensationValue(void)1016 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void)
1017 {
1018   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1));
1019 }
1020 
1021 /**
1022   * @brief  Get the compensation cell value of the GPIO NMOS transistor supplied by VDD.
1023   * @rmtoll CCVR    NCV1   LL_SYSCFG_GetNMOSVddCompensationValue
1024   * @retval Returned value is the NMOS compensation cell
1025   */
LL_SYSCFG_GetNMOSVddCompensationValue(void)1026 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void)
1027 {
1028   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1));
1029 }
1030 
1031 /**
1032   * @brief  Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2.
1033   * @rmtoll CCVR    PCV2   LL_SYSCFG_GetPMOSVddIO2CompensationValue
1034   * @retval Returned value is the PMOS compensation cell
1035   */
LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)1036 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void)
1037 {
1038   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2));
1039 }
1040 
1041 /**
1042   * @brief  Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2.
1043   * @rmtoll CCVR    NCV2   LL_SYSCFG_GetNMOSVddIO2CompensationValue
1044   * @retval Returned value is the NMOS compensation cell
1045   */
LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)1046 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void)
1047 {
1048   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2));
1049 }
1050 
1051 #if defined(SYSCFG_CCVR_PCV3)
1052 /**
1053   * @brief  Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD.
1054   * @rmtoll CCVR    PCV3   LL_SYSCFG_GetPMOSVddHSPICompensationValue
1055   * @retval Returned value is the PMOS compensation cell
1056   */
LL_SYSCFG_GetPMOSVddHSPICompensationValue(void)1057 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void)
1058 {
1059   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV3));
1060 }
1061 
1062 /**
1063   * @brief  Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD.
1064   * @rmtoll CCVR    NCV3   LL_SYSCFG_GetNMOSVddHSPICompensationValue
1065   * @retval Returned value is the NMOS compensation cell
1066   */
LL_SYSCFG_GetNMOSVddHSPICompensationValue(void)1067 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void)
1068 {
1069   return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV3));
1070 }
1071 #endif /* SYSCFG_CCVR_PCV3 */
1072 
1073 /**
1074   * @brief  Set the compensation cell code of the GPIO PMOS transistor supplied by VDD.
1075   * @rmtoll CCCR    PCC1  LL_SYSCFG_SetPMOSVddCompensationCode
1076   * @param  PMOSCode PMOS compensation code
1077   *         This code is applied to the PMOS compensation cell when the CS1 bit of the
1078   *         SYSCFG_CCCSR is set
1079   * @retval None
1080   */
LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)1081 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode)
1082 {
1083   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos);
1084 }
1085 
1086 /**
1087   * @brief  Get the compensation cell code of the GPIO PMOS transistor supplied by VDD.
1088   * @rmtoll CCCR    PCC1   LL_SYSCFG_GetPMOSVddCompensationCode
1089   * @retval Returned value is the PMOS compensation cell
1090   */
LL_SYSCFG_GetPMOSVddCompensationCode(void)1091 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void)
1092 {
1093   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1));
1094 }
1095 
1096 /**
1097   * @brief  Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2.
1098   * @rmtoll CCCR    PCC2  LL_SYSCFG_SetPMOSVddIO2CompensationCode
1099   * @param  PMOSCode PMOS compensation code
1100   *         This code is applied to the PMOS compensation cell when the CS2 bit of the
1101   *         SYSCFG_CCCSR is set
1102   * @retval None
1103   */
LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)1104 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode)
1105 {
1106   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos);
1107 }
1108 
1109 /**
1110   * @brief  Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2.
1111   * @rmtoll CCCR    PCC2   LL_SYSCFG_GetPMOSVddIO2CompensationCode
1112   * @retval Returned value is the PMOS compensation
1113   */
LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)1114 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void)
1115 {
1116   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2));
1117 }
1118 
1119 #if defined(SYSCFG_CCCR_PCC3)
1120 /**
1121   * @brief  Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD.
1122   * @rmtoll CCCR    PCC3  LL_SYSCFG_SetPMOSVddHSPICompensationCode
1123   * @param  PMOSCode PMOS compensation code
1124   *         This code is applied to the PMOS compensation cell when the CS3 bit of the
1125   *         SYSCFG_CCCSR is set
1126   * @retval None
1127   */
LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode)1128 __STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode)
1129 {
1130   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC3, PMOSCode << SYSCFG_CCCR_PCC3_Pos);
1131 }
1132 
1133 /**
1134   * @brief  Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD.
1135   * @rmtoll CCCR    PCC3   LL_SYSCFG_GetPMOSVddHSPICompensationCode
1136   * @retval Returned value is the PMOS compensation
1137   */
LL_SYSCFG_GetPMOSVddHSPICompensationCode(void)1138 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void)
1139 {
1140   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC3));
1141 }
1142 #endif /* SYSCFG_CCCR_PCC3 */
1143 
1144 /**
1145   * @brief  Set the compensation cell code of the GPIO NMOS transistor supplied by VDD.
1146   * @rmtoll CCCR    PCC2  LL_SYSCFG_SetNMOSVddCompensationCode
1147   * @param  NMOSCode NMOS compensation code
1148   *         This code is applied to the NMOS compensation cell when the CS2 bit of the
1149   *         SYSCFG_CMPCR is set
1150   * @retval None
1151   */
LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)1152 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode)
1153 {
1154   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos);
1155 }
1156 
1157 /**
1158   * @brief  Get the compensation cell code of the GPIO NMOS transistor supplied by VDD.
1159   * @rmtoll CCCR    NCC1   LL_SYSCFG_GetNMOSVddCompensationCode
1160   * @retval Returned value is the Vdd compensation cell code for NMOS transistors
1161   */
LL_SYSCFG_GetNMOSVddCompensationCode(void)1162 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void)
1163 {
1164   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1));
1165 }
1166 
1167 /**
1168   * @brief  Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2.
1169   * @rmtoll CCCR    NCC2  LL_SYSCFG_SetNMOSVddIO2CompensationCode
1170   * @param  NMOSCode NMOS compensation code
1171   *         This code is applied to the NMOS compensation cell when the CS2 bit of the
1172   *         SYSCFG_CMPCR is set
1173   *         Value between 0 and 15
1174   * @retval None
1175   */
LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)1176 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode)
1177 {
1178   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos);
1179 }
1180 
1181 /**
1182   * @brief  Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2.
1183   * @rmtoll CCCR    NCC2   LL_SYSCFG_GetNMOSVddIO2CompensationCode
1184   * @retval Returned value is the NMOS compensation cell code
1185   */
LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)1186 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void)
1187 {
1188   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2));
1189 }
1190 
1191 #if defined(SYSCFG_CCCR_NCC3)
1192 /**
1193   * @brief  Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD.
1194   * @rmtoll CCCR    NCC3  LL_SYSCFG_SetNMOSVddHSPICompensationCode
1195   * @param  NMOSCode NMOS compensation code
1196   *         This code is applied to the NMOS compensation cell when the CS3 bit of the
1197   *         SYSCFG_CCCSR is set
1198   *         Value between 0 and 15
1199   * @retval None
1200   */
LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode)1201 __STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode)
1202 {
1203   MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC3, NMOSCode << SYSCFG_CCCR_NCC3_Pos);
1204 }
1205 
1206 /**
1207   * @brief  Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD.
1208   * @rmtoll CCCR    NCC3   LL_SYSCFG_GetNMOSVddHSPICompensationCode
1209   * @retval Returned value is the NMOS compensation cell code
1210   */
LL_SYSCFG_GetNMOSVddHSPICompensationCode(void)1211 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void)
1212 {
1213   return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC3));
1214 }
1215 #endif /* SYSCFG_CCCR_NCC3 */
1216 
1217 /**
1218   * @brief  Enable the Compensation Cell of GPIO supplied by VDD.
1219   * @rmtoll CCCSR   EN1    LL_SYSCFG_EnableVddCompensationCell
1220   * @note   The vdd compensation cell can be used only when the device supply
1221   *         voltage ranges from 1.71 to 3.6 V
1222   * @retval None
1223   */
LL_SYSCFG_EnableVddCompensationCell(void)1224 __STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void)
1225 {
1226   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
1227 }
1228 
1229 /**
1230   * @brief  Enable the Compensation Cell of GPIO supplied by VDDIO2.
1231   * @rmtoll CCCSR   EN2    LL_SYSCFG_EnableVddIO2CompensationCell
1232   * @note   The Vdd I/O compensation cell can be used only when the device supply
1233   *         voltage ranges from 1.08 to 3.6 V
1234   * @retval None
1235   */
LL_SYSCFG_EnableVddIO2CompensationCell(void)1236 __STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void)
1237 {
1238   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
1239 }
1240 
1241 #if defined(SYSCFG_CCCSR_EN3)
1242 /**
1243   * @brief  Enable the Compensation Cell of HSPI IO supplied by VDD.
1244   * @rmtoll CCCSR   EN3    LL_SYSCFG_EnableVddHSPICompensationCell
1245   * @retval None
1246   */
LL_SYSCFG_EnableVddHSPICompensationCell(void)1247 __STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void)
1248 {
1249   SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
1250 }
1251 #endif /* SYSCFG_CCCSR_EN3 */
1252 
1253 /**
1254   * @brief  Disable the Compensation Cell of GPIO supplied by VDD.
1255   * @rmtoll CCCSR   EN1    LL_SYSCFG_DisableVddCompensationCell
1256   * @note   The Vdd compensation cell can be used only when the device supply
1257   *         voltage ranges from 1.71 to 3.6 V
1258   * @retval None
1259   */
LL_SYSCFG_DisableVddCompensationCell(void)1260 __STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void)
1261 {
1262   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1);
1263 }
1264 
1265 /**
1266   * @brief  Disable the Compensation Cell of GPIO supplied by VDDIO2.
1267   * @rmtoll CCCSR   EN2    LL_SYSCFG_DisableVddIO2CompensationCell
1268   * @note   The Vdd I/O compensation cell can be used only when the device supply
1269   *         voltage ranges from 1.08 to 3.6 V
1270   * @retval None
1271   */
LL_SYSCFG_DisableVddIO2CompensationCell(void)1272 __STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void)
1273 {
1274   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2);
1275 }
1276 
1277 #if defined(SYSCFG_CCCSR_EN3)
1278 /**
1279   * @brief  Disable the Compensation Cell of HSPI IO supplied by VDD.
1280   * @rmtoll CCCSR   EN3    LL_SYSCFG_DisableVddHSPICompensationCell
1281   * @retval None
1282   */
LL_SYSCFG_DisableVddHSPICompensationCell(void)1283 __STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void)
1284 {
1285   CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3);
1286 }
1287 #endif /* SYSCFG_CCCSR_EN3 */
1288 
1289 /**
1290   * @brief  Check if the Compensation Cell of GPIO supplied by VDD is enabled.
1291   * @rmtoll CCCSR   EN1    LL_SYSCFG_IsEnabled_VddCompensationCell
1292   * @retval State of bit (1 or 0).
1293   */
LL_SYSCFG_IsEnabled_VddCompensationCell(void)1294 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void)
1295 {
1296   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL);
1297 }
1298 
1299 /**
1300   * @brief  Check if the Compensation Cell of GPIO supplied by VDDIO2 is enabled.
1301   * @rmtoll CCCSR   EN2   LL_SYSCFG_IsEnabled_VddIO2CompensationCell
1302   * @retval State of bit (1 or 0).
1303   */
LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)1304 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void)
1305 {
1306   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL);
1307 }
1308 
1309 #if defined(SYSCFG_CCCSR_EN3)
1310 /**
1311   * @brief  Check if the Compensation Cell of HSPI IO supplied by VDD is enabled.
1312   * @rmtoll CCCSR   EN3   LL_SYSCFG_IsEnabled_VddHSPICompensationCell
1313   * @retval State of bit (1 or 0).
1314   */
LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void)1315 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void)
1316 {
1317   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3) == SYSCFG_CCCSR_EN3) ? 1UL : 0UL);
1318 }
1319 #endif /* SYSCFG_CCCSR_EN3 */
1320 
1321 /**
1322   * @brief  Get Compensation Cell ready Flag of GPIO supplied by VDD.
1323   * @rmtoll CCCSR   RDY1   LL_SYSCFG_IsActiveFlag_VddCMPCR
1324   * @retval State of bit (1 or 0).
1325   */
LL_SYSCFG_IsActiveFlag_VddCMPCR(void)1326 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void)
1327 {
1328   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL);
1329 }
1330 
1331 /**
1332   * @brief  Get Compensation Cell ready Flag of GPIO supplied by VDDIO2.
1333   * @rmtoll CCCSR   RDY2   LL_SYSCFG_IsActiveFlag_VddIO2CMPCR
1334   * @retval State of bit (1 or 0).
1335   */
LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)1336 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void)
1337 {
1338   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL);
1339 }
1340 
1341 #if defined(SYSCFG_CCCSR_RDY3)
1342 /**
1343   * @brief  Get Compensation Cell ready Flag of HSPI IO supplied by VDD.
1344   * @rmtoll CCCSR   RDY3   LL_SYSCFG_IsActiveFlag_VddHSPICMPCR
1345   * @retval State of bit (1 or 0).
1346   */
LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void)1347 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void)
1348 {
1349   return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY3) == (SYSCFG_CCCSR_RDY3)) ? 1UL : 0UL);
1350 }
1351 #endif /* SYSCFG_CCCSR_RDY3 */
1352 
1353 /**
1354   * @brief  Set the compensation cell code selection of GPIO supplied by VDD.
1355   * @rmtoll CCCSR   CS1    LL_SYSCFG_SetVddCellCompensationCode
1356   * @param  CompCode: Selects the code to be applied for the Vdd compensation cell
1357   *   This parameter can be one of the following values:
1358   *   @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
1359   *   @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1360   * @retval None
1361   */
LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)1362 __STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode)
1363 {
1364   SET_BIT(SYSCFG->CCCSR, CompCode);
1365 }
1366 
1367 /**
1368   * @brief  Set the compensation cell code selection of GPIO supplied by VDDIO2.
1369   * @rmtoll CCCSR   CS2    LL_SYSCFG_SetVddIO2CellCompensationCode
1370   * @param  CompCode: Selects the code to be applied for the VddIO compensation cell
1371   *   This parameter can be one of the following values:
1372   *   @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
1373   *   @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1374   * @retval None
1375   */
LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)1376 __STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode)
1377 {
1378   SET_BIT(SYSCFG->CCCSR, CompCode);
1379 }
1380 
1381 #if defined(SYSCFG_CCCSR_CS3)
1382 /**
1383   * @brief  Set the compensation cell code selection of HSPI IO supplied by VDD.
1384   * @rmtoll CCCSR   CS3    LL_SYSCFG_SetVddHSPICellCompensationCode
1385   * @param  CompCode: Selects the code to be applied for the VddIO compensation cell
1386   *   This parameter can be one of the following values:
1387   *   @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
1388   *   @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1389   * @retval None
1390   */
LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode)1391 __STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode)
1392 {
1393   SET_BIT(SYSCFG->CCCSR, CompCode);
1394 }
1395 #endif /* SYSCFG_CCCSR_CS3 */
1396 
1397 /**
1398   * @brief  Get the compensation cell code selection of GPIO supplied by VDD.
1399   * @rmtoll CCCSR   CS1    LL_SYSCFG_GetVddCellCompensationCode
1400   * @retval Returned value can be one of the following values:
1401   *   @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1402   *   @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)
1403   */
LL_SYSCFG_GetVddCellCompensationCode(void)1404 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void)
1405 {
1406   return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1));
1407 }
1408 
1409 /**
1410   * @brief  Get the compensation cell code selection of GPIO supplied by VDDIO2.
1411   * @rmtoll CCCSR   CS2    LL_SYSCFG_GetVddIO2CellCompensationCode
1412   * @retval Returned value can be one of the following values:
1413   *   @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1414   *   @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation
1415       cell code register (SYSCFG_CCCR)
1416   */
LL_SYSCFG_GetVddIO2CellCompensationCode(void)1417 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void)
1418 {
1419   return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2));
1420 }
1421 
1422 #if defined(SYSCFG_CCCSR_CS3)
1423 /**
1424   * @brief  Get the compensation cell code selection of HSPI IO supplied by VDD.
1425   * @rmtoll CCCSR   CS3    LL_SYSCFG_GetVddHSPICellCompensationCode
1426   * @retval Returned value can be one of the following values:
1427   *   @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)
1428   *   @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Selected Code is from the SYSCFG compensation
1429       cell code register (SYSCFG_CCCR)
1430   */
LL_SYSCFG_GetVddHSPICellCompensationCode(void)1431 __STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void)
1432 {
1433   return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3));
1434 }
1435 #endif /* SYSCFG_CCCSR_CS3 */
1436 
1437 /**
1438   * @}
1439   */
1440 
1441 /** @defgroup SYSTEM_LL_EF_SYSCFG_OTGPHY OTG HS PHY configurations
1442   * @{
1443   */
1444 
1445 #if defined(SYSCFG_OTGHSPHYCR_EN)
1446 /**
1447   * @brief  Enable the OTG high-speed PHY.
1448   * @rmtoll SYSCFG_OTGHSPHYCR   EN   LL_SYSCFG_EnableOTGPHY
1449   * @retval None
1450   */
LL_SYSCFG_EnableOTGPHY(void)1451 __STATIC_INLINE void LL_SYSCFG_EnableOTGPHY(void)
1452 {
1453   SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN);
1454 }
1455 
1456 /**
1457   * @brief  Disable the OTG high-speed PHY.
1458   * @rmtoll SYSCFG_OTGHSPHYCR   EN   LL_SYSCFG_DisableOTGPHY
1459   * @retval None
1460   */
LL_SYSCFG_DisableOTGPHY(void)1461 __STATIC_INLINE void LL_SYSCFG_DisableOTGPHY(void)
1462 {
1463   CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN);
1464 }
1465 
1466 /**
1467   * @brief  Check if the OTG high-speed PHY is enabled or disabled.
1468   * @rmtoll SYSCFG_OTGHSPHYCR   EN   LL_SYSCFG_IsEnabledOTGPHY
1469   * @retval None
1470   */
LL_SYSCFG_IsEnabledOTGPHY(void)1471 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHY(void)
1472 {
1473   return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN) == SYSCFG_OTGHSPHYCR_EN) ? 1UL : 0UL);
1474 }
1475 #endif /* SYSCFG_OTGHSPHYCR_EN */
1476 
1477 #if defined(SYSCFG_OTGHSPHYCR_PDCTRL)
1478 /**
1479   * @brief  Enable the OTG high-speed PHY common block power-down control.
1480   * @rmtoll SYSCFG_OTGHSPHYCR   PDCTRL   LL_SYSCFG_EnableOTGPHYPowerDown
1481   * @retval None
1482   */
LL_SYSCFG_EnableOTGPHYPowerDown(void)1483 __STATIC_INLINE void LL_SYSCFG_EnableOTGPHYPowerDown(void)
1484 {
1485   SET_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL);
1486 }
1487 
1488 /**
1489   * @brief  Disable the OTG high-speed PHY common block power-down control.
1490   * @rmtoll SYSCFG_OTGHSPHYCR   PDCTRL   LL_SYSCFG_DisableOTGPHYPowerDown
1491   * @retval None
1492   */
LL_SYSCFG_DisableOTGPHYPowerDown(void)1493 __STATIC_INLINE void LL_SYSCFG_DisableOTGPHYPowerDown(void)
1494 {
1495   CLEAR_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL);
1496 }
1497 
1498 /**
1499   * @brief  Check if the OTG high-speed PHY common block power-down is enabled or disabled.
1500   * @rmtoll SYSCFG_OTGHSPHYCR   PDCTRL   LL_SYSCFG_IsEnabledOTGPHYPowerDown
1501   * @retval None
1502   */
LL_SYSCFG_IsEnabledOTGPHYPowerDown(void)1503 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledOTGPHYPowerDown(void)
1504 {
1505   return ((READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL) == SYSCFG_OTGHSPHYCR_PDCTRL) ? 1UL : 0UL);
1506 }
1507 #endif /* SYSCFG_OTGHSPHYCR_PDCTRL */
1508 
1509 #if defined(SYSCFG_OTGHSPHYCR_CLKSEL)
1510 /**
1511   * @brief  Set the OTG high-speed PHY reference clock frequency selection.
1512   * @rmtoll SYSCFG_OTGHSPHYCR   CLKSEL   LL_SYSCFG_SetOTGPHYReferenceClockFrequency
1513   * @param  ClockFrequency This parameter can be one of the following values:
1514   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ
1515   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ
1516   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ
1517   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ
1518   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ
1519   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ
1520   * @retval None
1521   */
LL_SYSCFG_SetOTGPHYReferenceClockFrequency(uint32_t ClockFrequency)1522 __STATIC_INLINE void LL_SYSCFG_SetOTGPHYReferenceClockFrequency(uint32_t ClockFrequency)
1523 {
1524   MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, ClockFrequency);
1525 }
1526 
1527 /**
1528   * @brief  Get the OTG high-speed PHY reference clock frequency selection.
1529   * @rmtoll SYSCFG_OTGHSPHYCR   CLKSEL   LL_SYSCFG_GetOTGPHYReferenceClockFrequency
1530   * @retval Returned value can be one of the following values:
1531   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_16MHZ
1532   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_19_2MHZ
1533   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_20MHZ
1534   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_24MHZ
1535   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_26MHZ
1536   *         @arg @ref LL_SYSCFG_OTGHSPHY_CLK_32MHZ
1537   */
LL_SYSCFG_GetOTGPHYReferenceClockFrequency(void)1538 __STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYReferenceClockFrequency(void)
1539 {
1540   return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL));
1541 }
1542 #endif /* SYSCFG_OTGHSPHYCR_CLKSEL */
1543 
1544 #if defined(SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE)
1545 /**
1546   * @brief  Set the OTG high-speed PHY disconnect threshold adjustment.
1547   * @rmtoll SYSCFG_OTGHSPHYTUNER2   COMPDISTUNE   LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment
1548   * @param  DisconnectThreshold This parameter can be one of the following values:
1549   *         @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT
1550   *         @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT
1551   * @retval None
1552   */
LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold)1553 __STATIC_INLINE void LL_SYSCFG_SetOTGPHYDisconnectThresholdAdjustment(uint32_t DisconnectThreshold)
1554 {
1555   MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold);
1556 }
1557 
1558 /**
1559   * @brief  Get the OTG high-speed PHY disconnect threshold adjustment.
1560   * @rmtoll SYSCFG_OTGHSPHYTUNER2   COMPDISTUNE   LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment
1561   * @retval Returned value can be one of the following values:
1562   *         @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_5_9PERCENT
1563   *         @arg @ref LL_SYSCFG_OTGHSPHY_DISCONNECT_0PERCENT
1564   */
LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment(void)1565 __STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYDisconnectThresholdAdjustment(void)
1566 {
1567   return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE));
1568 }
1569 #endif /* SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE */
1570 
1571 #if defined(SYSCFG_OTGHSPHYTUNER2_SQRXTUNE)
1572 /**
1573   * @brief  Set the voltage level for the threshold used to detect valid high-speed data.
1574   * @rmtoll SYSCFG_OTGHSPHYTUNER2   SQRXTUNE   LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment
1575   * @param  SquelchThreshold This parameter can be one of the following values:
1576   *         @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT
1577   *         @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT
1578   * @retval None
1579   */
LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold)1580 __STATIC_INLINE void LL_SYSCFG_SetOTGPHYSquelchThresholdAdjustment(uint32_t SquelchThreshold)
1581 {
1582   MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold);
1583 }
1584 
1585 /**
1586   * @brief  Get the voltage level for the threshold used to detect valid high-speed data.
1587   * @rmtoll SYSCFG_OTGHSPHYTUNER2   SQRXTUNE   LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment
1588   * @retval Returned value can be one of the following values:
1589   *         @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_15PERCENT
1590   *         @arg @ref LL_SYSCFG_OTGHSPHY_SQUELCH_0PERCENT
1591   */
LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment(void)1592 __STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYSquelchThresholdAdjustment(void)
1593 {
1594   return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE));
1595 }
1596 #endif /* SYSCFG_OTGHSPHYTUNER2_SQRXTUNE */
1597 
1598 #if defined(SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE)
1599 /**
1600   * @brief  Set the OTG high-speed PHY transmitter preemphasis current control.
1601   * @rmtoll SYSCFG_OTGHSPHYTUNER2   TXPREEMPAMPTUNE   LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent
1602   * @param  PreemphasisCurrent This parameter can be one of the following values:
1603   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED
1604   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X
1605   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X
1606   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X
1607   * @retval None
1608   */
LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent)1609 __STATIC_INLINE void LL_SYSCFG_SetOTGPHYTransmitterPreemphasisCurrent(uint32_t PreemphasisCurrent)
1610 {
1611   MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent);
1612 }
1613 
1614 /**
1615   * @brief  Get the OTG high-speed PHY transmitter preemphasis current control.
1616   * @rmtoll SYSCFG_OTGHSPHYTUNER2   TXPREEMPAMPTUNE   LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent
1617   * @retval Returned value can be one of the following values:
1618   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_DISABLED
1619   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_1X
1620   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_2X
1621   *         @arg @ref LL_SYSCFG_OTGHSPHY_PREEMP_3X
1622   */
LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent(void)1623 __STATIC_INLINE uint32_t LL_SYSCFG_GetOTGPHYTransmitterPreemphasisCurrent(void)
1624 {
1625   return (uint32_t)(READ_BIT(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE));
1626 }
1627 #endif /* SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE */
1628 
1629 /**
1630   * @}
1631   */
1632 
1633 /** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management
1634   * @{
1635   */
1636 
1637 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1638 /**
1639   * @brief  Configure Secure mode.
1640   * @note Only available from secure state when system implements security (TZEN=1)
1641   * @rmtoll SECCFGR     SYSCFGSEC     LL_SYSCFG_ConfigSecure\n
1642   *         SECCFGR     CLASSBSEC     LL_SYSCFG_ConfigSecure\n
1643   *         SECCFGR     FPUSEC        LL_SYSCFG_ConfigSecure
1644   * @param  Configuration This parameter shall be the full combination
1645   *         of the following values:
1646   *         @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
1647   *         @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
1648   *         @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
1649   * @retval None
1650   */
LL_SYSCFG_ConfigSecure(uint32_t Configuration)1651 __STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration)
1652 {
1653   WRITE_REG(SYSCFG->SECCFGR, Configuration);
1654 }
1655 #endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */
1656 
1657 /**
1658   * @brief  Get Secure mode configuration.
1659   * @note Only available when system implements security (TZEN=1)
1660   * @rmtoll SECCFGR     SYSCFGSEC     LL_SYSCFG_ConfigSecure\n
1661   *         SECCFGR     CLASSBSEC     LL_SYSCFG_ConfigSecure\n
1662   *         SECCFGR     FPUSEC        LL_SYSCFG_ConfigSecure
1663   * @retval Returned value is the combination of the following values:
1664   *         @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC
1665   *         @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC
1666   *         @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC
1667   */
LL_SYSCFG_GetConfigSecure(void)1668 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void)
1669 {
1670   return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU));
1671 }
1672 
1673 /**
1674   * @}
1675   */
1676 
1677 /**
1678   * @}
1679   */
1680 
1681 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1682   * @{
1683   */
1684 
1685 /**
1686   * @brief  Return the device identifier
1687   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
1688   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1689   */
LL_DBGMCU_GetDeviceID(void)1690 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1691 {
1692   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1693 }
1694 
1695 /**
1696   * @brief  Return the device revision identifier
1697   * @note This field indicates the revision of the device.
1698   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
1699   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1700   */
LL_DBGMCU_GetRevisionID(void)1701 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1702 {
1703   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1704 }
1705 
1706 /**
1707   * @brief  Enable the Debug Module during STOP mode
1708   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
1709   * @retval None
1710   */
LL_DBGMCU_EnableDBGStopMode(void)1711 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1712 {
1713   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1714 }
1715 
1716 /**
1717   * @brief  Disable the Debug Module during STOP mode
1718   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
1719   * @retval None
1720   */
LL_DBGMCU_DisableDBGStopMode(void)1721 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1722 {
1723   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1724 }
1725 
1726 /**
1727   * @brief  Enable the Debug Module during STANDBY mode
1728   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
1729   * @retval None
1730   */
LL_DBGMCU_EnableDBGStandbyMode(void)1731 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1732 {
1733   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1734 }
1735 
1736 /**
1737   * @brief  Disable the Debug Module during STANDBY mode
1738   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
1739   * @retval None
1740   */
LL_DBGMCU_DisableDBGStandbyMode(void)1741 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1742 {
1743   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1744 }
1745 
1746 /**
1747   * @brief  Enable the Debug Clock Trace
1748   * @rmtoll DBGMCU_CR    TRACE_CLKEN   LL_DBGMCU_EnableTraceClock
1749   * @retval None
1750   */
LL_DBGMCU_EnableTraceClock(void)1751 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1752 {
1753   SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1754 }
1755 
1756 /**
1757   * @brief  Disable the Debug Clock Trace
1758   * @rmtoll DBGMCU_CR    TRACE_CLKEN   LL_DBGMCU_DisableTraceClock
1759   * @retval None
1760   */
LL_DBGMCU_DisableTraceClock(void)1761 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1762 {
1763   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN);
1764 }
1765 
1766 
1767 /**
1768   * @brief  Check if clock trace is enabled or disabled.
1769   * @rmtoll DBGMCU_CR_TRACE_CLKEN      LL_DBGMCU_IsEnabledTraceClock
1770   * @retval State of bit (1 or 0).
1771   */
LL_DBGMCU_IsEnabledTraceClock(void)1772 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1773 {
1774   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL);
1775 }
1776 
1777 /**
1778   * @brief  Set Trace pin assignment control
1779   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
1780   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
1781   * @param  PinAssignment This parameter can be one of the following values:
1782   *         @arg @ref LL_DBGMCU_TRACE_NONE
1783   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
1784   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1785   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1786   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1787   * @retval None
1788   */
LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)1789 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1790 {
1791   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1792 }
1793 
1794 /**
1795   * @brief  Get Trace pin assignment control
1796   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
1797   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
1798   * @retval Returned value can be one of the following values:
1799   *         @arg @ref LL_DBGMCU_TRACE_NONE
1800   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
1801   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1802   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1803   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1804   */
LL_DBGMCU_GetTracePinAssignment(void)1805 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1806 {
1807   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1808 }
1809 
1810 /**
1811   * @brief  Freeze APB1 peripherals (group1 peripherals)
1812   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
1813   * @param  Periphs This parameter can be a combination of the following values:
1814   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1815   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1816   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1817   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1818   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1819   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1820   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1821   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1822   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1823   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1824   * @retval None
1825   */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1826 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1827 {
1828   SET_BIT(DBGMCU->APB1FZR1, Periphs);
1829 }
1830 
1831 /**
1832   * @brief  Freeze APB1 peripherals (group2 peripherals)
1833   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
1834   * @param  Periphs This parameter can be a combination of the following values:
1835   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
1836   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1837   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C5_STOP (*)
1838   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C6_STOP (*)
1839   * @retval None
1840   * @note   (*) Availability depends on devices.
1841   */
LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)1842 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
1843 {
1844   SET_BIT(DBGMCU->APB1FZR2, Periphs);
1845 }
1846 
1847 /**
1848   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
1849   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1850   * @param  Periphs This parameter can be a combination of the following values:
1851   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1852   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1853   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1854   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1855   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1856   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1857   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1858   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1859   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1860   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1861   * @retval None
1862   */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1863 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1864 {
1865   CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
1866 }
1867 
1868 /**
1869   * @brief  Unfreeze APB1 peripherals (group2 peripherals)
1870   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
1871   * @param  Periphs This parameter can be a combination of the following values:
1872   *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP
1873   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
1874   * @retval None
1875   */
LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)1876 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
1877 {
1878   CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
1879 }
1880 
1881 /**
1882   * @brief  Freeze APB2 peripherals
1883   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
1884   * @param  Periphs This parameter can be a combination of the following values:
1885   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1886   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1887   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1888   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1889   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1890   * @retval None
1891   */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1892 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1893 {
1894   SET_BIT(DBGMCU->APB2FZR, Periphs);
1895 }
1896 
1897 /**
1898   * @brief  Unfreeze APB2 peripherals
1899   * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1900   * @param  Periphs This parameter can be a combination of the following values:
1901   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1902   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
1903   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1904   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1905   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1906   * @retval None
1907   */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1908 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1909 {
1910   CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1911 }
1912 
1913 /**
1914   * @brief  Freeze APB3 peripherals
1915   * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP  LL_DBGMCU_APB3_GRP1_FreezePeriph
1916   * @param  Periphs This parameter can be a combination of the following values:
1917   *         @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1918   *         @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1919   *         @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
1920   *         @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
1921   *         @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1922   * @retval None
1923   */
LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)1924 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)
1925 {
1926   SET_BIT(DBGMCU->APB3FZR, Periphs);
1927 }
1928 
1929 /**
1930   * @brief  Unfreeze APB3 peripherals
1931   * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP  LL_DBGMCU_APB3_GRP1_UnFreezePeriph
1932   * @param  Periphs This parameter can be a combination of the following values:
1933   *         @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP
1934   *         @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP
1935   *         @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP
1936   *         @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP
1937   *         @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP
1938   * @retval None
1939   */
LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)1940 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)
1941 {
1942   CLEAR_BIT(DBGMCU->APB3FZR, Periphs);
1943 }
1944 
1945 /**
1946   * @brief  Freeze AHB1 peripherals
1947   * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP  LL_DBGMCU_AHB1_GRP1_FreezePeriph
1948   * @param  Periphs This parameter can be a combination of the following values:
1949   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
1950   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
1951   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
1952   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
1953   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
1954   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
1955   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
1956   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
1957   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
1958   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
1959   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
1960   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
1961   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
1962   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
1963   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
1964   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
1965   * @retval None
1966   */
LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)1967 __STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)
1968 {
1969   SET_BIT(DBGMCU->AHB1FZR, Periphs);
1970 }
1971 
1972 /**
1973   * @brief  Unfreeze AHB1 peripherals
1974   * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP  LL_DBGMCU_AHB1_GRP1_FreezePeriph
1975   * @param  Periphs This parameter can be a combination of the following values:
1976   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
1977   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
1978   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
1979   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
1980   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
1981   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
1982   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
1983   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
1984   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
1985   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
1986   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
1987   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
1988   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
1989   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
1990   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
1991   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
1992   * @retval None
1993   */
LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)1994 __STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1995 {
1996   CLEAR_BIT(DBGMCU->AHB1FZR, Periphs);
1997 }
1998 
1999 /**
2000   * @brief  Freeze AHB3 peripherals
2001   * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP  LL_DBGMCU_AHB3_GRP1_FreezePeriph
2002   * @param  Periphs This parameter can be a combination of the following values:
2003   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP
2004   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP
2005   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP
2006   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP
2007   * @retval None
2008   */
LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs)2009 __STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs)
2010 {
2011   SET_BIT(DBGMCU->AHB3FZR, Periphs);
2012 }
2013 
2014 /**
2015   * @brief  Unfreeze AHB3 peripherals
2016   * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP  LL_DBGMCU_AHB3_GRP1_FreezePeriph
2017   * @param  Periphs This parameter can be a combination of the following values:
2018   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP
2019   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP
2020   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP
2021   *         @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP
2022   * @retval None
2023   */
LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs)2024 __STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs)
2025 {
2026   CLEAR_BIT(DBGMCU->AHB3FZR, Periphs);
2027 }
2028 
2029 /**
2030   * @}
2031   */
2032 
2033 #if defined(VREFBUF)
2034 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
2035   * @{
2036   */
2037 
2038 /**
2039   * @brief  Enable Internal voltage reference
2040   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
2041   * @retval None
2042   */
LL_VREFBUF_Enable(void)2043 __STATIC_INLINE void LL_VREFBUF_Enable(void)
2044 {
2045   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
2046 }
2047 
2048 /**
2049   * @brief  Disable Internal voltage reference
2050   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
2051   * @retval None
2052   */
LL_VREFBUF_Disable(void)2053 __STATIC_INLINE void LL_VREFBUF_Disable(void)
2054 {
2055   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
2056 }
2057 
2058 /**
2059   * @brief  Enable high impedance (VREF+pin is high impedance)
2060   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
2061   * @retval None
2062   */
LL_VREFBUF_EnableHIZ(void)2063 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
2064 {
2065   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
2066 }
2067 
2068 /**
2069   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
2070   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
2071   * @retval None
2072   */
LL_VREFBUF_DisableHIZ(void)2073 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
2074 {
2075   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
2076 }
2077 
2078 /**
2079   * @brief  Set the Voltage reference scale
2080   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
2081   * @param  Scale This parameter can be one of the following values:
2082   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
2083   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
2084   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
2085   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
2086   * @retval None
2087   */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)2088 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
2089 {
2090   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
2091 }
2092 
2093 /**
2094   * @brief  Get the Voltage reference scale
2095   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
2096   * @retval Returned value can be one of the following values:
2097   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
2098   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
2099   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
2100   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
2101   */
LL_VREFBUF_GetVoltageScaling(void)2102 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
2103 {
2104   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
2105 }
2106 
2107 /**
2108   * @brief  Check if Voltage reference buffer is ready
2109   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
2110   * @retval State of bit (1 or 0).
2111   */
LL_VREFBUF_IsVREFReady(void)2112 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
2113 {
2114   return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
2115 }
2116 
2117 /**
2118   * @brief  Get the trimming code for VREFBUF calibration
2119   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
2120   * @retval Between 0 and 0x3F
2121   */
LL_VREFBUF_GetTrimming(void)2122 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
2123 {
2124   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
2125 }
2126 
2127 /**
2128   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
2129   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
2130   * @param  Value Between 0 and 0x3F
2131   * @retval None
2132   */
LL_VREFBUF_SetTrimming(uint32_t Value)2133 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
2134 {
2135   WRITE_REG(VREFBUF->CCR, Value);
2136 }
2137 
2138 /**
2139   * @}
2140   */
2141 #endif /* VREFBUF */
2142 
2143 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
2144   * @{
2145   */
2146 
2147 /**
2148   * @brief  Set FLASH Latency
2149   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
2150   * @param  Latency This parameter can be one of the following values:
2151   *         @arg @ref LL_FLASH_LATENCY_0
2152   *         @arg @ref LL_FLASH_LATENCY_1
2153   *         @arg @ref LL_FLASH_LATENCY_2
2154   *         @arg @ref LL_FLASH_LATENCY_3
2155   *         @arg @ref LL_FLASH_LATENCY_4
2156   *         @arg @ref LL_FLASH_LATENCY_5
2157   *         @arg @ref LL_FLASH_LATENCY_6
2158   *         @arg @ref LL_FLASH_LATENCY_7
2159   *         @arg @ref LL_FLASH_LATENCY_8
2160   *         @arg @ref LL_FLASH_LATENCY_9
2161   *         @arg @ref LL_FLASH_LATENCY_10
2162   *         @arg @ref LL_FLASH_LATENCY_11
2163   *         @arg @ref LL_FLASH_LATENCY_12
2164   *         @arg @ref LL_FLASH_LATENCY_13
2165   *         @arg @ref LL_FLASH_LATENCY_14
2166   *         @arg @ref LL_FLASH_LATENCY_15
2167   * @retval None
2168   */
LL_FLASH_SetLatency(uint32_t Latency)2169 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2170 {
2171   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2172 }
2173 
2174 /**
2175   * @brief  Get FLASH Latency
2176   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
2177   * @retval Returned value can be one of the following values:
2178   *         @arg @ref LL_FLASH_LATENCY_0
2179   *         @arg @ref LL_FLASH_LATENCY_1
2180   *         @arg @ref LL_FLASH_LATENCY_2
2181   *         @arg @ref LL_FLASH_LATENCY_3
2182   *         @arg @ref LL_FLASH_LATENCY_4
2183   *         @arg @ref LL_FLASH_LATENCY_5
2184   *         @arg @ref LL_FLASH_LATENCY_6
2185   *         @arg @ref LL_FLASH_LATENCY_7
2186   *         @arg @ref LL_FLASH_LATENCY_8
2187   *         @arg @ref LL_FLASH_LATENCY_9
2188   *         @arg @ref LL_FLASH_LATENCY_10
2189   *         @arg @ref LL_FLASH_LATENCY_11
2190   *         @arg @ref LL_FLASH_LATENCY_12
2191   *         @arg @ref LL_FLASH_LATENCY_13
2192   *         @arg @ref LL_FLASH_LATENCY_14
2193   *         @arg @ref LL_FLASH_LATENCY_15
2194   */
LL_FLASH_GetLatency(void)2195 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2196 {
2197   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2198 }
2199 
2200 /**
2201   * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
2202   * @note Flash memory can be put in power-down mode only when the code is executed
2203   *       from RAM
2204   * @note Flash must not be accessed when power down is enabled
2205   * @note Flash must not be put in power-down while a program or an erase operation
2206   *       is on-going
2207   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
2208   *         FLASH_PDKEYR PDKEY1_1      LL_FLASH_EnableRunPowerDown\n
2209   *         FLASH_PDKEYR PDKEY1_2      LL_FLASH_EnableRunPowerDown\n
2210   *         FLASH_PDKEYR PDKEY2_1      LL_FLASH_EnableRunPowerDown\n
2211   *         FLASH_PDKEYR PDKEY2_2      LL_FLASH_EnableRunPowerDown
2212   * @retval None
2213   */
LL_FLASH_EnableRunPowerDown(void)2214 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
2215 {
2216   /* Following values must be written consecutively to unlock the RUN_PD bit in
2217   FLASH_ACR */
2218   WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
2219   WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
2220   WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
2221   WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
2222 
2223   /*Request to enter flash in power mode */
2224   SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2);
2225 }
2226 
2227 /**
2228   * @brief  Enable flash Power-down mode during run mode or Low-power run mode of bank1
2229   * @note   Bank 1 of flash memory can be put in power-down mode only when the code is executed
2230   *       from RAM
2231   * @note Bank1 of flash must not be accessed when power down is enabled
2232   * @note Bank1 of flash must not be put in power-down while a program or an erase operation
2233   *       is on-going
2234   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
2235   *         FLASH_PDKEYR PDKEY1_1      LL_FLASH_EnableRunPowerDown\n
2236   *         FLASH_PDKEYR PDKEY1_2      LL_FLASH_EnableRunPowerDown\n
2237   * @retval None
2238   */
LL_FLASH_EnableRunPowerDownBank1(void)2239 __STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank1(void)
2240 {
2241   /* Following values must be written consecutively to unlock the RUN_PD bit in
2242   FLASH_ACR */
2243   WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1);
2244   WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2);
2245 
2246   /*Request to enter flash in power mode */
2247   SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
2248 }
2249 
2250 /**
2251   * @brief  Enable flash Power-down mode during run mode or Low-power run mode of Bank2
2252   * @note   Bank 2 of flash memory can be put in power-down mode only when the code is executed
2253   *       from RAM
2254   * @note Bank2 of flash must not be accessed when power down is enabled
2255   * @note Bank2 of flash must not be put in power-down while a program or an erase operation
2256   *       is on-going
2257   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
2258   *         FLASH_PDKEYR PDKEY2_1      LL_FLASH_EnableRunPowerDown\n
2259   *         FLASH_PDKEYR PDKEY2_2      LL_FLASH_EnableRunPowerDown\n
2260   * @retval None
2261   */
LL_FLASH_EnableRunPowerDownBank2(void)2262 __STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank2(void)
2263 {
2264   /* Following values must be written consecutively to unlock the RUN_PD bit in
2265   FLASH_ACR */
2266   WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1);
2267   WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2);
2268 
2269   /*Request to enter flash in power mode */
2270   SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
2271 }
2272 
2273 /**
2274   * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
2275   * @note Flash must not be put in power-down while a program or an erase operation
2276   *       is on-going
2277   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
2278   * @retval None
2279   */
LL_FLASH_EnableSleepPowerDown(void)2280 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
2281 {
2282   SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
2283 }
2284 
2285 /**
2286   * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
2287   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
2288   * @retval None
2289   */
LL_FLASH_DisableSleepPowerDown(void)2290 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
2291 {
2292   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
2293 }
2294 /**
2295   * @}
2296   */
2297 
2298 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
2299 
2300 /**
2301   * @}
2302   */
2303 
2304 /**
2305   * @}
2306   */
2307 
2308 /**
2309   * @}
2310   */
2311 
2312 #ifdef __cplusplus
2313 }
2314 #endif
2315 
2316 #endif /* STM32u5xx_LL_SYSTEM_H */
2317