1 /**
2   ******************************************************************************
3   * @file    stm32h7rsxx_ll_system.h
4   * @author  MCD Application Team
5   * @brief   Header file of SYSTEM LL module.
6   *
7   ******************************************************************************
8   * @attention
9   *
10   * Copyright (c) 2022 STMicroelectronics.
11   * All rights reserved.
12   *
13   * This software is licensed under terms that can be found in the LICENSE file
14   * in the root directory of this software component.
15   * If no LICENSE file comes with this software, it is provided AS-IS.
16   *
17   ******************************************************************************
18   @verbatim
19   ==============================================================================
20                      ##### How to use this driver #####
21   ==============================================================================
22     [..]
23     The LL SYSTEM driver contains a set of generic APIs that can be
24     used by user:
25       (+) Some of the FLASH features need to be handled in the SYSTEM file.
26       (+) Access to DBGCMU registers
27       (+) Access to SBS registers
28       (+) Access to VREFBUF registers
29 
30   @endverbatim
31   */
32 
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32H7RSxx_LL_SYSTEM_H
35 #define STM32H7RSxx_LL_SYSTEM_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32h7rsxx.h"
43 
44 /** @addtogroup STM32H7RSxx_LL_Driver
45   * @{
46   */
47 
48 #if defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF)
49 
50 /** @defgroup SYSTEM_LL SYSTEM
51   * @{
52   */
53 
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56 /* Private constants ---------------------------------------------------------*/
57 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
58   * @{
59   */
60 #define LL_SBS_REGISTER_PINPOS_SHFT   16U                                 /*!< Define used to shift pin position in EXTICR register */
61 #define LL_SBS_HDPL_INCREMENT_VALUE   0x6AU                               /*!< Define used for the HDPL increment */
62 #define LL_SBS_DBG_UNLOCK             (0xB4U << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< Define used to unlock debug */
63 #define LL_SBS_ACCESS_PORT_UNLOCK     0xB4U                               /*!< Define used to unlock access port */
64 #define LL_SBS_DBG_CONFIG_LOCK        0xC3U                               /*!< Define used to lock debug configuration */
65 #define LL_SBS_DBG_CONFIG_UNLOCK      0xB4U                               /*!< Define used to unlock debug configuration */
66 /**
67   * @}
68   */
69 
70 /* Private macros ------------------------------------------------------------*/
71 
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
75   * @{
76   */
77 
78 /** @defgroup SYSTEM_LL_EC_SBS_HDPL SBS hide protection level
79   * @{
80   */
81 #define LL_SBS_HDPL0                  0xB4U /*!< Hide protection level 0 */
82 #define LL_SBS_HDPL1                  0x51U /*!< Hide protection level 1 */
83 #define LL_SBS_HDPL2                  0x8AU /*!< Hide protection level 2 */
84 #define LL_SBS_HDPL3                  0x6FU /*!< Hide protection level 3 */
85 /**
86   * @}
87   */
88 
89 /** @defgroup SYSTEM_LL_EC_SBS_AXISRAM_WS SBS AXISRAM wait state number (when ECC=0)
90   * @{
91   */
92 #define LL_SBS_AXISRAM_NO_WS          0U                    /*!< No wait state added when accessing AXISRAM */
93 #define LL_SBS_AXISRAM_ONE_WS         SBS_PMCR_AXISRAM_WS   /*!< One wait state added when accessing AXISRAM */
94 /**
95   * @}
96   */
97 
98 /** @defgroup SYSTEM_LL_EC_SBS_ETH_PHYSEL SBS Ethernet PHY interface selection
99   * @{
100   */
101 #define LL_SBS_ETH_PHYSEL_GMII_MII    0U                    /*!< GMII or MII interface */
102 #define LL_SBS_ETH_PHYSEL_RMII        SBS_PMCR_ETH_PHYSEL_2 /*!< RMII interface */
103 /**
104   * @}
105   */
106 
107 /** @defgroup SYSTEM_LL_EC_SBS_BOOSTVDDSEL SBS Booster Vdd selection
108   * @{
109   */
110 #define LL_SBS_BOOSTVDDSEL_VDDA       0U                   /*!< Vdda selected as analog switch booster voltage supply */
111 #define LL_SBS_BOOSTVDDSEL_VDD        SBS_PMCR_BOOSTVDDSEL /*!< Vdd selected as analog switch booster voltage supply */
112 /**
113   * @}
114   */
115 
116 /** @defgroup SYSTEM_LL_EC_SBS_XSPI2_COMP_CODESEL SBS XSPI2 compensation cell code selection
117   * @{
118   */
119 #define LL_SBS_XSPI2_CODE_CELL        0U                           /*!< Code applied to compensation cell from cell */
120 #define LL_SBS_XSPI2_CODE_REG         SBS_CCCSR_XSPI2_COMP_CODESEL /*!< Code applied to compensation cell from register */
121 /**
122   * @}
123   */
124 
125 /** @defgroup SYSTEM_LL_EC_SBS_XSPI1_COMP_CODESEL SBS XSPI1 compensation cell code selection
126   * @{
127   */
128 #define LL_SBS_XSPI1_CODE_CELL        0U                           /*!< Code applied to compensation cell from cell */
129 #define LL_SBS_XSPI1_CODE_REG         SBS_CCCSR_XSPI1_COMP_CODESEL /*!< Code applied to compensation cell from register */
130 /**
131   * @}
132   */
133 
134 /** @defgroup SYSTEM_LL_EC_SBS_COMP_CODESEL SBS I/O compensation cell code selection
135   * @{
136   */
137 #define LL_SBS_IO_CODE_CELL           0U                     /*!< Code applied to compensation cell from cell */
138 #define LL_SBS_IO_CODE_REG            SBS_CCCSR_COMP_CODESEL /*!< Code applied to compensation cell from register */
139 /**
140   * @}
141   */
142 
143 /** @defgroup SYSTEM_LL_EC_SBS_TIMBREAK SBS break lockup input timer peripherals
144   * @{
145   */
146 #define LL_SBS_TIMBREAK_PVD           SBS_BKLOCKR_PVD_BL      /*!< Connect the PVD output with TIM1/15/16/17 break input                                 */
147 #define LL_SBS_TIMBREAK_FLASHECC      SBS_BKLOCKR_FLASHECC_BL /*!< Connect the Flash ECC double error detection flag with TIM1/15/16/17 break input      */
148 #define LL_SBS_TIMBREAK_CM7LCKUP      SBS_BKLOCKR_CM7LCKUP_BL /*!< Connect the Cortex M7 lockup output with TIM1/15/16/17 break input                    */
149 #define LL_SBS_TIMBREAK_BKRAMECC      SBS_BKLOCKR_BKRAMECC_BL /*!< Connect the Backup RAM ECC double error detection flag with TIM1/15/16/17 break input */
150 #define LL_SBS_TIMBREAK_DTCMECC       SBS_BKLOCKR_DTCMECC_BL  /*!< Connect the DTCM ECC double error detection flag with TIM1/15/16/17 break input       */
151 #define LL_SBS_TIMBREAK_ITCMECC       SBS_BKLOCKR_ITCMECC_BL  /*!< Connect the ITCM ECC double error detection flag with TIM1/15/16/17 break input       */
152 #define LL_SBS_TIMBREAK_ARAM3ECC      SBS_BKLOCKR_ARAM3ECC_BL /*!< Connect the AXISRAM3 ECC double error detection flag with TIM1/15/16/17 break input    */
153 #define LL_SBS_TIMBREAK_ARAM1ECC      SBS_BKLOCKR_ARAM1ECC_BL /*!< Connect the AXISRAM1 ECC double error detection flag with TIM1/15/16/17 break input    */
154 /**
155   * @}
156   */
157 
158 /** @defgroup SYSTEM_LL_EC_SBS_EXTI_PORT SBS EXTI PORT
159   * @{
160   */
161 #define LL_SBS_EXTI_PORTA             0U                                                   /*!< EXTI PORT A */
162 #define LL_SBS_EXTI_PORTB             SBS_EXTICR1_PC_EXTI0_0                               /*!< EXTI PORT B */
163 #define LL_SBS_EXTI_PORTC             SBS_EXTICR1_PC_EXTI0_1                               /*!< EXTI PORT C */
164 #define LL_SBS_EXTI_PORTD             (SBS_EXTICR1_PC_EXTI0_1 | SBS_EXTICR1_PC_EXTI0_0)    /*!< EXTI PORT D */
165 #define LL_SBS_EXTI_PORTE             SBS_EXTICR1_PC_EXTI0_2                               /*!< EXTI PORT E */
166 #define LL_SBS_EXTI_PORTF             (SBS_EXTICR1_PC_EXTI0_2 | SBS_EXTICR1_PC_EXTI0_0)    /*!< EXTI PORT F */
167 #define LL_SBS_EXTI_PORTG             (SBS_EXTICR1_PC_EXTI0_2 | SBS_EXTICR1_PC_EXTI0_1)    /*!< EXTI PORT G */
168 #define LL_SBS_EXTI_PORTH             (SBS_EXTICR1_PC_EXTI0_2 | SBS_EXTICR1_PC_EXTI0_1 | \
169                                        SBS_EXTICR1_PC_EXTI0_0)                             /*!< EXTI PORT H */
170 #define LL_SBS_EXTI_PORTM             (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2)    /*!< EXTI PORT M */
171 #define LL_SBS_EXTI_PORTN             (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2 | \
172                                        SBS_EXTICR1_PC_EXTI0_0)                             /*!< EXTI PORT N */
173 #define LL_SBS_EXTI_PORTO             (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2 | \
174                                        SBS_EXTICR1_PC_EXTI0_1)                             /*!< EXTI PORT 0 */
175 #define LL_SBS_EXTI_PORTP             (SBS_EXTICR1_PC_EXTI0_3 | SBS_EXTICR1_PC_EXTI0_2 | \
176                                        SBS_EXTICR1_PC_EXTI0_1 | SBS_EXTICR1_PC_EXTI0_0)    /*!< EXTI PORT P */
177 /**
178   * @}
179   */
180 
181 /** @defgroup SYSTEM_LL_EC_SBS_EXTI_LINE SBS EXTI LINE
182   * @{
183   */
184 #define LL_SBS_EXTI_LINE0             ((0U  << LL_SBS_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */
185 #define LL_SBS_EXTI_LINE1             ((4U  << LL_SBS_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */
186 #define LL_SBS_EXTI_LINE2             ((8U  << LL_SBS_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_16 | EXTICR[0] */
187 #define LL_SBS_EXTI_LINE3             ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 0U)  /*!< EXTI_POSITION_24 | EXTICR[0] */
188 #define LL_SBS_EXTI_LINE4             ((0U  << LL_SBS_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */
189 #define LL_SBS_EXTI_LINE5             ((4U  << LL_SBS_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */
190 #define LL_SBS_EXTI_LINE6             ((8U  << LL_SBS_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_16 | EXTICR[1] */
191 #define LL_SBS_EXTI_LINE7             ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 1U)  /*!< EXTI_POSITION_24 | EXTICR[1] */
192 #define LL_SBS_EXTI_LINE8             ((0U  << LL_SBS_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */
193 #define LL_SBS_EXTI_LINE9             ((4U  << LL_SBS_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */
194 #define LL_SBS_EXTI_LINE10            ((8U  << LL_SBS_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_16 | EXTICR[2] */
195 #define LL_SBS_EXTI_LINE11            ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 2U)  /*!< EXTI_POSITION_24 | EXTICR[2] */
196 #define LL_SBS_EXTI_LINE12            ((0U  << LL_SBS_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */
197 #define LL_SBS_EXTI_LINE13            ((4U  << LL_SBS_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */
198 #define LL_SBS_EXTI_LINE14            ((8U  << LL_SBS_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_16 | EXTICR[3] */
199 #define LL_SBS_EXTI_LINE15            ((12U << LL_SBS_REGISTER_PINPOS_SHFT) | 3U)  /*!< EXTI_POSITION_24 | EXTICR[3] */
200 /**
201   * @}
202   */
203 
204 /** @defgroup SYSTEM_LL_EC_DBGMCU_DCRT DBGMCU Debug credential reset type
205   * @{
206   */
207 #define LL_DBGMCU_DCRT_SYSTEM         0U              /*!< System reset revoke the debug authentication credentials */
208 #define LL_DBGMCU_DCRT_POWER          DBGMCU_CR_DCRT  /*!< Power reset revoke the debug authentication credentials */
209 /**
210   * @}
211   */
212 
213 /** @defgroup SYSTEM_LL_EC_DBGMCU_AHB5_STOP DBGMCU AHB5 GRP1 STOP
214   * @{
215   */
216 #define LL_DBGMCU_AHB5_GRP1_HPDMA0_STOP    DBGMCU_AHB5FZR_HPDMA_0   /*!< The counter clock of HPDMA0 is stopped when the core is halted*/
217 #define LL_DBGMCU_AHB5_GRP1_HPDMA1_STOP    DBGMCU_AHB5FZR_HPDMA_1   /*!< The counter clock of HPDMA1 is stopped when the core is halted*/
218 #define LL_DBGMCU_AHB5_GRP1_HPDMA2_STOP    DBGMCU_AHB5FZR_HPDMA_2   /*!< The counter clock of HPDMA2 is stopped when the core is halted*/
219 #define LL_DBGMCU_AHB5_GRP1_HPDMA3_STOP    DBGMCU_AHB5FZR_HPDMA_3   /*!< The counter clock of HPDMA3 is stopped when the core is halted*/
220 #define LL_DBGMCU_AHB5_GRP1_HPDMA4_STOP    DBGMCU_AHB5FZR_HPDMA_4   /*!< The counter clock of HPDMA4 is stopped when the core is halted*/
221 #define LL_DBGMCU_AHB5_GRP1_HPDMA5_STOP    DBGMCU_AHB5FZR_HPDMA_5   /*!< The counter clock of HPDMA5 is stopped when the core is halted*/
222 #define LL_DBGMCU_AHB5_GRP1_HPDMA6_STOP    DBGMCU_AHB5FZR_HPDMA_6   /*!< The counter clock of HPDMA6 is stopped when the core is halted*/
223 #define LL_DBGMCU_AHB5_GRP1_HPDMA7_STOP    DBGMCU_AHB5FZR_HPDMA_7   /*!< The counter clock of HPDMA7 is stopped when the core is halted*/
224 #define LL_DBGMCU_AHB5_GRP1_HPDMA8_STOP    DBGMCU_AHB5FZR_HPDMA_8   /*!< The counter clock of HPDMA8 is stopped when the core is halted*/
225 #define LL_DBGMCU_AHB5_GRP1_HPDMA9_STOP    DBGMCU_AHB5FZR_HPDMA_9   /*!< The counter clock of HPDMAM9 is stopped when the core is halted*/
226 #define LL_DBGMCU_AHB5_GRP1_HPDMA10_STOP   DBGMCU_AHB5FZR_HPDMA_10  /*!< The counter clock of HPDMAM10 is stopped when the core is halted*/
227 #define LL_DBGMCU_AHB5_GRP1_HPDMA11_STOP   DBGMCU_AHB5FZR_HPDMA_11  /*!< The counter clock of HPDMAM11 is stopped when the core is halted*/
228 #define LL_DBGMCU_AHB5_GRP1_HPDMA12_STOP   DBGMCU_AHB5FZR_HPDMA_12  /*!< The counter clock of HPDMAM12 is stopped when the core is halted*/
229 #define LL_DBGMCU_AHB5_GRP1_HPDMA13_STOP   DBGMCU_AHB5FZR_HPDMA_13  /*!< The counter clock of HPDMAM13 is stopped when the core is halted*/
230 #define LL_DBGMCU_AHB5_GRP1_HPDMA14_STOP   DBGMCU_AHB5FZR_HPDMA_14  /*!< The counter clock of HPDMAM14 is stopped when the core is halted*/
231 #define LL_DBGMCU_AHB5_GRP1_HPDMA15_STOP   DBGMCU_AHB5FZR_HPDMA_15  /*!< The counter clock of HPDMAM15 is stopped when the core is halted*/
232 /**
233   * @}
234   */
235 
236 /** @defgroup SYSTEM_LL_EC_DBGMCU_AHB1_STOP DBGMCU AHB1 GRP1 STOP
237   * @{
238   */
239 #define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP    DBGMCU_AHB1FZR_GPDMA_0   /*!< The counter clock of GPDMA0 is stopped when the core is halted*/
240 #define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP    DBGMCU_AHB1FZR_GPDMA_1   /*!< The counter clock of GPDMA1 is stopped when the core is halted*/
241 #define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP    DBGMCU_AHB1FZR_GPDMA_2   /*!< The counter clock of GPDMA2 is stopped when the core is halted*/
242 #define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP    DBGMCU_AHB1FZR_GPDMA_3   /*!< The counter clock of GPDMA3 is stopped when the core is halted*/
243 #define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP    DBGMCU_AHB1FZR_GPDMA_4   /*!< The counter clock of GPDMA4 is stopped when the core is halted*/
244 #define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP    DBGMCU_AHB1FZR_GPDMA_5   /*!< The counter clock of GPDMA5 is stopped when the core is halted*/
245 #define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP    DBGMCU_AHB1FZR_GPDMA_6   /*!< The counter clock of GPDMA6 is stopped when the core is halted*/
246 #define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP    DBGMCU_AHB1FZR_GPDMA_7   /*!< The counter clock of GPDMA7 is stopped when the core is halted*/
247 #define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP    DBGMCU_AHB1FZR_GPDMA_8   /*!< The counter clock of GPDMA8 is stopped when the core is halted*/
248 #define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP    DBGMCU_AHB1FZR_GPDMA_9   /*!< The counter clock of GPDMAM9 is stopped when the core is halted*/
249 #define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP   DBGMCU_AHB1FZR_GPDMA_10  /*!< The counter clock of GPDMAM10 is stopped when the core is halted*/
250 #define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP   DBGMCU_AHB1FZR_GPDMA_11  /*!< The counter clock of GPDMAM11 is stopped when the core is halted*/
251 #define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP   DBGMCU_AHB1FZR_GPDMA_12  /*!< The counter clock of GPDMAM12 is stopped when the core is halted*/
252 #define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP   DBGMCU_AHB1FZR_GPDMA_13  /*!< The counter clock of GPDMAM13 is stopped when the core is halted*/
253 #define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP   DBGMCU_AHB1FZR_GPDMA_14  /*!< The counter clock of GPDMAM14 is stopped when the core is halted*/
254 #define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP   DBGMCU_AHB1FZR_GPDMA_15  /*!< The counter clock of GPDMAM15 is stopped when the core is halted*/
255 /**
256   * @}
257   */
258 
259 /** @defgroup SYSTEM_LL_EC_DBGMCU_APB1_STOP DBGMCU APB1 GRP1 STOP
260   * @{
261   */
262 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR_TIM2   /*!< The counter clock of TIM2 is stopped when the core is halted*/
263 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR_TIM3   /*!< The counter clock of TIM3 is stopped when the core is halted*/
264 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR_TIM4   /*!< The counter clock of TIM4 is stopped when the core is halted*/
265 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR_TIM5   /*!< The counter clock of TIM5 is stopped when the core is halted*/
266 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR_TIM6   /*!< The counter clock of TIM6 is stopped when the core is halted*/
267 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR_TIM7   /*!< The counter clock of TIM7 is stopped when the core is halted*/
268 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1FZR_TIM12  /*!< The counter clock of TIM12 is stopped when the core is halted*/
269 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1FZR_TIM13  /*!< The counter clock of TIM13 is stopped when the core is halted*/
270 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1FZR_TIM14  /*!< The counter clock of TIM14 is stopped when the core is halted*/
271 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR_LPTIM1 /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
272 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR_WWDG   /*!< The window watchdog counter clock is stopped when the core is halted*/
273 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR_I2C1   /*!< The I2C1 SMBus timeout is frozen*/
274 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR_I2C2   /*!< The I2C2 SMBus timeout is frozen*/
275 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR_I2C3   /*!< The I2C3 SMBus timeout is frozen*/
276 /**
277   * @}
278   */
279 
280 /** @defgroup SYSTEM_LL_EC_DBGMCU_APB2_STOP DBGMCU APB2 GRP1 STOP
281   * @{
282   */
283 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZR_TIM1     /*!< The counter clock of TIM1 is stopped when the core is halted*/
284 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2FZR_TIM9     /*!< The counter clock of TIM9 is stopped when the core is halted*/
285 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZR_TIM15    /*!< The counter clock of TIM15 is stopped when the core is halted*/
286 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZR_TIM16    /*!< The counter clock of TIM16 is stopped when the core is halted*/
287 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZR_TIM17    /*!< The counter clock of TIM17 is stopped when the core is halted*/
288 /**
289   * @}
290   */
291 
292 /** @defgroup SYSTEM_LL_EC_DBGMCU_APB4_STOP DBGMCU APB4 GRP1 STOP
293   * @{
294   */
295 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP    DBGMCU_APB4FZR_LPTIM2 /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
296 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP    DBGMCU_APB4FZR_LPTIM3 /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
297 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP    DBGMCU_APB4FZR_LPTIM4 /*!< The counter clock of LPTIM4 is stopped when the core is halted*/
298 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP    DBGMCU_APB4FZR_LPTIM5 /*!< The counter clock of LPTIM5 is stopped when the core is halted*/
299 #define LL_DBGMCU_APB4_GRP1_IWDG_STOP      DBGMCU_APB4FZR_IWDG   /*!< The counter clock of IWDG is stopped when the core is halted*/
300 #define LL_DBGMCU_APB4_GRP1_RTC_STOP       DBGMCU_APB4FZR_RTC    /*!< The counter clock of RTC is stopped when the core is halted*/
301 /**
302   * @}
303   */
304 
305 
306 #if defined(VREFBUF)
307 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
308   * @{
309   */
310 #define LL_VREFBUF_VOLTAGE_SCALE0          VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 0 (VREF_OUT1) */
311 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 1 (VREF_OUT2) */
312 #define LL_VREFBUF_VOLTAGE_SCALE2          VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 2 (VREF_OUT3) */
313 #define LL_VREFBUF_VOLTAGE_SCALE3          VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 3 (VREF_OUT4) */
314 /**
315   * @}
316   */
317 #endif /* VREFBUF */
318 
319 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
320   * @{
321   */
322 #define LL_FLASH_LATENCY_0        0                                                                 /*!< FLASH Zero wait state      */
323 #define LL_FLASH_LATENCY_1        FLASH_ACR_LATENCY_0                                               /*!< FLASH One wait state       */
324 #define LL_FLASH_LATENCY_2        FLASH_ACR_LATENCY_1                                               /*!< FLASH Two wait states      */
325 #define LL_FLASH_LATENCY_3        (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0)                       /*!< FLASH Three wait states    */
326 #define LL_FLASH_LATENCY_4        FLASH_ACR_LATENCY_2                                               /*!< FLASH Four wait states     */
327 #define LL_FLASH_LATENCY_5        (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0)                       /*!< FLASH Five wait state      */
328 #define LL_FLASH_LATENCY_6        (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1)                       /*!< FLASH Six wait state       */
329 #define LL_FLASH_LATENCY_7        (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Seven wait states    */
330 /**
331   * @}
332   */
333 
334 /**
335   * @}
336   */
337 
338 /* Exported macro ------------------------------------------------------------*/
339 
340 /* Exported functions --------------------------------------------------------*/
341 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
342   * @{
343   */
344 
345 /** @defgroup SYSTEM_LL_EF_SBS SBS
346   * @{
347   */
348 
349 /**
350   * @brief  Get initial vector for Cortex-M7
351   * @rmtoll SBS_BOOTSR INITVTOR      LL_SBS_GetBootAddress
352   * @retval Returned value is the physical boot address used by the Cortex-M7 after reset
353   */
LL_SBS_GetBootAddress(void)354 __STATIC_INLINE uint32_t LL_SBS_GetBootAddress(void)
355 {
356   return (uint32_t)(READ_BIT(SBS->BOOTSR, SBS_BOOTSR_INITVTOR));
357 }
358 
359 /**
360   * @brief  Increment hide protection level
361   * @rmtoll SBS_HDPLCR INCR_HDPL     LL_SBS_IncrementHDPL
362   * @retval None
363   */
LL_SBS_IncrementHDPL(void)364 __STATIC_INLINE void LL_SBS_IncrementHDPL(void)
365 {
366   MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, LL_SBS_HDPL_INCREMENT_VALUE);
367 }
368 
369 /**
370   * @brief  Get current hide protection level
371   * @rmtoll SBS_HDPLSR HDPL          LL_SBS_GetCurrentHDPL
372   * @retval Returned value is the current hide protection level of the device:
373   *         @arg @ref LL_SBS_HDPL0
374   *         @arg @ref LL_SBS_HDPL1
375   *         @arg @ref LL_SBS_HDPL2
376   *         @arg @ref LL_SBS_HDPL3
377   */
LL_SBS_GetCurrentHDPL(void)378 __STATIC_INLINE uint32_t LL_SBS_GetCurrentHDPL(void)
379 {
380   return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL));
381 }
382 
383 /**
384   * @brief  Set the authenticated debug hide protection level
385   * @rmtoll SBS_DBGCR DBG_AUTH_HDPL     LL_SBS_SetAuthDbgHDPL
386   * @param  Level This parameter can be one of the following values:
387   *         @arg @ref LL_SBS_HDPL1
388   *         @arg @ref LL_SBS_HDPL2
389   *         @arg @ref LL_SBS_HDPL3
390   * @retval None
391   */
LL_SBS_SetAuthDbgHDPL(uint32_t Level)392 __STATIC_INLINE void LL_SBS_SetAuthDbgHDPL(uint32_t Level)
393 {
394   MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos));
395 }
396 
397 /**
398   * @brief  Get current hide protection level
399   * @rmtoll SBS_DBGCR DBG_AUTH_HDPL     LL_SBS_GetAuthDbgHDPL
400   * @retval Returned value is the hide protection level where the authenticated debug is opened:
401   *         @arg @ref LL_SBS_HDPL1
402   *         @arg @ref LL_SBS_HDPL2
403   *         @arg @ref LL_SBS_HDPL3
404   */
LL_SBS_GetAuthDbgHDPL(void)405 __STATIC_INLINE uint32_t LL_SBS_GetAuthDbgHDPL(void)
406 {
407   return (uint32_t)(READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos);
408 }
409 
410 /**
411   * @brief  Unlock the debug
412   * @rmtoll SBS_DBGCR DBG_UNLOCK     LL_SBS_UnlockDebug
413   * @retval None
414   */
LL_SBS_UnlockDebug(void)415 __STATIC_INLINE void LL_SBS_UnlockDebug(void)
416 {
417   MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, LL_SBS_DBG_UNLOCK);
418 }
419 
420 /**
421   * @brief  Check if the debug is unlocked
422   * @rmtoll SBS_DBGCR DBG_UNLOCK     LL_SBS_IsUnlockedDebug
423   * @retval State of bit (1 or 0).
424   */
LL_SBS_IsUnlockedDebug(void)425 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebug(void)
426 {
427   return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK) == LL_SBS_DBG_UNLOCK) ? 1UL : 0UL);
428 }
429 
430 /**
431   * @brief  Unlock the access port
432   * @rmtoll SBS_DBGCR AP_UNLOCK     LL_SBS_UnlockAccessPort
433   * @retval None
434   */
LL_SBS_UnlockAccessPort(void)435 __STATIC_INLINE void LL_SBS_UnlockAccessPort(void)
436 {
437   MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, LL_SBS_ACCESS_PORT_UNLOCK);
438 }
439 
440 /**
441   * @brief  Check if the access port is unlocked
442   * @rmtoll SBS_DBGCR AP_UNLOCK     LL_SBS_IsUnlockedAccessPort
443   * @retval State of bit (1 or 0).
444   */
LL_SBS_IsUnlockedAccessPort(void)445 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedAccessPort(void)
446 {
447   return ((READ_BIT(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK) == LL_SBS_ACCESS_PORT_UNLOCK) ? 1UL : 0UL);
448 }
449 
450 /**
451   * @brief  Lock the debug configuration
452   * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK     LL_SBS_LockDebugConfig
453   * @retval None
454   */
LL_SBS_LockDebugConfig(void)455 __STATIC_INLINE void LL_SBS_LockDebugConfig(void)
456 {
457   MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_LOCK);
458 }
459 
460 /**
461   * @brief  Unlock the debug configuration
462   * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK     LL_SBS_UnlockDebugConfig
463   * @retval None
464   */
LL_SBS_UnlockDebugConfig(void)465 __STATIC_INLINE void LL_SBS_UnlockDebugConfig(void)
466 {
467   MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, LL_SBS_DBG_CONFIG_UNLOCK);
468 }
469 
470 /**
471   * @brief  Check if the debug configuration is unlocked
472   * @rmtoll SBS_DBGLOCKR DBGCFG_LOCK     LL_SBS_IsUnlockedDebugConfig
473   * @retval State of bit (1 or 0).
474   */
LL_SBS_IsUnlockedDebugConfig(void)475 __STATIC_INLINE uint32_t LL_SBS_IsUnlockedDebugConfig(void)
476 {
477   return ((READ_BIT(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK) == LL_SBS_DBG_CONFIG_UNLOCK) ? 1UL : 0UL);
478 }
479 
480 /**
481   * @brief  Set the command to be passed to RSS
482   * @rmtoll SBS_RSSCMDR RSSCMD     LL_SBS_SetRSSCmd
483   * @param  Command This parameter can have a value between 0 and 0xFFFF
484   * @retval None
485   */
LL_SBS_SetRSSCmd(uint32_t Command)486 __STATIC_INLINE void LL_SBS_SetRSSCmd(uint32_t Command)
487 {
488   MODIFY_REG(SBS->RSSCMDR, SBS_RSSCMDR_RSSCMD, Command);
489 }
490 
491 /**
492   * @brief  Get the command which will be passed to RSS
493   * @rmtoll SBS_RSSCMDR RSSCMD     LL_SBS_GetRSSCmd
494   * @retval Returned value is the command which will be passed to RSS (value between 0 and 0xFFFF)
495   */
LL_SBS_GetRSSCmd(void)496 __STATIC_INLINE uint32_t LL_SBS_GetRSSCmd(void)
497 {
498   return (uint32_t)(READ_BIT(SBS->RSSCMDR, SBS_RSSCMDR_RSSCMD));
499 }
500 
501 /**
502   * @brief  Set the number of AXISRAM wait state (when ECC=0)
503   * @rmtoll SBS_PMCR AXISRAM_WS     LL_SBS_SetAXISRAMWaitState
504   * @param  WaitState This parameter can be one of the following values:
505   *         @arg @ref LL_SBS_AXISRAM_NO_WS
506   *         @arg @ref LL_SBS_AXISRAM_ONE_WS
507   * @retval None
508   */
LL_SBS_SetAXISRAMWaitState(uint32_t WaitState)509 __STATIC_INLINE void LL_SBS_SetAXISRAMWaitState(uint32_t WaitState)
510 {
511   MODIFY_REG(SBS->PMCR, SBS_PMCR_AXISRAM_WS, WaitState);
512 }
513 
514 /**
515   * @brief  Get the number of AXISRAM wait state (when ECC=0)
516   * @rmtoll SBS_PMCR AXISRAM_WS     LL_SBS_GetAXISRAMWaitState
517   * @retval Returned value is the number of wait state when accessing AXISRAM:
518   *         @arg @ref LL_SBS_AXISRAM_NO_WS
519   *         @arg @ref LL_SBS_AXISRAM_ONE_WS
520   */
LL_SBS_GetAXISRAMWaitState(void)521 __STATIC_INLINE uint32_t LL_SBS_GetAXISRAMWaitState(void)
522 {
523   return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_AXISRAM_WS));
524 }
525 
526 /**
527   * @brief  Configure the Ethernet PHY interface
528   * @rmtoll SBS_PMCR ETH_PHYSEL     LL_SBS_SetEthernetPhy
529   * @param  Interface This parameter can be one of the following values:
530   *         @arg @ref LL_SBS_ETH_PHYSEL_GMII_MII
531   *         @arg @ref LL_SBS_ETH_PHYSEL_RMII
532   * @retval None
533   */
LL_SBS_SetEthernetPhy(uint32_t Interface)534 __STATIC_INLINE void LL_SBS_SetEthernetPhy(uint32_t Interface)
535 {
536   MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_PHYSEL, Interface);
537 }
538 
539 /**
540   * @brief  Get the selected Ethernet PHY interface
541   * @rmtoll SBS_PMCR ETH_PHYSEL     LL_SBS_GetEthernetPhy
542   * @retval Returned value is the selected Ethernet PHY interface:
543   *         @arg @ref LL_SBS_ETH_PHYSEL_GMII_MII
544   *         @arg @ref LL_SBS_ETH_PHYSEL_RMII
545   */
LL_SBS_GetEthernetPhy(void)546 __STATIC_INLINE uint32_t LL_SBS_GetEthernetPhy(void)
547 {
548   return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_ETH_PHYSEL));
549 }
550 
551 /**
552   * @brief  Configure the analog switch supply voltage for booster
553   * @rmtoll SBS_PMCR BOOSTVDDSEL     LL_SBS_SetBoosterVoltage
554   * @param  Voltage This parameter can be one of the following values:
555   *         @arg @ref LL_SBS_BOOSTVDDSEL_VDDA
556   *         @arg @ref LL_SBS_BOOSTVDDSEL_VDD
557   * @retval None
558   */
LL_SBS_SetBoosterVoltage(uint32_t Voltage)559 __STATIC_INLINE void LL_SBS_SetBoosterVoltage(uint32_t Voltage)
560 {
561   MODIFY_REG(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL, Voltage);
562 }
563 
564 /**
565   * @brief  Get the selected analog switch supply voltage for booster
566   * @rmtoll SBS_PMCR BOOSTVDDSEL     LL_SBS_GetBoosterVoltage
567   * @retval Returned value is the selected analog switch supply voltage:
568   *         @arg @ref LL_SBS_BOOSTVDDSEL_VDDA
569   *         @arg @ref LL_SBS_BOOSTVDDSEL_VDD
570   */
LL_SBS_GetBoosterVoltage(void)571 __STATIC_INLINE uint32_t LL_SBS_GetBoosterVoltage(void)
572 {
573   return (uint32_t)(READ_BIT(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL));
574 }
575 
576 /**
577   * @brief  Enable the booster
578   * @rmtoll SBS_PMCR BOOSTEN     LL_SBS_EnableBooster
579   * @retval None
580   */
LL_SBS_EnableBooster(void)581 __STATIC_INLINE void LL_SBS_EnableBooster(void)
582 {
583   SET_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN);
584 }
585 
586 /**
587   * @brief  Disable the booster
588   * @rmtoll SBS_PMCR BOOSTEN     LL_SBS_DisableBooster
589   * @retval None
590   */
LL_SBS_DisableBooster(void)591 __STATIC_INLINE void LL_SBS_DisableBooster(void)
592 {
593   CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN);
594 }
595 
596 /**
597   * @brief  Check if the booster is enabled
598   * @rmtoll SBS_PMCR BOOSTEN     LL_SBS_IsEnabledBooster
599   * @retval State of bit (1 or 0).
600   */
LL_SBS_IsEnabledBooster(void)601 __STATIC_INLINE uint32_t LL_SBS_IsEnabledBooster(void)
602 {
603   return ((READ_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN) != 0UL) ? 1UL : 0UL);
604 }
605 
606 /**
607   * @brief  Enable Floating Point Unit Invalid operation Interrupt
608   * @rmtoll SBS_FPUIMR FPU_IE_0      LL_SBS_EnableIT_FPU_IOC
609   * @retval None
610   */
LL_SBS_EnableIT_FPU_IOC(void)611 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IOC(void)
612 {
613   SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0);
614 }
615 
616 /**
617   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
618   * @rmtoll SBS_FPUIMR FPU_IE_1      LL_SBS_EnableIT_FPU_DZC
619   * @retval None
620   */
LL_SBS_EnableIT_FPU_DZC(void)621 __STATIC_INLINE void LL_SBS_EnableIT_FPU_DZC(void)
622 {
623   SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1);
624 }
625 
626 /**
627   * @brief  Enable Floating Point Unit Underflow Interrupt
628   * @rmtoll SBS_FPUIMR FPU_IE_2      LL_SBS_EnableIT_FPU_UFC
629   * @retval None
630   */
LL_SBS_EnableIT_FPU_UFC(void)631 __STATIC_INLINE void LL_SBS_EnableIT_FPU_UFC(void)
632 {
633   SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2);
634 }
635 
636 /**
637   * @brief  Enable Floating Point Unit Overflow Interrupt
638   * @rmtoll SBS_FPUIMR FPU_IE_3      LL_SBS_EnableIT_FPU_OFC
639   * @retval None
640   */
LL_SBS_EnableIT_FPU_OFC(void)641 __STATIC_INLINE void LL_SBS_EnableIT_FPU_OFC(void)
642 {
643   SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3);
644 }
645 
646 /**
647   * @brief  Enable Floating Point Unit Input denormal Interrupt
648   * @rmtoll SBS_FPUIMR FPU_IE_4      LL_SBS_EnableIT_FPU_IDC
649   * @retval None
650   */
LL_SBS_EnableIT_FPU_IDC(void)651 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IDC(void)
652 {
653   SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4);
654 }
655 
656 /**
657   * @brief  Enable Floating Point Unit Inexact Interrupt
658   * @rmtoll SBS_FPUIMR FPU_IE_5      LL_SBS_EnableIT_FPU_IXC
659   * @retval None
660   */
LL_SBS_EnableIT_FPU_IXC(void)661 __STATIC_INLINE void LL_SBS_EnableIT_FPU_IXC(void)
662 {
663   SET_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5);
664 }
665 
666 /**
667   * @brief  Disable Floating Point Unit Invalid operation Interrupt
668   * @rmtoll SBS_FPUIMR FPU_IE_0      LL_SBS_DisableIT_FPU_IOC
669   * @retval None
670   */
LL_SBS_DisableIT_FPU_IOC(void)671 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IOC(void)
672 {
673   CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0);
674 }
675 
676 /**
677   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
678   * @rmtoll SBS_FPUIMR FPU_IE_1      LL_SBS_DisableIT_FPU_DZC
679   * @retval None
680   */
LL_SBS_DisableIT_FPU_DZC(void)681 __STATIC_INLINE void LL_SBS_DisableIT_FPU_DZC(void)
682 {
683   CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1);
684 }
685 
686 /**
687   * @brief  Disable Floating Point Unit Underflow Interrupt
688   * @rmtoll SBS_FPUIMR FPU_IE_2      LL_SBS_DisableIT_FPU_UFC
689   * @retval None
690   */
LL_SBS_DisableIT_FPU_UFC(void)691 __STATIC_INLINE void LL_SBS_DisableIT_FPU_UFC(void)
692 {
693   CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2);
694 }
695 
696 /**
697   * @brief  Disable Floating Point Unit Overflow Interrupt
698   * @rmtoll SBS_FPUIMR FPU_IE_3      LL_SBS_DisableIT_FPU_OFC
699   * @retval None
700   */
LL_SBS_DisableIT_FPU_OFC(void)701 __STATIC_INLINE void LL_SBS_DisableIT_FPU_OFC(void)
702 {
703   CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3);
704 }
705 
706 /**
707   * @brief  Disable Floating Point Unit Input denormal Interrupt
708   * @rmtoll SBS_FPUIMR FPU_IE_4      LL_SBS_DisableIT_FPU_IDC
709   * @retval None
710   */
LL_SBS_DisableIT_FPU_IDC(void)711 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IDC(void)
712 {
713   CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4);
714 }
715 
716 /**
717   * @brief  Disable Floating Point Unit Inexact Interrupt
718   * @rmtoll SBS_FPUIMR FPU_IE_5      LL_SBS_DisableIT_FPU_IXC
719   * @retval None
720   */
LL_SBS_DisableIT_FPU_IXC(void)721 __STATIC_INLINE void LL_SBS_DisableIT_FPU_IXC(void)
722 {
723   CLEAR_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5);
724 }
725 
726 /**
727   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
728   * @rmtoll SBS_FPUIMR FPU_IE_0      LL_SBS_IsEnabledIT_FPU_IOC
729   * @retval State of bit (1 or 0).
730   */
LL_SBS_IsEnabledIT_FPU_IOC(void)731 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IOC(void)
732 {
733   return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_0) == SBS_FPUIMR_FPU_IE_0) ? 1UL : 0UL);
734 }
735 
736 /**
737   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
738   * @rmtoll SBS_FPUIMR FPU_IE_1      LL_SBS_IsEnabledIT_FPU_DZC
739   * @retval State of bit (1 or 0).
740   */
LL_SBS_IsEnabledIT_FPU_DZC(void)741 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_DZC(void)
742 {
743   return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_1) == SBS_FPUIMR_FPU_IE_1) ? 1UL : 0UL);
744 }
745 
746 /**
747   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
748   * @rmtoll SBS_FPUIMR FPU_IE_2      LL_SBS_IsEnabledIT_FPU_UFC
749   * @retval State of bit (1 or 0).
750   */
LL_SBS_IsEnabledIT_FPU_UFC(void)751 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_UFC(void)
752 {
753   return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_2) == SBS_FPUIMR_FPU_IE_2) ? 1UL : 0UL);
754 }
755 
756 /**
757   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
758   * @rmtoll SBS_FPUIMR FPU_IE_3      LL_SBS_IsEnabledIT_FPU_OFC
759   * @retval State of bit (1 or 0).
760   */
LL_SBS_IsEnabledIT_FPU_OFC(void)761 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_OFC(void)
762 {
763   return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_3) == SBS_FPUIMR_FPU_IE_3) ? 1UL : 0UL);
764 }
765 
766 /**
767   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
768   * @rmtoll SBS_FPUIMR FPU_IE_4      LL_SBS_IsEnabledIT_FPU_IDC
769   * @retval State of bit (1 or 0).
770   */
LL_SBS_IsEnabledIT_FPU_IDC(void)771 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IDC(void)
772 {
773   return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_4) == SBS_FPUIMR_FPU_IE_4) ? 1UL : 0UL);
774 }
775 
776 /**
777   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
778   * @rmtoll SBS_FPUIMR FPU_IE_5      LL_SBS_IsEnabledIT_FPU_IXC
779   * @retval State of bit (1 or 0).
780   */
LL_SBS_IsEnabledIT_FPU_IXC(void)781 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIT_FPU_IXC(void)
782 {
783   return ((READ_BIT(SBS->FPUIMR, SBS_FPUIMR_FPU_IE_5) == SBS_FPUIMR_FPU_IE_5) ? 1UL : 0UL);
784 }
785 
786 /**
787   * @brief  Check if the automatic erase of BKPRAM and PKARAM memories are done
788   * @rmtoll SBS_MESR MEF     LL_SBS_IsDoneMemoryErase
789   * @retval State of bit (1 or 0).
790   */
LL_SBS_IsDoneMemoryErase(void)791 __STATIC_INLINE uint32_t LL_SBS_IsDoneMemoryErase(void)
792 {
793   return (READ_BIT(SBS->MESR, SBS_MESR_MEF));
794 }
795 
796 /**
797   * @brief  Enable the XSPI2 speed optimization
798   * @rmtoll SBS_CCCSR XSPI2_IOHSLV     LL_SBS_EnableXSPI2SpeedOptim
799   * @retval None
800   */
LL_SBS_EnableXSPI2SpeedOptim(void)801 __STATIC_INLINE void LL_SBS_EnableXSPI2SpeedOptim(void)
802 {
803   SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_IOHSLV);
804 }
805 
806 /**
807   * @brief  Disable the XSPI2 speed optimization
808   * @rmtoll SBS_CCCSR XSPI2_IOHSLV     LL_SBS_DisableXSPI2SpeedOptim
809   * @retval None
810   */
LL_SBS_DisableXSPI2SpeedOptim(void)811 __STATIC_INLINE void LL_SBS_DisableXSPI2SpeedOptim(void)
812 {
813   CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_IOHSLV);
814 }
815 
816 /**
817   * @brief  Check if the XSPI2 speed optimization is enabled
818   * @rmtoll SBS_CCCSR XSPI2_IOHSLV     LL_SBS_IsEnabledXSPI2SpeedOptim
819   * @retval State of bit (1 or 0).
820   */
LL_SBS_IsEnabledXSPI2SpeedOptim(void)821 __STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI2SpeedOptim(void)
822 {
823   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_IOHSLV) != 0UL) ? 1UL : 0UL);
824 }
825 
826 /**
827   * @brief  Enable the XSPI1 speed optimization
828   * @rmtoll SBS_CCCSR XSPI1_IOHSLV     LL_SBS_EnableXSPI1SpeedOptim
829   * @retval None
830   */
LL_SBS_EnableXSPI1SpeedOptim(void)831 __STATIC_INLINE void LL_SBS_EnableXSPI1SpeedOptim(void)
832 {
833   SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_IOHSLV);
834 }
835 
836 /**
837   * @brief  Disable the XSPI1 speed optimization
838   * @rmtoll SBS_CCCSR XSPI1_IOHSLV     LL_SBS_DisableXSPI1SpeedOptim
839   * @retval None
840   */
LL_SBS_DisableXSPI1SpeedOptim(void)841 __STATIC_INLINE void LL_SBS_DisableXSPI1SpeedOptim(void)
842 {
843   CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_IOHSLV);
844 }
845 
846 /**
847   * @brief  Check if the XSPI1 speed optimization is enabled
848   * @rmtoll SBS_CCCSR XSPI1_IOHSLV     LL_SBS_IsEnabledXSPI1SpeedOptim
849   * @retval State of bit (1 or 0).
850   */
LL_SBS_IsEnabledXSPI1SpeedOptim(void)851 __STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI1SpeedOptim(void)
852 {
853   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_IOHSLV) != 0UL) ? 1UL : 0UL);
854 }
855 
856 /**
857   * @brief  Enable the I/O speed optimization
858   * @rmtoll SBS_CCCSR IOHSLV     LL_SBS_EnableIOSpeedOptim
859   * @retval None
860   */
LL_SBS_EnableIOSpeedOptim(void)861 __STATIC_INLINE void LL_SBS_EnableIOSpeedOptim(void)
862 {
863   SET_BIT(SBS->CCCSR, SBS_CCCSR_IOHSLV);
864 }
865 
866 /**
867   * @brief  Disable the I/O speed optimization
868   * @rmtoll SBS_CCCSR IOHSLV     LL_SBS_DisableIOSpeedOptim
869   * @retval None
870   */
LL_SBS_DisableIOSpeedOptim(void)871 __STATIC_INLINE void LL_SBS_DisableIOSpeedOptim(void)
872 {
873   CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_IOHSLV);
874 }
875 
876 /**
877   * @brief  Check if the I/O speed optimization is enabled
878   * @rmtoll SBS_CCCSR IOHSLV     LL_SBS_IsEnabledIOSpeedOptim
879   * @retval State of bit (1 or 0).
880   */
LL_SBS_IsEnabledIOSpeedOptim(void)881 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIOSpeedOptim(void)
882 {
883   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_IOHSLV) != 0UL) ? 1UL : 0UL);
884 }
885 
886 /**
887   * @brief  Check if the XSPI2 compensation cell is ready
888   * @rmtoll SBS_CCCSR XSPI2_COMP_RDY     LL_SBS_IsReadyXSPI2CompCell
889   * @retval State of bit (1 or 0).
890   */
LL_SBS_IsReadyXSPI2CompCell(void)891 __STATIC_INLINE uint32_t LL_SBS_IsReadyXSPI2CompCell(void)
892 {
893   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_RDY) != 0UL) ? 1UL : 0UL);
894 }
895 
896 /**
897   * @brief  Check if the XSPI1 compensation cell is ready
898   * @rmtoll SBS_CCCSR XSPI1_COMP_RDY     LL_SBS_IsReadyXSPI1CompCell
899   * @retval State of bit (1 or 0).
900   */
LL_SBS_IsReadyXSPI1CompCell(void)901 __STATIC_INLINE uint32_t LL_SBS_IsReadyXSPI1CompCell(void)
902 {
903   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_RDY) != 0UL) ? 1UL : 0UL);
904 }
905 
906 /**
907   * @brief  Check if the I/O compensation cell is ready
908   * @rmtoll SBS_CCCSR COMP_RDY     LL_SBS_IsReadyIOCompCell
909   * @retval State of bit (1 or 0).
910   */
LL_SBS_IsReadyIOCompCell(void)911 __STATIC_INLINE uint32_t LL_SBS_IsReadyIOCompCell(void)
912 {
913   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_COMP_RDY) != 0UL) ? 1UL : 0UL);
914 }
915 
916 /**
917   * @brief  Configure the code for the XSPI2 compensation cell
918   * @rmtoll SBS_CCCSR XSPI2_COMP_CODESEL     LL_SBS_SetXSPI2CompCellCode
919   * @param  Code This parameter can be one of the following values:
920   *         @arg @ref LL_SBS_XSPI2_CODE_CELL
921   *         @arg @ref LL_SBS_XSPI2_CODE_REG
922   * @retval None
923   */
LL_SBS_SetXSPI2CompCellCode(uint32_t Code)924 __STATIC_INLINE void LL_SBS_SetXSPI2CompCellCode(uint32_t Code)
925 {
926   MODIFY_REG(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_CODESEL, Code);
927 }
928 
929 /**
930   * @brief  Get the selected code for the XSPI2 compensation cell
931   * @rmtoll SBS_CCCSR XSPI2_COMP_CODESEL     LL_SBS_GetXSPI2CompCellCode
932   * @retval Returned value is the selected code for the XSPI2 compensation cell:
933   *         @arg @ref LL_SBS_XSPI2_CODE_CELL
934   *         @arg @ref LL_SBS_XSPI2_CODE_REG
935   */
LL_SBS_GetXSPI2CompCellCode(void)936 __STATIC_INLINE uint32_t LL_SBS_GetXSPI2CompCellCode(void)
937 {
938   return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_CODESEL));
939 }
940 
941 /**
942   * @brief  Enable the XSPI2 compensation cell
943   * @rmtoll SBS_PMCR XSPI2_COMP_EN     LL_SBS_EnableXSPI2CompCell
944   * @retval None
945   */
LL_SBS_EnableXSPI2CompCell(void)946 __STATIC_INLINE void LL_SBS_EnableXSPI2CompCell(void)
947 {
948   SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_EN);
949 }
950 
951 /**
952   * @brief  Disable the XSPI2 compensation cell
953   * @rmtoll SBS_CCCSR XSPI2_COMP_EN     LL_SBS_DisableXSPI2CompCell
954   * @retval None
955   */
LL_SBS_DisableXSPI2CompCell(void)956 __STATIC_INLINE void LL_SBS_DisableXSPI2CompCell(void)
957 {
958   CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_EN);
959 }
960 
961 /**
962   * @brief  Check if the XSPI2 compensation cell is enabled
963   * @rmtoll SBS_CCCSR XSPI2_COMP_EN     LL_SBS_IsEnabledXSPI2CompCell
964   * @retval State of bit (1 or 0).
965   */
LL_SBS_IsEnabledXSPI2CompCell(void)966 __STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI2CompCell(void)
967 {
968   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI2_COMP_EN) != 0UL) ? 1UL : 0UL);
969 }
970 
971 /**
972   * @brief  Configure the code for the XSPI1 compensation cell
973   * @rmtoll SBS_CCCSR XSPI1_COMP_CODESEL     LL_SBS_SetXSPI1CompCellCode
974   * @param  Code This parameter can be one of the following values:
975   *         @arg @ref LL_SBS_XSPI1_CODE_CELL
976   *         @arg @ref LL_SBS_XSPI1_CODE_REG
977   * @retval None
978   */
LL_SBS_SetXSPI1CompCellCode(uint32_t Code)979 __STATIC_INLINE void LL_SBS_SetXSPI1CompCellCode(uint32_t Code)
980 {
981   MODIFY_REG(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_CODESEL, Code);
982 }
983 
984 /**
985   * @brief  Get the selected code for the XSPI2 compensation cell
986   * @rmtoll SBS_CCCSR XSPI1_COMP_CODESEL     LL_SBS_GetXSPI1CompCellCode
987   * @retval Returned value is the selected code for the XSPI1 compensation cell:
988   *         @arg @ref LL_SBS_XSPI1_CODE_CELL
989   *         @arg @ref LL_SBS_XSPI1_CODE_REG
990   */
LL_SBS_GetXSPI1CompCellCode(void)991 __STATIC_INLINE uint32_t LL_SBS_GetXSPI1CompCellCode(void)
992 {
993   return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_CODESEL));
994 }
995 
996 /**
997   * @brief  Enable the XSPI1 compensation cell
998   * @rmtoll SBS_PMCR XSPI1_COMP_EN     LL_SBS_EnableXSPI1CompCell
999   * @retval None
1000   */
LL_SBS_EnableXSPI1CompCell(void)1001 __STATIC_INLINE void LL_SBS_EnableXSPI1CompCell(void)
1002 {
1003   SET_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_EN);
1004 }
1005 
1006 /**
1007   * @brief  Disable the XSPI1 compensation cell
1008   * @rmtoll SBS_CCCSR XSPI1_COMP_EN     LL_SBS_DisableXSPI1CompCell
1009   * @retval None
1010   */
LL_SBS_DisableXSPI1CompCell(void)1011 __STATIC_INLINE void LL_SBS_DisableXSPI1CompCell(void)
1012 {
1013   CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_EN);
1014 }
1015 
1016 /**
1017   * @brief  Check if the XSPI1 compensation cell is enabled
1018   * @rmtoll SBS_CCCSR XSPI1_COMP_EN     LL_SBS_IsEnabledXSPI1CompCell
1019   * @retval State of bit (1 or 0).
1020   */
LL_SBS_IsEnabledXSPI1CompCell(void)1021 __STATIC_INLINE uint32_t LL_SBS_IsEnabledXSPI1CompCell(void)
1022 {
1023   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_XSPI1_COMP_EN) != 0UL) ? 1UL : 0UL);
1024 }
1025 
1026 /**
1027   * @brief  Configure the code for the I/O compensation cell
1028   * @rmtoll SBS_CCCSR COMP_CODESEL     LL_SBS_SetIOCompCellCode
1029   * @param  Code This parameter can be one of the following values:
1030   *         @arg @ref LL_SBS_IO_CODE_CELL
1031   *         @arg @ref LL_SBS_IO_CODE_REG
1032   * @retval None
1033   */
LL_SBS_SetIOCompCellCode(uint32_t Code)1034 __STATIC_INLINE void LL_SBS_SetIOCompCellCode(uint32_t Code)
1035 {
1036   MODIFY_REG(SBS->CCCSR, SBS_CCCSR_COMP_CODESEL, Code);
1037 }
1038 
1039 /**
1040   * @brief  Get the selected code for the I/O compensation cell
1041   * @rmtoll SBS_CCCSR COMP_CODESEL     LL_SBS_GetIOCompCellCode
1042   * @retval Returned value is the selected code for the I/O compensation cell:
1043   *         @arg @ref LL_SBS_IO_CODE_CELL
1044   *         @arg @ref LL_SBS_IO_CODE_REG
1045   */
LL_SBS_GetIOCompCellCode(void)1046 __STATIC_INLINE uint32_t LL_SBS_GetIOCompCellCode(void)
1047 {
1048   return (uint32_t)(READ_BIT(SBS->CCCSR, SBS_CCCSR_COMP_CODESEL));
1049 }
1050 
1051 /**
1052   * @brief  Enable the I/O compensation cell
1053   * @rmtoll SBS_PMCR COMP_EN     LL_SBS_EnableIOCompCell
1054   * @retval None
1055   */
LL_SBS_EnableIOCompCell(void)1056 __STATIC_INLINE void LL_SBS_EnableIOCompCell(void)
1057 {
1058   SET_BIT(SBS->CCCSR, SBS_CCCSR_COMP_EN);
1059 }
1060 
1061 /**
1062   * @brief  Disable the I/O compensation cell
1063   * @rmtoll SBS_CCCSR COMP_EN     LL_SBS_DisableIOCompCell
1064   * @retval None
1065   */
LL_SBS_DisableIOCompCell(void)1066 __STATIC_INLINE void LL_SBS_DisableIOCompCell(void)
1067 {
1068   CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_COMP_EN);
1069 }
1070 
1071 /**
1072   * @brief  Check if the I/O compensation cell is enabled
1073   * @rmtoll SBS_CCCSR COMP_EN     LL_SBS_IsEnabledIOCompCell
1074   * @retval State of bit (1 or 0).
1075   */
LL_SBS_IsEnabledIOCompCell(void)1076 __STATIC_INLINE uint32_t LL_SBS_IsEnabledIOCompCell(void)
1077 {
1078   return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_COMP_EN) != 0UL) ? 1UL : 0UL);
1079 }
1080 
1081 /**
1082   * @brief  Get the XSPI2 PMOS compensation
1083   * @rmtoll SBS_CCVALR XSPI2_PSRC     LL_SBS_GetXSPI2PmosComp
1084   * @retval Returned value is the slew-rate compensation for XSPI2 PMOS transistors (value between 0 and 0xF)
1085   */
LL_SBS_GetXSPI2PmosComp(void)1086 __STATIC_INLINE uint32_t LL_SBS_GetXSPI2PmosComp(void)
1087 {
1088   return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI2_PSRC)) >> SBS_CCVALR_XSPI2_PSRC_Pos);
1089 }
1090 
1091 /**
1092   * @brief  Get the XSPI2 NMOS compensation
1093   * @rmtoll SBS_CCVALR XSPI2_NSRC     LL_SBS_GetXSPI2NmosComp
1094   * @retval Returned value is the slew-rate compensation for XSPI2 NMOS transistors (value between 0 and 0xF)
1095   */
LL_SBS_GetXSPI2NmosComp(void)1096 __STATIC_INLINE uint32_t LL_SBS_GetXSPI2NmosComp(void)
1097 {
1098   return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI2_NSRC)) >> SBS_CCVALR_XSPI2_NSRC_Pos);
1099 }
1100 
1101 /**
1102   * @brief  Get the XSPI1 PMOS compensation
1103   * @rmtoll SBS_CCVALR XSPI1_PSRC     LL_SBS_GetXSPI1PmosComp
1104   * @retval Returned value is the slew-rate compensation for XSPI1 PMOS transistors (value between 0 and 0xF)
1105   */
LL_SBS_GetXSPI1PmosComp(void)1106 __STATIC_INLINE uint32_t LL_SBS_GetXSPI1PmosComp(void)
1107 {
1108   return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI1_PSRC)) >> SBS_CCVALR_XSPI1_PSRC_Pos);
1109 }
1110 
1111 /**
1112   * @brief  Get the XSPI NMOS compensation
1113   * @rmtoll SBS_CCVALR XSPI1_NSRC     LL_SBS_GetXSPI1NmosComp
1114   * @retval Returned value is the slew-rate compensation for XSPI1 NMOS transistors (value between 0 and 0xF)
1115   */
LL_SBS_GetXSPI1NmosComp(void)1116 __STATIC_INLINE uint32_t LL_SBS_GetXSPI1NmosComp(void)
1117 {
1118   return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_XSPI1_NSRC)) >> SBS_CCVALR_XSPI1_NSRC_Pos);
1119 }
1120 
1121 /**
1122   * @brief  Get the I/O PMOS compensation
1123   * @rmtoll SBS_CCVALR PSRC     LL_SBS_GetIOPmosComp
1124   * @retval Returned value is the slew-rate compensation for I/O PMOS transistors (value between 0 and 0xF)
1125   */
LL_SBS_GetIOPmosComp(void)1126 __STATIC_INLINE uint32_t LL_SBS_GetIOPmosComp(void)
1127 {
1128   return (uint32_t)((READ_BIT(SBS->CCVALR, SBS_CCVALR_PSRC)) >> SBS_CCVALR_PSRC_Pos);
1129 }
1130 
1131 /**
1132   * @brief  Get the I/O NMOS compensation
1133   * @rmtoll SBS_CCVALR NSRC     LL_SBS_GetIONmosComp
1134   * @retval Returned value is the slew-rate compensation for I/O NMOS transistors (value between 0 and 0xF)
1135   */
LL_SBS_GetIONmosComp(void)1136 __STATIC_INLINE uint32_t LL_SBS_GetIONmosComp(void)
1137 {
1138   return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_NSRC));
1139 }
1140 
1141 /**
1142   * @brief  Set the XSPI2 software PMOS compensation
1143   * @rmtoll SBS_CCSWVALR XSPI2_SW_PSRC     LL_SBS_SetXSPI2SwPmosComp
1144   * @param  Compensation This parameter can have a value between 0 and 0xF
1145   * @retval None
1146   */
LL_SBS_SetXSPI2SwPmosComp(uint32_t Compensation)1147 __STATIC_INLINE void LL_SBS_SetXSPI2SwPmosComp(uint32_t Compensation)
1148 {
1149   MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_PSRC, (Compensation << SBS_CCSWVALR_XSPI2_SW_PSRC_Pos));
1150 }
1151 
1152 /**
1153   * @brief  Get the XSPI2 PMOS compensation
1154   * @rmtoll SBS_CCSWVALR XSPI2_SW_PSRC     LL_SBS_GetXSPI2SwPmosComp
1155   * @retval Returned value is the slew-rate compensation for XSPI2 PMOS transistors (value between 0 and 0xF)
1156   */
LL_SBS_GetXSPI2SwPmosComp(void)1157 __STATIC_INLINE uint32_t LL_SBS_GetXSPI2SwPmosComp(void)
1158 {
1159   return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_PSRC)) >> SBS_CCSWVALR_XSPI2_SW_PSRC_Pos);
1160 }
1161 
1162 /**
1163   * @brief  Set the XSPI2 software NMOS compensation
1164   * @rmtoll SBS_CCSWVALR XSPI2_SW_NSRC     LL_SBS_SetXSPI2SwNmosComp
1165   * @param  Compensation This parameter can have a value between 0 and 0xF
1166   * @retval None
1167   */
LL_SBS_SetXSPI2SwNmosComp(uint32_t Compensation)1168 __STATIC_INLINE void LL_SBS_SetXSPI2SwNmosComp(uint32_t Compensation)
1169 {
1170   MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_NSRC, (Compensation << SBS_CCSWVALR_XSPI2_SW_NSRC_Pos));
1171 }
1172 
1173 /**
1174   * @brief  Get the XSPI2 software NMOS compensation
1175   * @rmtoll SBS_CCSWVALR XSPI2_SW_NSRC     LL_SBS_GetXSPI2SwNmosComp
1176   * @retval Returned value is the slew-rate compensation for XSPI2 NMOS transistors (value between 0 and 0xF)
1177   */
LL_SBS_GetXSPI2SwNmosComp(void)1178 __STATIC_INLINE uint32_t LL_SBS_GetXSPI2SwNmosComp(void)
1179 {
1180   return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI2_SW_NSRC)) >> SBS_CCSWVALR_XSPI2_SW_NSRC_Pos);
1181 }
1182 
1183 /**
1184   * @brief  Set the XSPI1 software PMOS compensation
1185   * @rmtoll SBS_CCSWVALR XSPI2_SW_PSRC     LL_SBS_SetXSPI1SwPmosComp
1186   * @param  Compensation This parameter can have a value between 0 and 0xF
1187   * @retval None
1188   */
LL_SBS_SetXSPI1SwPmosComp(uint32_t Compensation)1189 __STATIC_INLINE void LL_SBS_SetXSPI1SwPmosComp(uint32_t Compensation)
1190 {
1191   MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_PSRC, (Compensation << SBS_CCSWVALR_XSPI1_SW_PSRC_Pos));
1192 }
1193 
1194 /**
1195   * @brief  Get the XSPI1 PMOS compensation
1196   * @rmtoll SBS_CCSWVALR XSPI1_SW_PSRC     LL_SBS_GetXSPI1SwPmosComp
1197   * @retval Returned value is the slew-rate compensation for XSPI1 PMOS transistors (value between 0 and 0xF)
1198   */
LL_SBS_GetXSPI1SwPmosComp(void)1199 __STATIC_INLINE uint32_t LL_SBS_GetXSPI1SwPmosComp(void)
1200 {
1201   return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_PSRC)) >> SBS_CCSWVALR_XSPI1_SW_PSRC_Pos);
1202 }
1203 
1204 /**
1205   * @brief  Set the XSPI1 software NMOS compensation
1206   * @rmtoll SBS_CCSWVALR XSPI1_SW_NSRC     LL_SBS_SetXSPI1SwNmosComp
1207   * @param  Compensation This parameter can have a value between 0 and 0xF
1208   * @retval None
1209   */
LL_SBS_SetXSPI1SwNmosComp(uint32_t Compensation)1210 __STATIC_INLINE void LL_SBS_SetXSPI1SwNmosComp(uint32_t Compensation)
1211 {
1212   MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_NSRC, (Compensation << SBS_CCSWVALR_XSPI1_SW_NSRC_Pos));
1213 }
1214 
1215 /**
1216   * @brief  Get the XSPI1 software NMOS compensation
1217   * @rmtoll SBS_CCSWVALR XSPI1_SW_NSRC     LL_SBS_GetXSPI1SwNmosComp
1218   * @retval Returned value is the slew-rate compensation for XSPI1 NMOS transistors (value between 0 and 0xF)
1219   */
LL_SBS_GetXSPI1SwNmosComp(void)1220 __STATIC_INLINE uint32_t LL_SBS_GetXSPI1SwNmosComp(void)
1221 {
1222   return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_XSPI1_SW_NSRC)) >> SBS_CCSWVALR_XSPI1_SW_NSRC_Pos);
1223 }
1224 
1225 /**
1226   * @brief  Set the I/O software PMOS compensation
1227   * @rmtoll SBS_CCSWVALR SW_PSRC     LL_SBS_SetIOSwPmosComp
1228   * @param  Compensation This parameter can have a value between 0 and 0xF
1229   * @retval None
1230   */
LL_SBS_SetIOSwPmosComp(uint32_t Compensation)1231 __STATIC_INLINE void LL_SBS_SetIOSwPmosComp(uint32_t Compensation)
1232 {
1233   MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_SW_PSRC, (Compensation << SBS_CCSWVALR_SW_PSRC_Pos));
1234 }
1235 
1236 /**
1237   * @brief  Get the I/O PMOS compensation
1238   * @rmtoll SBS_CCSWVALR SW_PSRC     LL_SBS_GetIOSwPmosComp
1239   * @retval Returned value is the slew-rate compensation for I/O PMOS transistors (value between 0 and 0xF)
1240   */
LL_SBS_GetIOSwPmosComp(void)1241 __STATIC_INLINE uint32_t LL_SBS_GetIOSwPmosComp(void)
1242 {
1243   return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_SW_PSRC)) >> SBS_CCSWVALR_SW_PSRC_Pos);
1244 }
1245 
1246 /**
1247   * @brief  Set the I/O software NMOS compensation
1248   * @rmtoll SBS_CCSWVALR SW_NSRC     LL_SBS_SetIOSwNmosComp
1249   * @param  Compensation This parameter can have a value between 0 and 0xF
1250   * @retval None
1251   */
LL_SBS_SetIOSwNmosComp(uint32_t Compensation)1252 __STATIC_INLINE void LL_SBS_SetIOSwNmosComp(uint32_t Compensation)
1253 {
1254   MODIFY_REG(SBS->CCSWVALR, SBS_CCSWVALR_SW_NSRC, (Compensation << SBS_CCSWVALR_SW_NSRC_Pos));
1255 }
1256 
1257 /**
1258   * @brief  Get the I/O software NMOS compensation
1259   * @rmtoll SBS_CCSWVALR SW_NSRC     LL_SBS_GetIOSwNmosComp
1260   * @retval Returned value is the slew-rate compensation for I/O NMOS transistors (value between 0 and 0xF)
1261   */
LL_SBS_GetIOSwNmosComp(void)1262 __STATIC_INLINE uint32_t LL_SBS_GetIOSwNmosComp(void)
1263 {
1264   return (uint32_t)((READ_BIT(SBS->CCSWVALR, SBS_CCSWVALR_SW_NSRC)) >> SBS_CCSWVALR_SW_NSRC_Pos);
1265 }
1266 
1267 /**
1268   * @brief  Set connections to TIM1/15/16/17 Break inputs
1269   * @rmtoll SBS_BKLOCKR PVD_BL          LL_SBS_SetTIMBreakInputs\n
1270   *         SBS_BKLOCKR FLASHECC_BL     LL_SBS_SetTIMBreakInputs\n
1271   *         SBS_BKLOCKR CM7LCKUP_BL     LL_SBS_SetTIMBreakInputs\n
1272   *         SBS_BKLOCKR BKRAMECC_BL     LL_SBS_SetTIMBreakInputs\n
1273   *         SBS_BKLOCKR DTCMECC_BL      LL_SBS_SetTIMBreakInputs\n
1274   *         SBS_BKLOCKR ITCMECC_BL      LL_SBS_SetTIMBreakInputs\n
1275   *         SBS_BKLOCKR ARAM3ECC_BL     LL_SBS_SetTIMBreakInputs\n
1276   *         SBS_BKLOCKR ARAM1ECC_BL     LL_SBS_SetTIMBreakInputs
1277   * @param  Break This parameter can be a combination of the following values:
1278   *         @arg @ref LL_SBS_TIMBREAK_PVD
1279   *         @arg @ref LL_SBS_TIMBREAK_FLASHECC
1280   *         @arg @ref LL_SBS_TIMBREAK_CM7LCKUP
1281   *         @arg @ref LL_SBS_TIMBREAK_BKRAMECC
1282   *         @arg @ref LL_SBS_TIMBREAK_DTCMECC
1283   *         @arg @ref LL_SBS_TIMBREAK_ITCMECC
1284   *         @arg @ref LL_SBS_TIMBREAK_ARAM3ECC
1285   *         @arg @ref LL_SBS_TIMBREAK_ARAM1ECC
1286   * @retval None
1287   */
LL_SBS_SetTIMBreakInputs(uint32_t Break)1288 __STATIC_INLINE void LL_SBS_SetTIMBreakInputs(uint32_t Break)
1289 {
1290   MODIFY_REG(SBS->BKLOCKR,
1291              (SBS_BKLOCKR_PVD_BL | SBS_BKLOCKR_FLASHECC_BL | SBS_BKLOCKR_CM7LCKUP_BL | SBS_BKLOCKR_BKRAMECC_BL | \
1292               SBS_BKLOCKR_DTCMECC_BL | SBS_BKLOCKR_ITCMECC_BL | SBS_BKLOCKR_ARAM3ECC_BL | SBS_BKLOCKR_ARAM1ECC_BL)
1293              , Break);
1294 }
1295 
1296 /**
1297   * @brief  Get connections to TIM1/15/16/17 Break inputs
1298   * @rmtoll SBS_BKLOCKR CLL           LL_SBS_GetTIMBreakInputs\n
1299   *         SBS_BKLOCKR SPL           LL_SBS_GetTIMBreakInputs\n
1300   *         SBS_BKLOCKR PVDL          LL_SBS_GetTIMBreakInputs\n
1301   *         SBS_BKLOCKR ECCL          LL_SBS_GetTIMBreakInputs
1302   * @retval Returned value can be can be a combination of the following values:
1303   *         @arg @ref LL_SBS_TIMBREAK_PVD
1304   *         @arg @ref LL_SBS_TIMBREAK_FLASHECC
1305   *         @arg @ref LL_SBS_TIMBREAK_CM7LCKUP
1306   *         @arg @ref LL_SBS_TIMBREAK_BKRAMECC
1307   *         @arg @ref LL_SBS_TIMBREAK_DTCMECC
1308   *         @arg @ref LL_SBS_TIMBREAK_ITCMECC
1309   *         @arg @ref LL_SBS_TIMBREAK_ARAM3ECC
1310   *         @arg @ref LL_SBS_TIMBREAK_ARAM1ECC
1311   */
LL_SBS_GetTIMBreakInputs(void)1312 __STATIC_INLINE uint32_t LL_SBS_GetTIMBreakInputs(void)
1313 {
1314   return (uint32_t)(READ_BIT(SBS->BKLOCKR,
1315                              (SBS_BKLOCKR_PVD_BL | SBS_BKLOCKR_FLASHECC_BL | SBS_BKLOCKR_CM7LCKUP_BL | \
1316                               SBS_BKLOCKR_BKRAMECC_BL | SBS_BKLOCKR_DTCMECC_BL | SBS_BKLOCKR_ITCMECC_BL | \
1317                               SBS_BKLOCKR_ARAM3ECC_BL | SBS_BKLOCKR_ARAM1ECC_BL)));
1318 }
1319 
1320 /**
1321   * @brief  Configure source input for the EXTI external interrupt.
1322   * @rmtoll SBS_EXTICR1 EXTI0         LL_SBS_SetEXTISource\n
1323   *         SBS_EXTICR1 EXTI1         LL_SBS_SetEXTISource\n
1324   *         SBS_EXTICR1 EXTI2         LL_SBS_SetEXTISource\n
1325   *         SBS_EXTICR1 EXTI3         LL_SBS_SetEXTISource\n
1326   *         SBS_EXTICR2 EXTI4         LL_SBS_SetEXTISource\n
1327   *         SBS_EXTICR2 EXTI5         LL_SBS_SetEXTISource\n
1328   *         SBS_EXTICR2 EXTI6         LL_SBS_SetEXTISource\n
1329   *         SBS_EXTICR2 EXTI7         LL_SBS_SetEXTISource\n
1330   *         SBS_EXTICR3 EXTI8         LL_SBS_SetEXTISource\n
1331   *         SBS_EXTICR3 EXTI9         LL_SBS_SetEXTISource\n
1332   *         SBS_EXTICR3 EXTI10        LL_SBS_SetEXTISource\n
1333   *         SBS_EXTICR3 EXTI11        LL_SBS_SetEXTISource\n
1334   *         SBS_EXTICR4 EXTI12        LL_SBS_SetEXTISource\n
1335   *         SBS_EXTICR4 EXTI13        LL_SBS_SetEXTISource\n
1336   *         SBS_EXTICR4 EXTI14        LL_SBS_SetEXTISource\n
1337   *         SBS_EXTICR4 EXTI15        LL_SBS_SetEXTISource
1338   * @param  Port This parameter can be one of the following values:
1339   *         @arg @ref LL_SBS_EXTI_PORTA
1340   *         @arg @ref LL_SBS_EXTI_PORTB
1341   *         @arg @ref LL_SBS_EXTI_PORTC
1342   *         @arg @ref LL_SBS_EXTI_PORTD
1343   *         @arg @ref LL_SBS_EXTI_PORTE
1344   *         @arg @ref LL_SBS_EXTI_PORTF
1345   *         @arg @ref LL_SBS_EXTI_PORTG
1346   *         @arg @ref LL_SBS_EXTI_PORTH
1347   *         @arg @ref LL_SBS_EXTI_PORTM
1348   *         @arg @ref LL_SBS_EXTI_PORTN
1349   *         @arg @ref LL_SBS_EXTI_PORTO
1350   *         @arg @ref LL_SBS_EXTI_PORTP
1351   *
1352   *         (*) value not defined in all devices
1353   * @param  Line This parameter can be one of the following values:
1354   *         @arg @ref LL_SBS_EXTI_LINE0
1355   *         @arg @ref LL_SBS_EXTI_LINE1
1356   *         @arg @ref LL_SBS_EXTI_LINE2
1357   *         @arg @ref LL_SBS_EXTI_LINE3
1358   *         @arg @ref LL_SBS_EXTI_LINE4
1359   *         @arg @ref LL_SBS_EXTI_LINE5
1360   *         @arg @ref LL_SBS_EXTI_LINE6
1361   *         @arg @ref LL_SBS_EXTI_LINE7
1362   *         @arg @ref LL_SBS_EXTI_LINE8
1363   *         @arg @ref LL_SBS_EXTI_LINE9
1364   *         @arg @ref LL_SBS_EXTI_LINE10
1365   *         @arg @ref LL_SBS_EXTI_LINE11
1366   *         @arg @ref LL_SBS_EXTI_LINE12
1367   *         @arg @ref LL_SBS_EXTI_LINE13
1368   *         @arg @ref LL_SBS_EXTI_LINE14
1369   *         @arg @ref LL_SBS_EXTI_LINE15
1370   * @retval None
1371   */
LL_SBS_SetEXTISource(uint32_t Port,uint32_t Line)1372 __STATIC_INLINE void LL_SBS_SetEXTISource(uint32_t Port, uint32_t Line)
1373 {
1374   MODIFY_REG(SBS->EXTICR[Line & 0x03U],
1375              SBS_EXTICR1_PC_EXTI0 << (Line >> LL_SBS_REGISTER_PINPOS_SHFT),
1376              Port << (Line >> LL_SBS_REGISTER_PINPOS_SHFT));
1377 }
1378 
1379 /**
1380   * @brief  Get the configured defined for specific EXTI Line
1381   * @rmtoll SBS_EXTICR1 EXTI0         LL_SBS_GetEXTISource\n
1382   *         SBS_EXTICR1 EXTI1         LL_SBS_GetEXTISource\n
1383   *         SBS_EXTICR1 EXTI2         LL_SBS_GetEXTISource\n
1384   *         SBS_EXTICR1 EXTI3         LL_SBS_GetEXTISource\n
1385   *         SBS_EXTICR2 EXTI4         LL_SBS_GetEXTISource\n
1386   *         SBS_EXTICR2 EXTI5         LL_SBS_GetEXTISource\n
1387   *         SBS_EXTICR2 EXTI6         LL_SBS_GetEXTISource\n
1388   *         SBS_EXTICR2 EXTI7         LL_SBS_GetEXTISource\n
1389   *         SBS_EXTICR3 EXTI8         LL_SBS_GetEXTISource\n
1390   *         SBS_EXTICR3 EXTI9         LL_SBS_GetEXTISource\n
1391   *         SBS_EXTICR3 EXTI10        LL_SBS_GetEXTISource\n
1392   *         SBS_EXTICR3 EXTI11        LL_SBS_GetEXTISource\n
1393   *         SBS_EXTICR4 EXTI12        LL_SBS_GetEXTISource\n
1394   *         SBS_EXTICR4 EXTI13        LL_SBS_GetEXTISource\n
1395   *         SBS_EXTICR4 EXTI14        LL_SBS_GetEXTISource\n
1396   *         SBS_EXTICR4 EXTI15        LL_SBS_GetEXTISource
1397   * @param  Line This parameter can be one of the following values:
1398   *         @arg @ref LL_SBS_EXTI_LINE0
1399   *         @arg @ref LL_SBS_EXTI_LINE1
1400   *         @arg @ref LL_SBS_EXTI_LINE2
1401   *         @arg @ref LL_SBS_EXTI_LINE3
1402   *         @arg @ref LL_SBS_EXTI_LINE4
1403   *         @arg @ref LL_SBS_EXTI_LINE5
1404   *         @arg @ref LL_SBS_EXTI_LINE6
1405   *         @arg @ref LL_SBS_EXTI_LINE7
1406   *         @arg @ref LL_SBS_EXTI_LINE8
1407   *         @arg @ref LL_SBS_EXTI_LINE9
1408   *         @arg @ref LL_SBS_EXTI_LINE10
1409   *         @arg @ref LL_SBS_EXTI_LINE11
1410   *         @arg @ref LL_SBS_EXTI_LINE12
1411   *         @arg @ref LL_SBS_EXTI_LINE13
1412   *         @arg @ref LL_SBS_EXTI_LINE14
1413   *         @arg @ref LL_SBS_EXTI_LINE15
1414   * @retval Returned value can be one of the following values:
1415   *         @arg @ref LL_SBS_EXTI_PORTA
1416   *         @arg @ref LL_SBS_EXTI_PORTB
1417   *         @arg @ref LL_SBS_EXTI_PORTC
1418   *         @arg @ref LL_SBS_EXTI_PORTD
1419   *         @arg @ref LL_SBS_EXTI_PORTE
1420   *         @arg @ref LL_SBS_EXTI_PORTF
1421   *         @arg @ref LL_SBS_EXTI_PORTG
1422   *         @arg @ref LL_SBS_EXTI_PORTH
1423   *         @arg @ref LL_SBS_EXTI_PORTM
1424   *         @arg @ref LL_SBS_EXTI_PORTN
1425   *         @arg @ref LL_SBS_EXTI_PORTO
1426   *         @arg @ref LL_SBS_EXTI_PORTP
1427   */
LL_SBS_GetEXTISource(uint32_t Line)1428 __STATIC_INLINE uint32_t LL_SBS_GetEXTISource(uint32_t Line)
1429 {
1430   return (uint32_t)(READ_BIT(SBS->EXTICR[Line & 0x03U],
1431                              (SBS_EXTICR1_PC_EXTI0 << (Line >> LL_SBS_REGISTER_PINPOS_SHFT))) >> (Line >> LL_SBS_REGISTER_PINPOS_SHFT));
1432 }
1433 
1434 /**
1435   * @}
1436   */
1437 
1438 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1439   * @{
1440   */
1441 
1442 /**
1443   * @brief  Return the device identifier
1444   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
1445   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
1446   */
LL_DBGMCU_GetDeviceID(void)1447 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1448 {
1449   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1450 }
1451 
1452 /**
1453   * @brief  Return the device revision identifier
1454   * @note This field indicates the revision of the device.
1455   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
1456   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1457   */
LL_DBGMCU_GetRevisionID(void)1458 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1459 {
1460   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1461 }
1462 
1463 /**
1464   * @brief  Enable the Debug Module during sleep mode
1465   * @rmtoll DBGMCU_CR    DBG_SLEEP      LL_DBGMCU_EnableDBGSleepMode
1466   * @retval None
1467   */
LL_DBGMCU_EnableDBGSleepMode(void)1468 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1469 {
1470   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1471 }
1472 
1473 /**
1474   * @brief  Disable the Debug Module during sleep mode
1475   * @rmtoll DBGMCU_CR    DBG_SLEEP      LL_DBGMCU_DisableDBGSleepMode
1476   * @retval None
1477   */
LL_DBGMCU_DisableDBGSleepMode(void)1478 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1479 {
1480   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1481 }
1482 
1483 /**
1484   * @brief  Indicate if the Debug Module during sleep mode is enabled
1485   * @rmtoll DBGMCU_CR    DBG_SLEEP      LL_DBGMCU_IsEnabledDBGSleepMode
1486   * @retval State of bit (1 or 0).
1487   */
LL_DBGMCU_IsEnabledDBGSleepMode(void)1488 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGSleepMode(void)
1489 {
1490   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP) == (DBGMCU_CR_DBG_SLEEP)) ? 1UL : 0UL);
1491 }
1492 
1493 /**
1494   * @brief  Enable the Debug Module during STOP mode
1495   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
1496   * @retval None
1497   */
LL_DBGMCU_EnableDBGStopMode(void)1498 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1499 {
1500   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1501 }
1502 
1503 /**
1504   * @brief  Disable the Debug Module during STOP mode
1505   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
1506   * @retval None
1507   */
LL_DBGMCU_DisableDBGStopMode(void)1508 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1509 {
1510   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1511 }
1512 
1513 /**
1514   * @brief  Indicate if the Debug Module during STOP mode is enabled
1515   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_IsEnabledDBGStopMode
1516   * @retval State of bit (1 or 0).
1517   */
LL_DBGMCU_IsEnabledDBGStopMode(void)1518 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStopMode(void)
1519 {
1520   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP) == (DBGMCU_CR_DBG_STOP)) ? 1UL : 0UL);
1521 }
1522 
1523 /**
1524   * @brief  Enable the Debug Module during STANDBY mode
1525   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
1526   * @retval None
1527   */
LL_DBGMCU_EnableDBGStandbyMode(void)1528 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1529 {
1530   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1531 }
1532 
1533 /**
1534   * @brief  Disable the Debug Module during STANDBY mode
1535   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
1536   * @retval None
1537   */
LL_DBGMCU_DisableDBGStandbyMode(void)1538 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1539 {
1540   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1541 }
1542 
1543 /**
1544   * @brief  Indicate if the Debug Module during STANDBY mode is enabled
1545   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_IsEnabledDBGStandbyMode
1546   * @retval State of bit (1 or 0).
1547   */
LL_DBGMCU_IsEnabledDBGStandbyMode(void)1548 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStandbyMode(void)
1549 {
1550   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY) == (DBGMCU_CR_DBG_STANDBY)) ? 1UL : 0UL);
1551 }
1552 
1553 /**
1554   * @brief  Configure the debug credentials reset type
1555   * @rmtoll DBGMCU_CR DCRT     LL_DBGMCU_SetDbgCredentialResetType
1556   * @param  Type This parameter can be one of the following values:
1557   *         @arg @ref LL_DBGMCU_DCRT_SYSTEM
1558   *         @arg @ref LL_DBGMCU_DCRT_POWER
1559   * @retval None
1560   */
LL_DBGMCU_SetDbgCredentialResetType(uint32_t Type)1561 __STATIC_INLINE void LL_DBGMCU_SetDbgCredentialResetType(uint32_t Type)
1562 {
1563   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DCRT, Type);
1564 }
1565 
1566 /**
1567   * @brief  Get the selected debug credentials reset type
1568   * @rmtoll DBGMCU_CR DCRT     LL_DBGMCU_GetDbgCredentialResetType
1569   * @retval Returned value is the debug credentials reset type:
1570   *         @arg @ref LL_DBGMCU_DCRT_SYSTEM
1571   *         @arg @ref LL_DBGMCU_DCRT_POWER
1572   */
LL_DBGMCU_GetDbgCredentialResetType(void)1573 __STATIC_INLINE uint32_t LL_DBGMCU_GetDbgCredentialResetType(void)
1574 {
1575   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DCRT));
1576 }
1577 
1578 /**
1579   * @brief  Enable the clock for Trace port
1580   * @rmtoll DBGMCU_CR    TRACECLKEN      LL_DBGMCU_EnableTraceClock
1581   * @retval None
1582   */
LL_DBGMCU_EnableTraceClock(void)1583 __STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
1584 {
1585   SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
1586 }
1587 
1588 /**
1589   * @brief  Disable the clock for Trace port
1590   * @rmtoll DBGMCU_CR    TRACECLKEN      LL_DBGMCU_DisableTraceClock
1591   * @retval None
1592   */
LL_DBGMCU_DisableTraceClock(void)1593 __STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
1594 {
1595   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
1596 }
1597 
1598 /**
1599   * @brief  Indicate if the clock for Trace port is enabled
1600   * @rmtoll DBGMCU_CR    TRACE_EN      LL_DBGMCU_IsEnabledTraceClock
1601   * @retval State of bit (1 or 0).
1602   */
LL_DBGMCU_IsEnabledTraceClock(void)1603 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
1604 {
1605   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN) == (DBGMCU_CR_TRACECLKEN)) ? 1UL : 0UL);
1606 }
1607 
1608 /**
1609   * @brief  Enable the clock for debug port
1610   * @rmtoll DBGMCU_CR    D1DBGCKEN      LL_DBGMCU_EnableDebugClock
1611   * @retval None
1612   */
LL_DBGMCU_EnableDebugClock(void)1613 __STATIC_INLINE void LL_DBGMCU_EnableDebugClock(void)
1614 {
1615   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBGCKEN);
1616 }
1617 
1618 /**
1619   * @brief  Disable the clock for debug port
1620   * @rmtoll DBGMCU_CR    D1DBGCKEN      LL_DBGMCU_DisableDebugClock
1621   * @retval None
1622   */
LL_DBGMCU_DisableDebugClock(void)1623 __STATIC_INLINE void LL_DBGMCU_DisableDebugClock(void)
1624 {
1625   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBGCKEN);
1626 }
1627 
1628 /**
1629   * @brief  Indicate if the clock for debug port is enabled
1630   * @rmtoll DBGMCU_CR    D1DBGCKEN      LL_DBGMCU_IsEnabledDebugClock
1631   * @retval State of bit (1 or 0).
1632   */
LL_DBGMCU_IsEnabledDebugClock(void)1633 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDebugClock(void)
1634 {
1635   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBGCKEN) != 0UL) ? 1UL : 0UL);
1636 }
1637 
1638 /**
1639   * @brief  Enable the external trigger output
1640   * @rmtoll DBGMCU_CR    TRGOEN      LL_DBGMCU_EnableTriggerOutput
1641   * @retval None
1642   */
LL_DBGMCU_EnableTriggerOutput(void)1643 __STATIC_INLINE void LL_DBGMCU_EnableTriggerOutput(void)
1644 {
1645   SET_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
1646 }
1647 
1648 /**
1649   * @brief  Disable the external trigger output
1650   * @rmtoll DBGMCU_CR    TRGOEN      LL_DBGMCU_DisableTriggerOutput
1651   * @retval None
1652   */
LL_DBGMCU_DisableTriggerOutput(void)1653 __STATIC_INLINE void LL_DBGMCU_DisableTriggerOutput(void)
1654 {
1655   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN);
1656 }
1657 
1658 /**
1659   * @brief  Indicate if the external trigger output is enabled
1660   * @rmtoll DBGMCU_CR    TRGOEN      LL_DBGMCU_IsEnabledTriggerOutput
1661   * @retval State of bit (1 or 0).
1662   */
LL_DBGMCU_IsEnabledTriggerOutput(void)1663 __STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTriggerOutput(void)
1664 {
1665   return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRGOEN) != 0UL) ? 1UL : 0UL);
1666 }
1667 
1668 /**
1669   * @brief  Freeze APB1 peripherals (group1 peripherals)
1670   * @rmtoll DBGMCU_APB1FZR DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
1671   * @param  Periphs This parameter can be a combination of the following values:
1672   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1673   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1674   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1675   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1676   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1677   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1678   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1679   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1680   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1681   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1682   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1683   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1684   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1685   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1686   * @retval None
1687   */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1688 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1689 {
1690   SET_BIT(DBGMCU->APB1FZR, Periphs);
1691 }
1692 
1693 /**
1694   * @brief  UnFreeze APB1 peripherals (group1 peripherals)
1695   * @rmtoll DBGMCU_APB1FZR DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1696   * @param  Periphs This parameter can be a combination of the following values:
1697   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1698   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1699   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
1700   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
1701   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1702   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
1703   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
1704   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
1705   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
1706   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
1707   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1708   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1709   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
1710   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
1711   * @retval None
1712   */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1713 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1714 {
1715   CLEAR_BIT(DBGMCU->APB1FZR, Periphs);
1716 }
1717 
1718 /**
1719   * @brief  Freeze APB4 peripherals (group1 peripherals)
1720   * @rmtoll DBGMCU_APB4FZR DBG_xxxx_STOP  LL_DBGMCU_APB4_GRP1_FreezePeriph
1721   * @param  Periphs This parameter can be a combination of the following values:
1722   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
1723   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
1724   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
1725   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
1726   *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
1727   *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
1728   * @retval None
1729   */
LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)1730 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)
1731 {
1732   SET_BIT(DBGMCU->APB4FZR, Periphs);
1733 }
1734 
1735 /**
1736   * @brief  UnFreeze APB4 peripherals (group1 peripherals)
1737   * @rmtoll DBGMCU_APB4FZR DBG_xxxx_STOP  LL_DBGMCU_APB4_GRP1_UnFreezePeriph
1738   * @param  Periphs This parameter can be a combination of the following values:
1739   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
1740   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
1741   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
1742   *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
1743   *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
1744   *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
1745   * @retval None
1746   */
LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)1747 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)
1748 {
1749   CLEAR_BIT(DBGMCU->APB4FZR, Periphs);
1750 }
1751 
1752 /**
1753   * @brief  freeze APB2 peripherals (group1 peripherals)
1754   * @rmtoll DBGMCU_APB2FZR DBG_xxxx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
1755   * @param  Periphs This parameter can be a combination of the following values:
1756   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1757   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
1758   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1759   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1760   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1761   * @retval None
1762   */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1763 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1764 {
1765   SET_BIT(DBGMCU->APB2FZR, Periphs);
1766 }
1767 
1768 /**
1769   * @brief  Unfreeze APB2 peripherals
1770   * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1771   * @param  Periphs This parameter can be a combination of the following values:
1772   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1773   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
1774   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1775   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1776   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1777   * @retval None
1778   */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1779 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1780 {
1781   CLEAR_BIT(DBGMCU->APB2FZR, Periphs);
1782 }
1783 
1784 /**
1785   * @brief  freeze AHB5 peripherals (group1 peripherals)
1786   * @rmtoll DBGMCU_AHB5FZR DBG_xxxx_STOP  LL_DBGMCU_AHB5_GRP1_FreezePeriph
1787   * @param  Periphs This parameter can be a combination of the following values:
1788   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA0_STOP
1789   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_STOP
1790   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA2_STOP
1791   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA3_STOP
1792   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA4_STOP
1793   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA5_STOP
1794   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA6_STOP
1795   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA7_STOP
1796   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA8_STOP
1797   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA9_STOP
1798   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA10_STOP
1799   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA11_STOP
1800   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA12_STOP
1801   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA13_STOP
1802   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA14_STOP
1803   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA15_STOP
1804   * @retval None
1805   */
LL_DBGMCU_AHB5_GRP1_FreezePeriph(uint32_t Periphs)1806 __STATIC_INLINE void LL_DBGMCU_AHB5_GRP1_FreezePeriph(uint32_t Periphs)
1807 {
1808   SET_BIT(DBGMCU->AHB5FZR, Periphs);
1809 }
1810 
1811 /**
1812   * @brief  Unfreeze AHB5 peripherals (group1 peripherals)
1813   * @rmtoll DBGMCU_AHB5FZR DBG_xxxx_STOP  LL_DBGMCU_AHB5_GRP1_UnFreezePeriph
1814   * @param  Periphs This parameter can be a combination of the following values:
1815   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA0_STOP
1816   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_STOP
1817   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA2_STOP
1818   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA3_STOP
1819   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA4_STOP
1820   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA5_STOP
1821   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA6_STOP
1822   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA7_STOP
1823   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA8_STOP
1824   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA9_STOP
1825   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA10_STOP
1826   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA11_STOP
1827   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA12_STOP
1828   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA13_STOP
1829   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA14_STOP
1830   *         @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA15_STOP
1831   * @retval None
1832   */
LL_DBGMCU_AHB5_GRP1_UnFreezePeriph(uint32_t Periphs)1833 __STATIC_INLINE void LL_DBGMCU_AHB5_GRP1_UnFreezePeriph(uint32_t Periphs)
1834 {
1835   CLEAR_BIT(DBGMCU->AHB5FZR, Periphs);
1836 }
1837 
1838 /**
1839   * @brief  freeze AHB1 peripherals (group1 peripherals)
1840   * @rmtoll DBGMCU_AHB1FZR DBG_xxxx_STOP  LL_DBGMCU_AHB1_GRP1_FreezePeriph
1841   * @param  Periphs This parameter can be a combination of the following values:
1842   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
1843   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
1844   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
1845   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
1846   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
1847   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
1848   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
1849   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
1850   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
1851   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
1852   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
1853   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
1854   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
1855   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
1856   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
1857   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
1858   * @retval None
1859   */
LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)1860 __STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs)
1861 {
1862   SET_BIT(DBGMCU->AHB1FZR, Periphs);
1863 }
1864 
1865 /**
1866   * @brief  Unfreeze AHB1 peripherals (group1 peripherals)
1867   * @rmtoll DBGMCU_AHB1FZR DBG_xxxx_STOP  LL_DBGMCU_AHB1_GRP1_UnFreezePeriph
1868   * @param  Periphs This parameter can be a combination of the following values:
1869   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP
1870   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP
1871   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP
1872   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP
1873   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP
1874   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP
1875   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP
1876   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP
1877   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP
1878   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP
1879   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP
1880   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP
1881   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP
1882   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP
1883   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP
1884   *         @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP
1885   * @retval None
1886   */
LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)1887 __STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1888 {
1889   CLEAR_BIT(DBGMCU->AHB1FZR, Periphs);
1890 }
1891 
1892 /**
1893   * @}
1894   */
1895 
1896 #if defined(VREFBUF)
1897 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
1898   * @{
1899   */
1900 
1901 /**
1902   * @brief  Enable Internal voltage reference
1903   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
1904   * @retval None
1905   */
LL_VREFBUF_Enable(void)1906 __STATIC_INLINE void LL_VREFBUF_Enable(void)
1907 {
1908   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1909 }
1910 
1911 /**
1912   * @brief  Disable Internal voltage reference
1913   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
1914   * @retval None
1915   */
LL_VREFBUF_Disable(void)1916 __STATIC_INLINE void LL_VREFBUF_Disable(void)
1917 {
1918   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1919 }
1920 
1921 /**
1922   * @brief  Enable high impedance (VREF+pin is high impedance)
1923   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
1924   * @retval None
1925   */
LL_VREFBUF_EnableHIZ(void)1926 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
1927 {
1928   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1929 }
1930 
1931 /**
1932   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
1933   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
1934   * @retval None
1935   */
LL_VREFBUF_DisableHIZ(void)1936 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
1937 {
1938   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
1939 }
1940 
1941 /**
1942   * @brief  Set the Voltage reference scale
1943   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
1944   * @param  Scale This parameter can be one of the following values:
1945   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1946   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1947   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1948   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1949   * @retval None
1950   */
LL_VREFBUF_SetVoltageScaling(uint32_t Scale)1951 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
1952 {
1953   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
1954 }
1955 
1956 /**
1957   * @brief  Get the Voltage reference scale
1958   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
1959   * @retval Returned value can be one of the following values:
1960   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
1961   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
1962   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
1963   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE3
1964   */
LL_VREFBUF_GetVoltageScaling(void)1965 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
1966 {
1967   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
1968 }
1969 
1970 /**
1971   * @brief  Check if Voltage reference buffer is ready
1972   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
1973   * @retval State of bit (1 or 0).
1974   */
LL_VREFBUF_IsVREFReady(void)1975 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
1976 {
1977   return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL);
1978 }
1979 
1980 /**
1981   * @brief  Get the trimming code for VREFBUF calibration
1982   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
1983   * @retval Between 0 and 0x3F
1984   */
LL_VREFBUF_GetTrimming(void)1985 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
1986 {
1987   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
1988 }
1989 
1990 /**
1991   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
1992   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
1993   * @param  Value Between 0 and 0x3F
1994   * @retval None
1995   */
LL_VREFBUF_SetTrimming(uint32_t Value)1996 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
1997 {
1998   WRITE_REG(VREFBUF->CCR, Value);
1999 }
2000 
2001 /**
2002   * @}
2003   */
2004 #endif /* VREFBUF */
2005 
2006 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
2007   * @{
2008   */
2009 
2010 /**
2011   * @brief  Set FLASH Latency
2012   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
2013   * @param  Latency This parameter can be one of the following values:
2014   *         @arg @ref LL_FLASH_LATENCY_0
2015   *         @arg @ref LL_FLASH_LATENCY_1
2016   *         @arg @ref LL_FLASH_LATENCY_2
2017   *         @arg @ref LL_FLASH_LATENCY_3
2018   *         @arg @ref LL_FLASH_LATENCY_4
2019   *         @arg @ref LL_FLASH_LATENCY_5
2020   *         @arg @ref LL_FLASH_LATENCY_6
2021   *         @arg @ref LL_FLASH_LATENCY_7
2022   * @retval None
2023   */
LL_FLASH_SetLatency(uint32_t Latency)2024 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
2025 {
2026   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
2027 }
2028 
2029 /**
2030   * @brief  Get FLASH Latency
2031   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
2032   * @retval Returned value can be one of the following values:
2033   *         @arg @ref LL_FLASH_LATENCY_0
2034   *         @arg @ref LL_FLASH_LATENCY_1
2035   *         @arg @ref LL_FLASH_LATENCY_2
2036   *         @arg @ref LL_FLASH_LATENCY_3
2037   *         @arg @ref LL_FLASH_LATENCY_4
2038   *         @arg @ref LL_FLASH_LATENCY_5
2039   *         @arg @ref LL_FLASH_LATENCY_6
2040   *         @arg @ref LL_FLASH_LATENCY_7
2041   */
LL_FLASH_GetLatency(void)2042 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
2043 {
2044   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
2045 }
2046 
2047 /**
2048   * @brief  Unlock the Flash
2049   * @rmtoll FLASH_KEYR    CUKEY       LL_FLASH_Unlock
2050   * @retval None
2051   */
LL_FLASH_Unlock(void)2052 __STATIC_INLINE void LL_FLASH_Unlock(void)
2053 {
2054   /* Unlock Flash */
2055   FLASH->KEYR = 0x45670123U;
2056   FLASH->KEYR = 0xCDEF89ABU;
2057 }
2058 
2059 /**
2060   * @brief  Lock the Flash
2061   * @rmtoll FLASH_CR    LOCK       LL_FLASH_Lock
2062   * @retval None
2063   */
LL_FLASH_Lock(void)2064 __STATIC_INLINE void LL_FLASH_Lock(void)
2065 {
2066   /* Lock Flash */
2067   SET_BIT(FLASH->CR, FLASH_CR_LOCK);
2068 }
2069 
2070 /**
2071   * @brief  Check if Flash is locked
2072   * @rmtoll FLASH_CR    LOCK       LL_FLASH_IsLocked
2073   * @retval State of bit (1 or 0).
2074   */
LL_FLASH_IsLocked(void)2075 __STATIC_INLINE uint32_t LL_FLASH_IsLocked(void)
2076 {
2077   return ((READ_BIT(FLASH->CR, FLASH_CR_LOCK) == FLASH_CR_LOCK) ? 1UL : 0UL);
2078 }
2079 
2080 /**
2081   * @brief  Unlock the Option Bytes update
2082   * @rmtoll FLASH_OPTKEYR    OCUKEY       LL_FLASH_OptionBytes_Unlock
2083   * @retval None
2084   */
LL_FLASH_OptionBytes_Unlock(void)2085 __STATIC_INLINE void LL_FLASH_OptionBytes_Unlock(void)
2086 {
2087   /* Unlock Option Bytes */
2088   FLASH->OPTKEYR = 0x08192A3BU;
2089   FLASH->OPTKEYR = 0x4C5D6E7FU;
2090 }
2091 
2092 /**
2093   * @brief  Lock the Option Bytes update
2094   * @rmtoll FLASH_OPTCR    OPTLOCK       LL_FLASH_OptionBytes_Lock
2095   * @retval None
2096   */
LL_FLASH_OptionBytes_Lock(void)2097 __STATIC_INLINE void LL_FLASH_OptionBytes_Lock(void)
2098 {
2099   /* Lock option bytes */
2100   SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK);
2101 }
2102 
2103 /**
2104   * @brief  Check if Option Bytes update is locked
2105   * @rmtoll FLASH_OPTCR    OPTLOCK       LL_FLASH_OptionBytes_IsLocked
2106   * @retval State of bit (1 or 0).
2107   */
LL_FLASH_OptionBytes_IsLocked(void)2108 __STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsLocked(void)
2109 {
2110   return ((READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == FLASH_OPTCR_OPTLOCK) ? 1UL : 0UL);
2111 }
2112 
2113 /**
2114   * @brief  Enable Option Bytes programming
2115   * @rmtoll FLASH_OPTCR    PG_OPT       LL_FLASH_OptionBytes_EnableProg
2116   * @retval None
2117   */
LL_FLASH_OptionBytes_EnableProg(void)2118 __STATIC_INLINE void LL_FLASH_OptionBytes_EnableProg(void)
2119 {
2120   /* Set PG_OPT Bit */
2121   SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT);
2122 }
2123 
2124 /**
2125   * @brief  Disable Option Bytes programming
2126   * @rmtoll FLASH_OPTCR    PG_OPT       LL_FLASH_OptionBytes_DisableProg
2127   * @retval None
2128   */
LL_FLASH_OptionBytes_DisableProg(void)2129 __STATIC_INLINE void LL_FLASH_OptionBytes_DisableProg(void)
2130 {
2131   /* Clear PG_OPT Bit */
2132   CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT);
2133 }
2134 
2135 /**
2136   * @brief  Check if Option Bytes programming is enabled
2137   * @rmtoll FLASH_OPTCR    PG_OPT       LL_FLASH_OptionBytes_IsEnabledProg
2138   * @retval State of bit (1 or 0).
2139   */
LL_FLASH_OptionBytes_IsEnabledProg(void)2140 __STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsEnabledProg(void)
2141 {
2142   return ((READ_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OPT) == FLASH_OPTCR_PG_OPT) ? 1UL : 0UL);
2143 }
2144 
2145 /**
2146   * @brief  Check if operation pending
2147   * @rmtoll FLASH_SR    QW       LL_FLASH_IsPendingOperation
2148   * @retval State of bit (1 or 0).
2149   */
LL_FLASH_IsPendingOperation(void)2150 __STATIC_INLINE uint32_t LL_FLASH_IsPendingOperation(void)
2151 {
2152   return ((READ_BIT(FLASH->SR, FLASH_SR_QW) == FLASH_SR_QW) ? 1UL : 0UL);
2153 }
2154 
2155 /**
2156   * @brief  Enable the I2C in Flash User Option bytes
2157   * @rmtoll FLASH_OBW2SR    I2C_NI3C       LL_FLASH_OptionBytes_EnableI2C
2158   * @retval None
2159   */
LL_FLASH_OptionBytes_EnableI2C(void)2160 __STATIC_INLINE void LL_FLASH_OptionBytes_EnableI2C(void)
2161 {
2162   /* Set I2C_N3C Bit */
2163   SET_BIT(FLASH->OBW2SRP, FLASH_OBW2SRP_I2C_NI3C);
2164 }
2165 
2166 /**
2167   * @brief  Enable the I3C in Flash User Option bytes
2168   * @rmtoll FLASH_OBW2SR    I2C_NI3C       LL_FLASH_OptionBytes_EnableI3C
2169   * @retval None
2170   */
LL_FLASH_OptionBytes_EnableI3C(void)2171 __STATIC_INLINE void LL_FLASH_OptionBytes_EnableI3C(void)
2172 {
2173   /* Clear I2C_N3C Bit */
2174   CLEAR_BIT(FLASH->OBW2SRP, FLASH_OBW2SRP_I2C_NI3C);
2175 }
2176 
2177 /**
2178   * @brief  Check if I2C is enabled in Flash User Option Bytes
2179   * @rmtoll FLASH_OBW2SR    I2C_NI3C       LL_FLASH_OptionBytes_IsI2CEnabled
2180   * @retval State of bit (1 or 0).
2181   */
LL_FLASH_OptionBytes_IsI2CEnabled(void)2182 __STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsI2CEnabled(void)
2183 {
2184   return ((READ_BIT(FLASH->OBW2SR, FLASH_OBW2SR_I2C_NI3C) == FLASH_OBW2SR_I2C_NI3C) ? 1UL : 0UL);
2185 }
2186 
2187 /**
2188   * @brief  Check if I3C is enabled in Flash User Option Bytes
2189   * @rmtoll FLASH_OBW2SR    I2C_NI3C       LL_FLASH_OptionBytes_IsI3CEnabled
2190   * @retval State of bit (1 or 0).
2191   */
LL_FLASH_OptionBytes_IsI3CEnabled(void)2192 __STATIC_INLINE uint32_t LL_FLASH_OptionBytes_IsI3CEnabled(void)
2193 {
2194   return ((READ_BIT(FLASH->OBW2SR, FLASH_OBW2SR_I2C_NI3C) == 0U) ? 1UL : 0UL);
2195 }
2196 
2197 /**
2198   * @}
2199   */
2200 
2201 /**
2202   * @}
2203   */
2204 
2205 /**
2206   * @}
2207   */
2208 
2209 #endif /* defined (FLASH) || defined (SBS) || defined (DBGMCU) || defined (VREFBUF) */
2210 
2211 /**
2212   * @}
2213   */
2214 
2215 #ifdef __cplusplus
2216 }
2217 #endif
2218 
2219 #endif /* STM32H7RSxx_LL_SYSTEM_H */
2220