Searched refs:LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 (Results 1 – 2 of 2) sorted by relevance
496 #define LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q/2… macro503 #define LL_RCC_RNG_CLKSOURCE_PLL1Q LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2
752 case LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2: /* PLL1Q/2 clock used as RNG clock source */ in LL_RCC_GetRNGClockFreq()
