Searched refs:LL_RCC_PREDIV_DIV_5 (Results 1 – 6 of 6) sorted by relevance
101 … ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
95 … ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
117 … ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
490 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided … macro
458 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divide… macro
813 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided … macro
