Searched refs:LL_RCC_PREDIV_DIV_2 (Results 1 – 6 of 6) sorted by relevance
115 …UE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \124 …IV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))378 UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; in LL_PLL_ConfigSystemClock_HSI()
99 …UE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \322 UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; in LL_PLL_ConfigSystemClock_HSI()
93 …UE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \309 UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; in LL_PLL_ConfigSystemClock_HSI()
455 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divide… macro472 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided … macro
487 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided … macro
810 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided … macro
